CN113517218B - Method for manufacturing semiconductor bit line contact, method for manufacturing bit line and memory - Google Patents
Method for manufacturing semiconductor bit line contact, method for manufacturing bit line and memory Download PDFInfo
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- CN113517218B CN113517218B CN202010275218.3A CN202010275218A CN113517218B CN 113517218 B CN113517218 B CN 113517218B CN 202010275218 A CN202010275218 A CN 202010275218A CN 113517218 B CN113517218 B CN 113517218B
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 68
- 229920005591 polysilicon Polymers 0.000 claims abstract description 57
- 238000005530 etching Methods 0.000 claims abstract description 19
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 238000001020 plasma etching Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 155
- 239000011241 protective layer Substances 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
Abstract
The application discloses a method for manufacturing a semiconductor bit line contact, a method for manufacturing a bit line and a memory, wherein the method for manufacturing the semiconductor bit line contact comprises the following steps: providing a substrate, and sequentially depositing a sacrificial layer and a bit line groove mask layer on the substrate; fabricating a recess on the substrate based on the bit line recess mask layer; depositing a polysilicon layer over the recess and the substrate; plasma etching the polysilicon layer so that the top surface of the remaining polysilicon layer is substantially flush with the top surface of the substrate; and removing the sacrificial layer. According to the manufacturing method of the semiconductor bit line contact, the sacrificial layer is deposited on the substrate, the sacrificial layer is etched at the same time when the polycrystalline silicon layer is etched, and the etching is stopped until the sacrificial layer is etched to a thickness of a preset proportion, so that the top surface of the polycrystalline silicon layer is flush with the top surface of the substrate.
Description
Technical Field
The present application relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor bit line contact, a method for manufacturing a bit line, and a memory.
Background
As shown in fig. 1, the process flow chart of the prior art method for manufacturing the DRAM (Dynamic Random Access Memory ) bit line comprises the following steps: 1) Photoetching the bit line groove mask layer 2 on the substrate 1; 2) Etching the substrate 1 to form a groove 3; 3) Depositing a polysilicon layer 4; 4) Back etching is carried out on the polysilicon layer 4; 5) And depositing a conducting wire layer and an insulating layer on the residual polycrystalline silicon layer 4 and the substrate 1 in sequence, and etching the insulating layer, the conducting wire layer and the residual polycrystalline silicon layer 4 to form bit lines. Wherein steps 1) to 4) are steps of a method for manufacturing a DRAM bit line contact. As shown in fig. 1, when the polysilicon layer 4 is etched back in the bit line contact (DLC, data Line Contact), the top surface of the polysilicon layer 4 is lower than the top surface of the substrate 1, thereby forming a recess 7, which results in an inability to planarize (level) the polysilicon layer 4 and the substrate 1.
DRAM Data lines (Data lines) used in the fabrication of buried gates (BurriedGATE) are planarized by etching back polysilicon and Field oxide (Field) surfaces. The data line connected with the Active terminal is connected through the polysilicon of the bit line contact, and the polysilicon is not arranged on the field oxide layer and is directly connected with the data line. If a step difference is generated between the polysilicon surface and the field oxide surface during the polysilicon back etching, the polysilicon shape (Profile) of the data line becomes a wavy shape with a positive slope (Posi-slope) or a negative slope (naga-slope), which is Not a satisfactory data line, and affects the yield, and may further cause a problem of a field oxide Shoulder (formed Shoulder) being inclined, and causing a problem of Not opening (Not-open) during the subsequent formation of the bit line contact.
Disclosure of Invention
The application aims to provide a manufacturing method of a semiconductor bit line contact, a manufacturing method of a bit line and a memory. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
According to an aspect of an embodiment of the present application, there is provided a method of manufacturing a semiconductor bit line contact, including:
providing a substrate, and sequentially depositing a sacrificial layer and a bit line groove mask layer on the substrate;
fabricating a recess on the substrate based on the bit line recess mask layer;
depositing a polysilicon layer over the recess and the substrate;
plasma etching the polysilicon layer so that the top surface of the remaining polysilicon layer is substantially flush with the top surface of the substrate;
and removing the sacrificial layer.
According to an aspect of an embodiment of the present application, there is provided a method of manufacturing a semiconductor bit line, including:
the steps of the above method;
sequentially depositing a wire layer and an insulating layer on the remaining polysilicon layer and the substrate;
forming a bit line mask on the insulating layer;
and etching the insulating layer, the wire layer and the residual polysilicon layer through the bit line mask to form bit lines.
According to an aspect of an embodiment of the present application, there is provided a semiconductor memory including:
the substrate comprises more than one active area isolated from each other and at least one groove, wherein the active area is exposed out of the groove;
at least one bit line on the substrate;
the bit line comprises a polycrystalline silicon layer, a conducting wire layer and an insulating layer, wherein the polycrystalline silicon layer is in contact with the active region, the conducting wire layer is located on the polycrystalline silicon layer, and the top surface of the polycrystalline silicon layer is basically flush with the top surface of the substrate.
According to an aspect of an embodiment of the present application, there is provided an electronic device including the above semiconductor memory.
One of the technical solutions provided in one aspect of the embodiments of the present application may include the following beneficial effects:
according to the manufacturing method of the semiconductor bit line contact, the sacrificial layer is deposited on the substrate, the sacrificial layer is etched at the same time when the polycrystalline silicon layer is etched, and the etching is stopped until the sacrificial layer is etched by the thickness of a preset proportion, so that the top surface of the polycrystalline silicon layer is flush with the top surface of the substrate, and the problem that the top surface of the polycrystalline silicon layer and the top surface of the substrate cannot be leveled due to the fact that the top surface of the etched polycrystalline silicon layer is lower than the top surface of the substrate is avoided.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the embodiments of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
FIG. 1 is a process flow diagram of a prior art method of fabricating a semiconductor bit line;
FIG. 2 illustrates a flow chart of a method of fabricating a semiconductor bit line contact in accordance with one embodiment of the present application;
FIG. 3 illustrates a flow chart of a method of fabricating a semiconductor bit line in accordance with one embodiment of the present application;
FIG. 4 shows a schematic diagram of the structure after deposition of a sacrificial layer and a bitline recess mask layer on a substrate in accordance with one embodiment of the application;
FIG. 5 shows a schematic diagram of the structure shown in FIG. 4 after forming a trench in the structure;
FIG. 6 shows a schematic view of the structure shown in FIG. 5 after forming grooves therein;
FIG. 7 shows a schematic diagram of the structure after depositing a polysilicon layer over the structure shown in FIG. 6;
FIG. 8 shows a schematic diagram of the structure shown in FIG. 7 after etching away a portion of the polysilicon layer;
FIG. 9 shows a schematic diagram of the structure shown in FIG. 8 after removal of the remaining sacrificial layer;
fig. 10 shows a schematic structure of a semiconductor memory according to an embodiment of the present application.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
As shown in fig. 1, one embodiment of the present application provides a method for manufacturing a semiconductor bit line contact, comprising:
a substrate 1 is provided and a sacrificial layer 5 and a bitline recess mask layer 2 are sequentially deposited on the substrate 1 as shown in fig. 4.
The substrate may be a semiconductor substrate, such as a Si substrate. In particular, according to one embodiment of the present application, a substrate on which a BCAT (buried channel array transistor) structure has been formed may be used. A silicon nitride protective layer may be formed on the substrate.
The bit line trench mask layer 2 may be formed of a hard mask material (SOH).For example, the bit line recess mask layer 2 may be a carbon bit line recess mask layer. The thickness of the polysilicon layer 4 may beThe thickness of the sacrificial layer 5 may be set to 15% of the polysilicon. The sacrificial layer 5 comprises a dielectric material with an etch ratio to polysilicon exceeding 1:30. The sacrificial layer 5 may be SiN or SiN/POLY/TiN stack. The sacrificial layer 5 may also be a material support such as silicon oxide, polysilicon, photoresist, etc., and the present embodiment uses a silicon oxide layer as the sacrificial layer.
The thickness of the sacrificial layer 5 is preset to 10% -20% of the thickness of the polysilicon layer 4, and the over-etching is set to 10% -20% at the same time, and is opposite to the ratio of the thickness of the sacrificial layer to the thickness of the polysilicon.
The overetch may be 10% -16% and equal to the ratio of the thickness of the sacrificial layer 5 to the thickness of the polysilicon layer 4.
The substrate 1 surface further comprises a SiN protective layer.
A recess 3 is fabricated on the substrate 1 based on the bit line recess mask layer 2.
Specifically, the bit line recess mask layer 2 is lithographically etched to form trenches 6, as shown in fig. 5. The sacrificial layer 5 and the substrate 1 are etched through the trench 6, forming a recess 3 on the substrate 1, as shown in fig. 6. The depth of the groove 3 may beWhen the sacrificial layer 5 is etched 10-15% of the thickness, a recess 3 (recess) is created. A polysilicon layer 4 is deposited over the recess 3 and the substrate 1 as shown in fig. 7.
The polysilicon layer 4 is plasma etched so that the top surface of the remaining polysilicon layer 4 is substantially flush with the top surface of the substrate 1, as shown in fig. 8. The top surface of the polysilicon layer 4 is not more than 5% different in height from the top surface of the substrate 1.
In some embodiments, plasma etching polysilicon layer 4 comprises: when the plasma etching reaches the sacrificial layer 5, the plasma etching is stopped.
In some embodiments, etching the polysilicon layer 4 and the sacrificial layer 5 simultaneously includes: the polysilicon layer 4 and the sacrificial layer 5 are etched simultaneously by a plasma etching process.
In some embodiments, the etching time is controlled by the endpoint detection method when the polysilicon layer 4 and the sacrificial layer 5 are etched simultaneously.
The sacrificial layer 5 is removed as shown in fig. 9.
In some embodiments, removing the remaining sacrificial layer 5 comprises: the remaining sacrificial layer 5 is removed by a wet etching process.
In certain embodiments, the predetermined proportion is 15%.
In some embodiments, the sacrificial layer 5 is replaced with a layer of a replacement material, wherein the etch selectivity of the replacement material to silicon nitride and polysilicon is greater than 30:1.
Another embodiment of the present application also provides a method for manufacturing a semiconductor bit line, including:
the step of the above-mentioned semiconductor bit line contact manufacturing approach;
a wire layer 8 and an insulating layer 9 are deposited in sequence on the remaining polysilicon layer 4 and the substrate 1.
A bit line mask is formed on the insulating layer 9.
The bit lines are formed by etching the insulating layer 8, the wire layer 9 and the remaining polysilicon layer 4 through a bit line mask, as shown in fig. 10.
As shown in fig. 10, the present embodiment also provides a semiconductor memory including:
a substrate 1, wherein the substrate 1 comprises more than one active area isolated from each other and at least one groove 3, and the groove 3 exposes the active area;
at least one bit line on the substrate 1;
wherein the bit line comprises a polysilicon layer 4 in contact with the active region, a conductive line layer 8 and an insulating layer 9 on the polysilicon layer 4, the top surface of the polysilicon layer 4 of the bit line in the recess 3 being substantially flush with the top surface of the substrate 1. The top surface of the polysilicon layer 4 is not more than 5% different in height from the top surface of the substrate 1.
In some embodiments, there are buried channel transistors on the substrate 1.
The semiconductor memory may be a DRAM.
The embodiment also provides an electronic device comprising the semiconductor memory. The electronic equipment comprises a smart phone, a computer, a tablet personal computer, a wearable intelligent device, an artificial intelligent device, a mobile power supply and the like.
According to the manufacturing method of the semiconductor bit line contact, the sacrificial layer is deposited on the substrate, the sacrificial layer is etched at the same time when the polycrystalline silicon layer is etched, and the etching is stopped until the sacrificial layer is etched by a thickness of a preset proportion, so that the top surface of the polycrystalline silicon layer is flush with the top surface of the substrate, and the problem that the top surface of the polycrystalline silicon layer and the top surface of the substrate cannot be leveled due to the fact that the top surface of the etched polycrystalline silicon layer is lower than the top surface of the substrate is avoided; in addition, the inclination of the Shoulder (holder) of the substrate can be avoided, the problem of non-opening of the CC (Not Open is) is solved, and the problem of abnormal shape (Profile) of the polysilicon layer caused by leveling is solved.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (18)
1. A method of fabricating a semiconductor bit line contact, comprising:
providing a substrate, and sequentially depositing a sacrificial layer and a bit line groove mask layer on the substrate;
fabricating a recess on the substrate based on the bit line recess mask layer;
depositing a polysilicon layer over the recess and the substrate;
plasma etching the polysilicon layer so that the top surface of the remaining polysilicon layer is substantially flush with the top surface of the substrate;
and removing the sacrificial layer.
2. The method of claim 1, wherein the sacrificial layer comprises: dielectric material with an etch ratio to Poly exceeding 1:30.
3. The method of claim 2, wherein the sacrificial layer is SiN or SiN/Poly/TiN stack.
4. The method of claim 1, wherein the substrate surface further comprises a SiN protective layer.
5. The method of claim 1, wherein the thickness of the sacrificial layer is preset to 10% -20% of the thickness of the polysilicon, while the overetch is set to 10% -20% and is opposite to the ratio of the sacrificial layer to the thickness of the polysilicon.
6. The method of claim 5, wherein the over etch is 10% -16% and is equal to the ratio of sacrificial layer to polysilicon thickness.
7. The method of claim 1, wherein the plasma etching the polysilicon layer comprises: when the plasma etching reaches the sacrificial layer, the plasma etching is stopped.
8. The method of claim 1, wherein the fabricating a groove in the substrate comprises:
photoetching the bit line groove mask layer to form a groove;
and etching the sacrificial layer and the substrate through the groove, and forming a groove on the substrate.
9. The method of claim 1, wherein simultaneously etching the polysilicon layer and the sacrificial layer comprises: and simultaneously etching the polysilicon layer and the sacrificial layer through a plasma etching process.
10. The method of claim 1, wherein removing the remaining sacrificial layer comprises: and removing the residual sacrificial layer through a wet etching process.
11. The method of claim 1, wherein a top surface of the polysilicon layer is not more than 5% different from a top surface of the substrate.
12. A method of fabricating a semiconductor bit line, comprising:
the method of any one of claims 1-11;
sequentially depositing a wire layer and an insulating layer on the remaining polysilicon layer and the substrate;
forming a bit line mask on the insulating layer;
and etching the insulating layer, the wire layer and the residual polysilicon layer through the bit line mask to form bit lines.
13. A semiconductor memory device, comprising:
the substrate comprises more than one active area isolated from each other and at least one groove, wherein the active area is exposed out of the groove;
at least one bit line on the substrate;
the bit line comprises a polycrystalline silicon layer, a conducting wire layer and an insulating layer, wherein the polycrystalline silicon layer is in contact with the active region, the conducting wire layer is located on the polycrystalline silicon layer, and the top surface of the polycrystalline silicon layer is basically flush with the top surface of the substrate.
14. The semiconductor memory of claim 13, wherein the substrate has a buried channel transistor thereon.
15. The semiconductor memory of claim 13, wherein a top surface of the polysilicon layer is not more than 5% different from a top surface of the substrate.
16. The semiconductor memory according to claim 13, wherein the semiconductor memory is a DRAM.
17. An electronic device comprising the semiconductor memory of claim 14.
18. The electronic device of claim 17, comprising a smart phone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010275218.3A CN113517218B (en) | 2020-04-09 | 2020-04-09 | Method for manufacturing semiconductor bit line contact, method for manufacturing bit line and memory |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010275218.3A CN113517218B (en) | 2020-04-09 | 2020-04-09 | Method for manufacturing semiconductor bit line contact, method for manufacturing bit line and memory |
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| CN113517218A CN113517218A (en) | 2021-10-19 |
| CN113517218B true CN113517218B (en) | 2023-12-08 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030000967A (en) * | 2001-06-27 | 2003-01-06 | 주식회사 하이닉스반도체 | Method for forming bitline of semiconductor device |
| JP2013201414A (en) * | 2012-02-23 | 2013-10-03 | Ps4 Luxco S A R L | Semiconductor device and manufacturing method of the same |
| CN109935588A (en) * | 2017-12-18 | 2019-06-25 | 联华电子股份有限公司 | Memory and preparation method thereof |
| CN110148596A (en) * | 2018-02-12 | 2019-08-20 | 联华电子股份有限公司 | Bit line gate structure of dynamic random access memory and forming method thereof |
| CN110690193A (en) * | 2019-09-30 | 2020-01-14 | 福建省晋华集成电路有限公司 | Semiconductor memory device and process method |
-
2020
- 2020-04-09 CN CN202010275218.3A patent/CN113517218B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030000967A (en) * | 2001-06-27 | 2003-01-06 | 주식회사 하이닉스반도체 | Method for forming bitline of semiconductor device |
| JP2013201414A (en) * | 2012-02-23 | 2013-10-03 | Ps4 Luxco S A R L | Semiconductor device and manufacturing method of the same |
| CN109935588A (en) * | 2017-12-18 | 2019-06-25 | 联华电子股份有限公司 | Memory and preparation method thereof |
| CN110148596A (en) * | 2018-02-12 | 2019-08-20 | 联华电子股份有限公司 | Bit line gate structure of dynamic random access memory and forming method thereof |
| CN110690193A (en) * | 2019-09-30 | 2020-01-14 | 福建省晋华集成电路有限公司 | Semiconductor memory device and process method |
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