CN205621740U - Novel concave groove gate MISFET device of gaN base - Google Patents
Novel concave groove gate MISFET device of gaN base Download PDFInfo
- Publication number
- CN205621740U CN205621740U CN201620226766.6U CN201620226766U CN205621740U CN 205621740 U CN205621740 U CN 205621740U CN 201620226766 U CN201620226766 U CN 201620226766U CN 205621740 U CN205621740 U CN 205621740U
- Authority
- CN
- China
- Prior art keywords
- layer
- gan
- alloy
- epitaxial layer
- gan base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 230000004888 barrier function Effects 0.000 claims abstract description 5
- 229910002704 AlGaN Inorganic materials 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 19
- 238000005036 potential barrier Methods 0.000 claims description 16
- 229910001020 Au alloy Inorganic materials 0.000 claims description 14
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 6
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052681 coesite Inorganic materials 0.000 claims description 4
- 229910052906 cristobalite Inorganic materials 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 229910052682 stishovite Inorganic materials 0.000 claims description 4
- 229910052905 tridymite Inorganic materials 0.000 claims description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- 229910001182 Mo alloy Inorganic materials 0.000 claims description 2
- 229910001252 Pd alloy Inorganic materials 0.000 claims description 2
- 229910001260 Pt alloy Inorganic materials 0.000 claims description 2
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 32
- 230000008569 process Effects 0.000 abstract description 9
- 238000001039 wet etching Methods 0.000 abstract description 6
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000011982 device technology Methods 0.000 abstract 1
- 238000001035 drying Methods 0.000 abstract 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 39
- 229910002601 GaN Inorganic materials 0.000 description 38
- 238000010586 diagram Methods 0.000 description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 6
- 230000004044 response Effects 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 230000037230 mobility Effects 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical group F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 229910017083 AlN Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000026267 regulation of growth Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The utility model provides a semiconductor device technology of preparing, concretely relates to novel concave groove gate MISFET device of gaN base includes the substrate from lower to upper in proper order, the stress buffer layer, the gaN epitaxial layer, the alGaN barrier layer, the reaction sculpture forms the recess, growth alN thin layer on the throne, grid insulating medium layer, both ends form source electrode and drain electrode, deposit grid on the insulating layer of recess channel department. The utility model discloses simple process, the damage that leads to the fact the gate region territory in the time of can solving traditional dry process or wet etching recess well can form the high -quality device performance of MIS interface in order to promote concave groove gate MISFET, if reduce grid leakage current and conducting resistance and improve threshold voltage stability etc.
Description
Technical field
This utility model relates to the technical field of semiconductor device, more particularly, to a kind of novel GaN base notched gates MISFET device.
Background technology
Gallium nitride (GaN) material has that energy gap is big, breakdown field strength is high, electronics saturation drift velocity is big, thermal conductivity advantages of higher, is very suitable for making high-power, high frequency, high temperature power electronic devices.In applied power electronics field, in order to meet fail safe, field-effect transistor (FET) device must realize normally-off (also known as enhancement mode) work, and needs at least 4-5V at some occasion threshold voltage.And for conventional AlGaN/GaN HFET (HFET), due to interface high concentration, the existence of the two-dimensional electron gas (2DEG) of high mobility, even if when additional grid voltage is zero, device is also at opening (normally on device).In order to solve these problems, the isolated-gate field effect transistor (IGFET) (MISFET) using MIS structure is an effective technology path.
GaN base notched gates MISFET device, on the premise of retaining access area 2DEG concentration (not sacrificing break-over of device characteristic), reduces the 2DEG below grid when removing zero-bias the most completely, and MIS structure grid can be used to achieve high threshold voltage.But, traditional groove preparation is to use inductively coupled plasma (ICP) or reactive ion etching (RIE) equipment to perform etching the AlGaN potential barrier below grid.Owing to the lattice of channel region can be caused damage by the use of plasma, and then affect the reliability and stability at MIS interface.Additionally, the selective etching ratio of AlGaN and GaN material is less, the self-stopping technology of etching the most relatively difficult to achieve, process repeatability is poor.The lifting of these 2 channel mobilities limiting this mixed type MISFET, thus add the conducting resistance of device.
Numeral wet etching utilizes repeatedly oxidation and chemical solution corrosion can obtain the normally-off notched gates MISFET device that technique is controlled, and can effectively remove plasma damage.But recess edge is the most neat, area of grid has cone-shaped AlGaN residual, the surface of GaN channel layer also can observe substantial amounts of etching hole.Use selection area epitaxy technology to prepare groove and can also remove the plasma damage of area of grid, improve MIS interfacial characteristics, but epitaxy technique is more complicated.It is therefore desirable to seek a kind of selective area growth interface guard method, to overcome the shortcoming in traditional handicraft, thus obtain higher mobility and threshold voltage.Owing to the extension of GaN base material is to realize under its synthesis rate quasi-balanced state slightly larger than decomposition rate, therefore, nitrogen is only had in chemical gas-phase deposition system, hydrogen or nitrogen and the mixed gas of hydrogen and when there is no growth source, the decomposition rate of GaN base material can be made slightly larger than synthesis rate by growth regulation parameter, thus under the auxiliary of mask, the AlGaN epitaxial layer of area of grid is successively decomposed along the inverse process of growth response, it is thus achieved that groove.
Summary of the invention
This utility model is to overcome at least one defect described in above-mentioned prior art, a kind of novel GaN base notched gates MISFET device is provided, damage when conventional dry or wet etching groove, area of grid caused can be solved well, high-quality MIS interface can be formed to promote the device performance of notched gates MISFET.
For solving above-mentioned technical problem, the technical solution adopted in the utility model is: a kind of novel GaN base notched gates MISFET device, wherein, includes substrate the most successively, stress-buffer layer, GaN epitaxial layer, AlGaN potential barrier, reactive ion etching forms groove, growing AIN thin layer in place, gate insulator dielectric layer, two ends form source electrode and drain electrode, and the insulating barrier at recess channel deposits grid.
When preparing above-mentioned device, available following method.
The preparation method of a kind of novel GaN base notched gates MISFET, wherein, utilizes the inverse process of GaN material growth response to be removed by area of grid AlGaN and obtain groove, and promotes MIS interface quality by depositing Al N thin layer in place；Specifically comprise the steps of
S1, at Grown stress-buffer layer；
S2, on stress-buffer layer grow GaN epitaxial layer；
S3, in GaN epitaxial layer (3), grow AlGaN potential barrier；
S4, in AlGaN potential barrier deposit one layer of SiO2, as mask layer；
S5, method by photoetching and wet etching, remove the mask layer of area of grid；
S6, the AlGaN potential barrier of removal area of grid；
S7, growing AIN thin layer in place；
S8, deposition gate insulator dielectric layer；
S9, dry etching complete device isolation, etch source electrode and drain ohmic contact region simultaneously；
S10, on source electrode and drain region are deposited with source electrode and drain ohmic contact metal；
S11, on groove dielectric layer area of grid evaporation gate metal.
Concrete, in described step S6, utilize the inverse process of GaN material growth response to be removed by area of grid AlGaN and obtain groove；In described step S7, depositing Al N thin layer in place promotes MIS interface quality.
Described substrate is any one in Si substrate, Sapphire Substrate, silicon carbide substrates, GaN self-supported substrate.
Described stress-buffer layer is any one of AlN, AlGaN, GaN or combines；Stress buffer layer thickness is 10 nm ~ 100 μm.
Described GaN epitaxial layer is GaN epitaxial layer or the high resistant GaN epitaxial layer of doping of involuntary doping, and the doped chemical of described doping resistive formation is carbon or ferrum；GaN epitaxial layer thickness is 100 nm ~ 100 μm.
Described epitaxial layer is AlGaN potential barrier, and AlGaN layer thickness is 5-50 nm, and al composition varying concentrations.
Described AlGaN potential barrier material can also be a kind of or the most several combination in AlInN, InGaN, AlInGaN, AlN.
In described AlGaN potential barrier, and can also insert AlN thin layer between GaN layer, thickness is 0-10 nm.
Described epitaxial layer is high-quality AlN layer, and thickness is 0-10 nm；Described insulating medium layer is Al2O3、HfO2、SiO2Or SiN etc., thickness is 1-100 nm；Form AlN/ dielectric layer stacked structure.
Described source electrode and drain material are Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy；Grid material is Ni/Au alloy, Pt/Al alloy, Pd/Au alloy or TiN/Ti/Au alloy；
The growing method of the AlGaN epitaxial layer in the stress-buffer layer in described step S1, the GaN epitaxial layer in step S2, step S3 and the AlN in step S7 is Metalorganic Chemical Vapor Deposition, molecular beam epitaxy contour quality film formation method；In described step S4, the growing method of mask layer is plasma enhanced chemical vapor deposition method, atomic layer deposition method, physical vaporous deposition or magnetron sputtering method；The recess etch method of described step S6 is to utilize the mixed gas of nitrogen, hydrogen or nitrogen and hydrogen to make AlGaN epitaxial layer successively decompose in metal organic chemical vapor deposition system.
Alternatively, it is also possible to utilize following method step to express this utility model.
Area of grid AlGaN is removed and obtains groove by the inverse process utilizing GaN material growth response, and promotes MIS interface quality by depositing Al N thin layer in place.Specifically comprise the steps of
1. provide and need the AlGaN/GaN heterojunction material carrying out groove grids etching；
2., at described deposited on materials one dielectric layer, form mask layer；
3. on described mask layer, utilize photoetching development technology, manifest area of grid；
4. use chemical solution to remove the mask material of area of grid, retain the mask material in other regions, it is achieved mask layer is graphical；
5. under the auxiliary of described mask pattern, it is achieved recess etch.
6., under the auxiliary of described mask pattern, grow one layer of AlN thin layer in place in grooved area.
Further, in described step 1, described substrate is the epitaxial layer substrate with heterogeneity.
In described step 2, dielectric layer is to be formed by plasma enhanced chemical vapor deposition or ald or physical vapour deposition (PVD) or magnetron sputtering.Described dielectric layer is SiO2Or SiN.
In described step 3, described photoresist is positivity or negative photoresist.
In described step 4, it is hydrofluoric acid aqueous solution or Fluohydric acid. and the mixed solution of ammonium fluoride that described dielectric layer removes the chemical solution used.
In described step 5, described recess etch is Metalorganic Chemical Vapor Deposition or molecular beam epitaxy.Reacting gas is H2、N2, or H2With N2Mixed gas.
In described step 6, described AlN thin layer be grown to Metalorganic Chemical Vapor Deposition or molecular beam epitaxy in place.
Compared with prior art, provide the benefit that: a kind of novel GaN base notched gates MISFET device of this utility model, obtain groove owing to utilizing the inverse process of GaN material growth response to be removed by area of grid AlGaN, damage when conventional dry or wet etching groove, area of grid caused can be solved well.The method need not use chemical solvent, can avoid corrosion hole and the wet etching residue in notched gates region.Additionally, the device performance of MIS interface quality and notched gates MISFET can be improved further by the high-quality AlN thin layer that formed in place.
Accompanying drawing explanation
Fig. 1-11 is the device manufacture method process schematic representation of this utility model embodiment 1.
Figure 12 is the device architecture schematic diagram of this utility model embodiment 2.
Figure 13 is the device architecture schematic diagram of this utility model embodiment 3.
Figure 14 is the device architecture schematic diagram of this utility model embodiment 4.
Figure 15 is the device architecture schematic diagram of this utility model embodiment 5.
Detailed description of the invention
Accompanying drawing being merely cited for property explanation, it is impossible to be interpreted as the restriction to this patent；In order to the present embodiment is more preferably described, some parts of accompanying drawing have omission, zoom in or out, and do not represent the size of actual product；To those skilled in the art, in accompanying drawing, some known features and explanation thereof may will be understood by omission.Being merely cited for property of position relationship explanation described in accompanying drawing, it is impossible to be interpreted as the restriction to this patent.
Embodiment 1
It is the device architecture schematic diagram of the present embodiment as shown in figure 11, its structure includes substrate 1 the most successively, stress-buffer layer 2, GaN epitaxial layer 3, AlGaN potential barrier 4, reactive ion etching forms groove, growing AIN thin layer 5 in place, gate insulator dielectric layer 6, two ends form source electrode 7 and drain electrode 8, and the insulating barrier 6 at recess channel deposits grid 9.
The manufacture method of the device field-effect transistor of above-mentioned GaN base notched gates MISFET as Figure 1-Figure 11, comprises the following steps:
S1, utilize mocvd method, Si substrate 1 grows a ply stress cushion 2, as shown in Figure 1；
S2, utilize mocvd method, stress-buffer layer 2 grows GaN epitaxial layer 3, as shown in Figure 2；
S3, utilize mocvd method, GaN epitaxial layer 3 grows AlGaN potential barrier 4, as shown in Figure 3；
S4, by one layer of SiO of plasma enhanced chemical vapor deposition2, as mask layer 10, as shown in Figure 4；
S5, by photoetching method select region etch, remove the mask layer 10 of area of grid, as shown in Figure 5；
S6, utilize mocvd method, form groove grids by the inverse process of GaN material growth response, as shown in Figure 6；
S7, utilize mocvd method, one layer of high-quality AlN thin layer 5 of growth in place, as shown in Figure 7；
S8, removal mask layer 10, utilize Atomic layer deposition method, form AlN/Al2O3Dielectric layer 6 stacked structure, as shown in Figure 8；
S9, utilize ICP to complete device isolation, etch source electrode and drain ohmic contact region, as shown in Figure 9 simultaneously；
S10, on source electrode and drain region are deposited with, Ti/Al/Ni/Au alloy is as source electrode 7 and the metal ohmic contact of drain electrode 8, as shown in Figure 10；
S11, on the insulating barrier in groove grids region be deposited with Ni/Au alloy as grid 9 metal, as shown in figure 11.
So far, the preparation process of whole device is completed.Figure 11 is the device architecture schematic diagram of embodiment 1.
Embodiment 2
Being the device architecture schematic diagram of the present embodiment as shown in figure 12, it differs only in embodiment 1 structure: embodiment 2 further groove grid is to be obtained by epitaxial growth back reaction etching, but the high-quality AlN thin layer of growth not in place.
Embodiment 3
Being the device architecture schematic diagram of the present embodiment as shown in figure 13, it differs only in embodiment 1 structure: in embodiment 1, whole area of grid AlGaN potential barrier is etched and removes and form groove.Conducting channel produces between AlN/ dielectric layer and GaN epitaxial layer.And in this embodiment, certain thickness AlGaN potential barrier can be retained by controlling etch period, owing to raceway groove has higher two-dimensional electron gas at heterojunction boundary, channel mobility and output electric current can be improved.
Embodiment 4
Being the device architecture schematic diagram of the present embodiment as shown in figure 14, it differs only in embodiment 1 and example 3 structure: in this embodiment, whole AlGaN potential barrier can be removed and over etching certain thickness in GaN epitaxial layer by controlling etch period.Conducting channel produces between AlN/ dielectric layer and GaN epitaxial layer.
Embodiment 5
Being the device architecture schematic diagram of the present embodiment as shown in figure 15, it is with embodiment 1 difference: embodiment 1 is horizontal conducting type MISFET, and embodiment 4 is longitudinal conducting type device.Specifically, the GaN epitaxial layer of embodiment 4 is N-shaped doped epitaxial layer, and backing material is low-resistance silicon, GaN heavy doping self-supported substrate etc..
Embodiment 6
The present embodiment differs only in embodiment 1 structure: after the present embodiment obtains groove grids by epitaxial growth back reaction etching, and growth high-quality SiN thin layer in place, thickness is 0-10 nm.
Furthermore, it is necessary to explanation, the accompanying drawing of above example, merely to the purpose of signal, is therefore not necessarily to scale.
Obviously, above-described embodiment of the present utility model is only for clearly demonstrating this utility model example, and is not the restriction to embodiment of the present utility model.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here without also cannot all of embodiment be given exhaustive.All any amendment, equivalent and improvement etc. made within spirit of the present utility model and principle, within should be included in this utility model scope of the claims.
Claims (8)
1. a novel GaN base notched gates MISFET device, it is characterized in that, include substrate (1), stress-buffer layer (2), GaN epitaxial layer (3) the most successively, AlGaN potential barrier (4), reactive ion etching forms groove, growing AIN thin layer (5) in place, gate insulator dielectric layer (6), two ends form source electrode (7) and drain electrode (8), and the insulating barrier (6) at recess channel deposits grid (9).
One the most according to claim 1 novel GaN base notched gates MISFET device, it is characterised in that: described substrate (1) is any one in Si substrate, Sapphire Substrate, silicon carbide substrates, GaN self-supported substrate.
One the most according to claim 1 novel GaN base notched gates MISFET device, it is characterised in that: any one that stress-buffer layer (2) is AlN, AlGaN, GaN described or combination；Stress buffer layer thickness is 10 nm ~ 100 μm.
One the most according to claim 1 novel GaN base notched gates MISFET device, it is characterised in that: the described GaN epitaxial layer that GaN epitaxial layer (3) is involuntary doping or the high resistant GaN epitaxial layer of doping, GaN epitaxial layer thickness is 100 nm ~ 100 μm.
One the most according to claim 1 novel GaN base notched gates MISFET device, it is characterised in that: described epitaxial layer is AlGaN potential barrier (4), and AlGaN layer thickness is 5-50 nm.
One the most according to claim 1 novel GaN base notched gates MISFET device, it is characterised in that: in described AlGaN potential barrier (4), and can also insert AlN thin layer between GaN layer, thickness is 0-10 nm.
One the most according to claim 1 novel GaN base notched gates MISFET device, it is characterised in that: described epitaxial layer (5) is high-quality AlN layer, and thickness is 0-10 nm；Described insulating medium layer (6) is Al2O3、HfO2、SiO2Or SiN etc., thickness is 1-100 nm；Form AlN/ dielectric layer stacked structure.
One the most according to claim 1 novel GaN base notched gates MISFET device, it is characterised in that: described source electrode (7) and drain electrode (8) material are Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy；Grid (9) material is Ni/Au alloy, Pt/Al alloy, Pd/Au alloy or TiN/Ti/Au alloy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620226766.6U CN205621740U (en) | 2016-03-23 | 2016-03-23 | Novel concave groove gate MISFET device of gaN base |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620226766.6U CN205621740U (en) | 2016-03-23 | 2016-03-23 | Novel concave groove gate MISFET device of gaN base |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205621740U true CN205621740U (en) | 2016-10-05 |
Family
ID=57031926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620226766.6U Active CN205621740U (en) | 2016-03-23 | 2016-03-23 | Novel concave groove gate MISFET device of gaN base |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205621740U (en) |
-
2016
- 2016-03-23 CN CN201620226766.6U patent/CN205621740U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110190116B (en) | High-threshold-voltage normally-off high-electron-mobility transistor and preparation method thereof | |
| CN208861993U (en) | Normally-off high electron mobility transistor | |
| JP5923712B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN107742644B (en) | High-performance normally-off GaN field effect transistor and preparation method thereof | |
| KR102080745B1 (en) | Nitride semiconductor and method thereof | |
| CN108604597A (en) | With AL(1-X)SIXThe enhancement mode III- nitride devices of O gate insulators | |
| CN106298887A (en) | A kind of preparation method of high threshold voltage high mobility notched gates MOSFET | |
| CN105932041B (en) | The face N GaN base fin high electron mobility transistor and production method | |
| CN107768252A (en) | A kind of normally-off GaN base MOSFET structure of the high conduction property of high threshold voltage and preparation method thereof | |
| CN104638010B (en) | A kind of GaN normally-off MISFET devices laterally turned on and preparation method thereof | |
| JP5520432B2 (en) | Manufacturing method of semiconductor transistor | |
| CN110648914B (en) | Method for improving breakdown voltage of gallium nitride transistor | |
| CN105789315A (en) | AINGaN base field effect transistor of high quality MIS structure and manufacturing method thereof | |
| CN109860288A (en) | Semiconductor device | |
| CN107785435A (en) | A kind of low on-resistance MIS notched gates GaN base transistors and preparation method | |
| CN110100313A (en) | A kind of enhanced switching device and its manufacturing method | |
| CN105679679B (en) | A kind of preparation method of GaN base notched gates MISFET | |
| CN105428236A (en) | GaN HEMT radio frequency device and gate self-aligning preparation method thereof | |
| CN107706232A (en) | A kind of MIS grid structure normally-off GaN base transistor in situ and preparation method | |
| CN111081772A (en) | Gallium nitride transistor and method for manufacturing the same | |
| CN206441733U (en) | A kind of high threshold voltage high mobility notched gates MOSFET structure | |
| CN207966998U (en) | A kind of normally-off GaN base MOSFET structure of the high conduction property of high threshold voltage | |
| CN219832664U (en) | High-performance p-GaN gate enhanced transistor based on oxygen treatment | |
| CN106449737A (en) | Low-contact resistor type GaN-based device and manufacturing method thereof | |
| CN205621740U (en) | Novel concave groove gate MISFET device of gaN base |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |