CN107154435A - Grading current barrier layer vertical-type power device - Google Patents
Grading current barrier layer vertical-type power device Download PDFInfo
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- 230000004888 barrier function Effects 0.000 title claims abstract description 183
- 238000000034 method Methods 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 9
- 229910052772 Samarium Inorganic materials 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 35
- 230000005684 electric field Effects 0.000 description 17
- 230000005669 field effect Effects 0.000 description 15
- 239000010931 gold Substances 0.000 description 13
- 125000005842 heteroatom Chemical group 0.000 description 13
- 238000001451 molecular beam epitaxy Methods 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 8
- 238000005566 electron beam evaporation Methods 0.000 description 8
- 230000001965 increasing effect Effects 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- 239000000376 reactant Substances 0.000 description 7
- 238000009826 distribution Methods 0.000 description 6
- 230000008020 evaporation Effects 0.000 description 6
- 238000001704 evaporation Methods 0.000 description 6
- 229910002704 AlGaN Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 229910021529 ammonia Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000004907 flux Effects 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000011160 research Methods 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 229910001425 magnesium ion Inorganic materials 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention discloses a kind of grading current barrier layer vertical-type power device, mainly solve existing similar device breakdown potential force down with conducting resistance it is big the problem of, it includes：Substrate (1), drift layer (2), aperture layer (3), the symmetrical multistage hierarchic structure current barrier layer (4) in left and right two, channel layer (6) and barrier layer (7), the both sides of channel layer (6) and barrier layer (7) are etched with source slot (10), two source electrodes (11) are deposited with both sides source slot (10), extension has p-type cap layers (8) on barrier layer between source electrode (11), it is carved with step (9) in p-type cap layers (8) both sides, p-type cap layers (8) are deposited over grid (12), substrate (1) is deposited with drain electrode (13) below, aperture (5) are formed between two symmetrical current barrier layers (4).Breakdown voltage of the present invention is high, technique is simple, conducting resistance is small, high yield rate, available for power electronic system.
Description
Technical field
The invention belongs to microelectronics technology, it is related to semiconductor devices, particularly grading current barrier layer vertical-type work(
Rate device, available for power electronic system.
Technical background
Power semiconductor is the core parts of Power Electronic Technique, with becoming increasingly conspicuous for the energy and environmental problem,
Research and develop novel high-performance, low-loss power device just turn into improve utilization rate of electrical, save the energy, alleviating energy crisis it is effective
One of approach.And serious restricting relation is there is in power device research, between high speed, high pressure and low on-resistance, close
It is the key for improving device overall performance to manage, effectively improve this restricting relation.With the development of microelectric technique, tradition the
The theoretical limit that generation Si semiconductors and second generation GaAs semiconductor power devices performance have been determined in itself close to its material.In order to
Chip area can be further reduced, working frequency is improved, improves operating temperature, reduction conducting resistance, improves breakdown voltage, reduction
Machine volume, overall efficiency is improved, using GaN as the semiconductor material with wide forbidden band of representative, by its bigger energy gap, higher
Critical breakdown electric field and Geng Gao electronics saturation drift velocity, and the protrusion such as stable chemical performance, high temperature resistant, radioresistance is excellent
Point, shows one's talent in terms of high performance power device is prepared, and application potential is huge.Especially with GaN base heterojunction structure
Horizontal HEMT, i.e., horizontal GaN base high electron mobility transistor (HEMT) device, is even more because of its low electric conduction
The characteristics such as resistance, high-breakdown-voltage, senior engineer's working frequency, become the focus studied and applied both at home and abroad, focus.
However, in horizontal GaN base HEMT device, in order to obtain higher breakdown voltage, it is necessary to increase grid leak spacing, this
Device size and conducting resistance can be increased, reduce effective current density and chip performance on unit chip area, so as to cause
The increase of chip area and development cost.In addition, in horizontal GaN base HEMT device, as caused by high electric field and surface state
Current collapse problem is more serious, although currently existing numerous braking measures, current collapse problem is not obtained still thoroughly
Solve.In order to solve the above problems, researchers propose vertical-type GaN base current apertures hetero junction field effect device, are also
A kind of current barrier layer vertical-type power device, referring to AlGaN/GaN current aperture vertical electron
transistors,IEEE Device Research Conference,pp.31-32,2002.GaN base current apertures hetero-junctions
Fieldtron can improve breakdown voltage by increasing drift layer thickness, it is to avoid sacrifice asking for device size and conducting resistance
Topic, therefore high power density chip can be realized.And in GaN base current apertures hetero junction field effect device, high electric field area
Domain is located in semi-conducting material body, and this can thoroughly eliminate current collapse problem., Ilan Ben-Yaacov et al. in 2004
AlGaN/GaN current apertures hetero junction field effect devices are developed using MOCVD regrowths trench technology after etching, the device is not
Using passivation layer, maximum output current is 750mA/mm, and mutual conductance is 120mS/mm, and two ends grid breakdown voltage is 65V, and electric current collapses
Effect of collapsing is significantly inhibited, referring to AlGaN/GaN current aperture vertical electron
transistors with regrown channels,Journal of Applied Physics,Vol.95,No.4,
pp.2073-2078,2004.2012, Srabanti Chowdhury et al. utilized Mg ion implantings current barrier layer combination etc.
The technology of ion auxiliary MBE regrowth AlGaN/GaN hetero-junctions, develops the current apertures heterojunction field effect based on GaN substrate
Device is answered, the device is using 3 μm of drift regions, and maximum output current is 4kAcm-2, conducting resistance is 2.2m Ω cm2, puncture
Voltage is 250V, and suppression current collapse effect is good, referring to CAVET on Bulk GaN Substrates Achieved
With MBE-Regrown AlGaN/GaN Layers to Suppress Dispersion,IEEE Electron Device
Letters,Vol.33,No.1,pp.41-43,2012.The same year, a kind of enhancing proposed by Masahiro Sugimoto et al.
Type GaN base current apertures hetero junction field effect device is authorized, referring to Transistor, US8188514B2,2012.In addition,
2014, Hui Nie et al. developed a kind of enhanced GaN base current apertures hetero junction field effect device based on GaN substrate, should
Device threshold voltage is 0.5V, and saturation current is more than 2.3A, and breakdown voltage is 1.5kV, and conducting resistance is 2.2m Ω cm2, ginseng
See 1.5-kV and 2.2-m Ω-cm2Vertical GaN Transistors on Bulk-GaN Substrates,IEEE
Electron Device Letters,Vol.35,No.9,pp.939-941,2014。
Traditional GaN base current apertures hetero junction field effect device is to be based on GaN base wide bandgap semiconductor heterojunction structure, its
Including：Substrate 1, drift layer 2, aperture layer 3, left and right two symmetrical current barrier layers 4, aperture 5, channel layer 6 and barrier layer 7；
The both sides of channel layer 6 and barrier layer 7, which are etched with source slot 10, both sides source slot 10, is deposited with two source electrodes 11, between source electrode 11
Extension has p-type cap layers 8 on barrier layer, and two steps 9 are carved with the both sides of p-type cap layers 8, and p-type cap layers 8 are deposited over grid 12, lining
Bottom 1 is deposited with drain electrode 13 below, as shown in Figure 1.
By the theory and experimental study of more than ten years, researchers have found, above-mentioned traditional GaN base current apertures heterojunction field
There is inherent shortcoming in effect device structure, electric-field intensity distribution in device can be caused extremely uneven, especially in current blocking
With there is high peak electric field in layer, in the semi-conducting material of aperture area interface close beneath so as to cause device to hit too early
Wear.This to be difficult to realize by increasing the thickness of n-type GaN drift layer come the breakdown potential of constantly improve device in actual process
Pressure.Therefore, the breakdown voltage of traditional structure GaN base current apertures hetero junction field effect device is not universal high.It is higher in order to obtain
Device electric breakdown strength, it is possible to by increasing the thickness of n-type GaN drift layer come the breakdown voltage of constantly improve device, 2013
Year, it is heterogeneous that Zhongda Li et al. have studied a kind of enhanced GaN base current apertures based on superjunction using technology of numerical simulation
Junction field effect device, result of study shows the Electric Field Distribution that super-junction structure can be effectively inside modulation device, when making to be in OFF state
Electric-field intensity tends to be uniformly distributed device inside everywhere, therefore device electric breakdown strength is up to 5~20kV, and wide using 3 μm of attached columns
When breakdown voltage be 12.4kV, and conducting resistance be 4.2m Ω cm2, referring to Design and Simulation of 5-20-
kV GaN Enhancement-Mode Vertical Superjunction HEMT,IEEE Transactions on
Electron Decices,Vol.60,No.10,pp.3230-3237,2013.Using the GaN base current apertures hetero-junctions of superjunction
Fieldtron can theoretically obtain high-breakdown-voltage, and can realize increase of the breakdown voltage with n-type GaN drift layer thickness
And it is constantly improve, it is to have reported a kind of very effective high power device knot of breakdown voltage highest in document both at home and abroad at present
Structure.However, in the GaN base current apertures hetero junction field effect device using super-junction structure, when break-over of device near superjunction
Extra conducting resistance can be produced, and the conducting resistance can be continuously increased with the increase of drift layer thickness, thus while device
The breakdown voltage of part is improved with the increase of drift layer thickness, but the conducting resistance of device can also be accordingly increased, device
Contradiction between middle breakdown voltage and conducting resistance does not have thorough solution.Therefore, explore and research and develop breakdown voltage height, electric conduction
The small new GaN base current apertures hetero junction field effect device of resistance, it is very necessary, urgent, have important practical significance.
The content of the invention
It is an object of the invention to the deficiency for above-mentioned prior art, there is provided a kind of grading current barrier layer vertical-type work(
Rate device, to reduce the conducting resistance of device, improves the breakdown voltage of device, and realizes the sustainable increase of breakdown voltage, shows
The contradiction between alleviation device electric breakdown strength and conducting resistance is write, improves the breakdown characteristics of device.
To achieve these goals, the technical proposal of the invention is realized in this way：
First, device architecture
A kind of grading current barrier layer vertical-type power device, including:Substrate 1, drift layer 2, aperture layer 3, two it is symmetrical
Current barrier layer 4, channel layer 6 and barrier layer 7, the both sides of channel layer 6 and barrier layer 7 are etched with source slot 10, both sides source slot 10
In be deposited with extension on the barrier layer between two source electrodes 11, source electrode 11 and have p-type cap layers 8, two platforms are carved with the both sides of p-type cap layers 8
Rank 9, p-type cap layers 8 are deposited over grid 12, and substrate 1 is deposited between drain electrode 13, two symmetrical current barrier layers 4 below
Form aperture 5, it is characterised in that：
Described two current barrier layers 4, be by from the first inside barrier layer 41 of the both sides of aperture layer 3, the second barrier layer 42,
Two symmetrical m grades of hierarchic structures that 3rd barrier layer 43 to m barrier layers 4m is collectively formed, wherein the first barrier layer 41 is located at
Outermost both sides in aperture layer 3.
2nd, preparation method
The method that the present invention makes grading current barrier layer vertical-type power device, including following process：
A. n is being used+On section bar material GaN substrate 1 epitaxial thickness be 3~10 μm, doping concentration be 1 × 1015~1 ×
1018cm-3N-Type GaN semi-conducting materials, form drift layer 2；
B. extension n-type GaN semi-conducting materials on drift layer 2, formed thickness be 1~10 μm, doping concentration be 1 × 1015
~1 × 1018cm-3Aperture layer 3；
C. mask is made for the first time on aperture layer 3, be 1 using two side position implantation dosages of the mask in aperture layer
×1015~1 × 1016cm-2N-type impurity, make thickness T1For 1~10 μm, width S1For 0.5~1 μm of two first stops
Layer 41；
D. carry out m-1 mask successively on aperture layer 3, and utilize mask successively, in preceding two stops once formed
Both sides implantation dosage is 1 × 10 in aperture layer 3 between layer15~1 × 1016cm-2N-type impurity, sequentially form the second barrier layer
The m level hierarchic structures current barrier layer 4 that 42 to m barrier layers 4m, the first barrier layer 41 to m barrier layers 4m are constituted, two right
Aperture 5 is formed between the current barrier layer 4 of title, m is determined according to device actual operation requirements, its value is the integer more than or equal to 2；
E. in two current barrier layers 4 and the upper epitaxial GaN semi-conducting materials of aperture 5, thickness is formed for 0.04~0.2 μm
Channel layer 6；
F. in the upper epitaxial GaN base semiconductor material with wide forbidden band of channel layer 6, the barrier layer 7 that thickness is 5~50nm is formed；
G. in the upper epitaxial p-type GaN semi-conducting materials of barrier layer 7, the p-type cap layers that thickness is 0.02~0.25 μm are formed
8；
H. mask is made in p-type cap layers 8, is performed etching using the mask in the p-type cap layers left and right sides, and etched area is deep
Degree is equal to the thickness of p-type cap layers, and the p-type cap layers 8 formed between step 9, two steps 9 and two current barrier layers 4 are in level
Overlapping length on direction is all higher than 0 μm；
I. mask is made on the top of potential barrier 7 not covered by p-type cap layers 8 and p-type cap layers top, using the mask in gesture
The arranged on left and right sides of barrier layer 7 is performed etching, and untill being etched to the upper surface of two current barrier layers 4, forms left and right two source slots
10；
J. made on two tops of source slot 10, the top of barrier layer 7 not covered by p-type cap layers 8 and the top of p-type cap layers 8
Mask, deposits metal, and depth of the thickness more than source slot 10 of deposited metal, to make using the mask in two source slots 10
Make source electrode 11；
K. the top of barrier layer 7 not covered on the top of source electrode 11, by p-type cap layers 8 and the top of p-type cap layers 8 make mask,
Metal is deposited on the top of p-type cap layers 8 using the mask, to make grid 12；
L. metal is deposited on the back side of substrate 1, to make drain electrode 13.
Device of the present invention is compared with traditional GaN base current apertures hetero junction field effect device, with advantages below：
1. breakdown voltage is realized to continue to increase.
The present invention is using the current barrier layer of multistage stepped-style, and the barrier layers at different levels and aperture layer for making device inside have a common boundary
Face close beneath can produce a peak electric field, and by adjusting the thickness, width and doping concentration on barrier layers at different levels, can be with
So that barrier layers at different levels and the peak electric field approximately equal of aperture layer interface close beneath, and partly led less than GaN base broad stopband
The breakdown electric field of body material, so as to improve the breakdown voltage of device；In addition, can by the ladder number for increasing current barrier layer
Realize continuing to increase for breakdown voltage.
2. while device electric breakdown strength is improved, device on-resistance can be slightly reduced.
The present invention improves device electric breakdown strength by using the current blocking Rotating fields of multistage stepped-style, due to first
Horizontal range of barrier layer to the m barrier layers away from drift layer center is sequentially reduced, when break-over of device, is removed in device drift layer
Depletion region produced by m barrier layers can have an impact to transporting for electric current, produce outside conducting resistance, remaining barrier layer institute at different levels
The depletion region of generation is due to away from aperture center, i.e. current path, so hardly influenceing the conducting resistance of device.By adjusting
Thickness, width and the doping concentration on barrier layers at different levels in whole device of the present invention, can also further reduce the conducting resistance of device.
Therefore, with the increase of current barrier layer step number purpose, the breakdown voltage of device continues to increase, and conducting resistance can slightly subtract
It is small.
The technology contents and effect of the present invention are further illustrated below in conjunction with drawings and examples.
Brief description of the drawings
Fig. 1 is the structure chart of traditional GaN base current apertures hetero junction field effect device；
Fig. 2 is the structure chart of grading current barrier layer vertical-type power device of the present invention；
Fig. 3 is the flow chart that the present invention makes grading current barrier layer vertical-type power device；
Fig. 4 is the two dimensional electric field distribution map in the case of puncturing to traditional devices and device simulation of the present invention gained；
Fig. 5 is to the output current figure in the case of forward conduction obtained by traditional devices and device simulation of the present invention.
Embodiment
Reference picture 2, grading current barrier layer vertical-type power device of the present invention is heterogeneous based on GaN base wide bandgap semiconductor
Junction structure, it includes：Substrate 1, drift layer 2, aperture layer 3, there are left and right two symmetrical current barrier layer 4, apertures in aperture layer 3
5th, the both sides of channel layer 6 and barrier layer 7, channel layer 6 and barrier layer 7, which are etched with source slot 10, both sides source slot 10, is deposited with two
Extension has p-type cap layers 8 on barrier layer between source electrode 11, source electrode 11, and two steps 9, p-type cap layers 8 are carved with the both sides of p-type cap layers 8
Deposited over to have grid 12, substrate 1 is deposited with drain electrode 13 below.Wherein：
The drift layer 2, positioned at the top of substrate 1, its thickness is 3~10 μm, doping concentration is 1 × 1015~1 × 1018cm-3；
The aperture layer 3, positioned at the top of drift layer 2, its thickness is 1~10 μm, doping concentration is 1 × 1015~1 ×
1018cm-3；
Described two current barrier layers 4, be by from the first inside barrier layer 41 of the both sides of aperture layer 3, the second barrier layer 42,
Two symmetrical m grades of hierarchic structures that 3rd barrier layer 43 to m barrier layers 4m is collectively formed, series m is actual according to device
Use requirement determines that its value is the integer more than or equal to 2；First barrier layer 41 is located at the outermost both sides in aperture layer 3, each to stop
Layer is adulterated using p-type；First thickness to m barrier layers is Ti, width is Si, and from the both sides of aperture layer 3 inwardly, TiSuccessively
Reduce, S1≤S2≤...≤Si≤…≤Sm, i is integer and m >=i >=1, T1For 1~10 μm, width S1For 0.5~1 μm, T1For
The thickness on the first barrier layer 41, S1For the width on the first barrier layer 41；
The aperture 5, between two current barrier layers 4；
The channel layer 6, positioned at two current barrier layers 4 and the top of aperture 5, its thickness is 0.04~0.2 μm；
The barrier layer 7, positioned at the top of channel layer 6, if it is by the identical or different GaN base wide bandgap semiconductor material of dried layer
Material composition, thickness is 5~50nm；
The p-type cap layers 8, its overlapping length with two current barrier layers 4 in the horizontal direction is all higher than 0 μm；
The source slot 10, its depth is equal to the gross thickness of channel layer 6 and barrier layer 7；
The source electrode 11, its thickness is more than the depth of source slot 10.
Reference picture 3, the present invention makes the process of grading current barrier layer vertical-type power device, provides following three kinds of implementation
Example：
Embodiment one：Make the grading current barrier layer vertical-type power device that current barrier layer ladder series m is 2.
Step 1. extension n on substrate 1-Type GaN, forms drift layer 2, such as Fig. 3 a.
Using n+Type GaN does substrate 1, using metal organic chemical vapor deposition technology, and epitaxial thickness is on substrate 1
3 μm, doping concentration be 1 × 1015cm-3N-Type GaN material, forms drift layer 2, wherein：
The process conditions that extension is used for：Temperature is 950 DEG C, and pressure is 40Torr, with SiH4For doped source, hydrogen flowing quantity
For 4000sccm, ammonia flow is 4000sccm, and gallium source flux is 100 μm of ol/min.
Step 2. extension n-type GaN on drift layer, forms aperture layer 3, such as Fig. 3 b.
Using metal organic chemical vapor deposition technology, on drift layer 2 epitaxial thickness be 1 μm, doping concentration be 1 ×
1015cm-3N-type GaN material, formed aperture layer 3, wherein：
The process conditions that extension is used for：Temperature is 950 DEG C, and pressure is 40Torr, with SiH4For doped source, hydrogen flowing quantity
For 4000sccm, ammonia flow is 4000sccm, and gallium source flux is 100 μm of ol/min.
Step 3. makes the first barrier layer 41, such as Fig. 3 c.
First mask is made for the first time on aperture layer 3；
Ion implantation technique is reused, the two side position implantation dosages in aperture layer are 1 × 1015cm-2N-type impurity
Mg, makes thickness T1For 1 μm, width S1For 0.5 μm of two the first barrier layers 41.
Step 4. makes the second barrier layer 42, such as Fig. 3 d.
First make mask for the second time on aperture layer 3 and two the first barrier layers 41；
Ion implantation technique is reused, two side positions inject in the aperture layer between left and right two the first barrier layers 41
Dosage is 4.5 × 1015cm-2N-type impurity Mg, form thickness T2For 0.5 μm, width S2For 1 μm of two the second barrier layers 42,
First barrier layer 41 and the second barrier layer 42 constitute current barrier layer 4, the current barrier layer 4 of two symmetrical two grades of hierarchic structure
Between formed aperture 5.
Step 5. extension GaN material makes channel layer 6, such as Fig. 3 e.
Using molecular beam epitaxy technique, outside the top on two the first barrier layers 41, two the second barrier layers 42 and aperture 5
Prolong the GaN material that thickness is 0.04 μm, form channel layer 6；
The molecular beam epitaxy technique, its process conditions is：Vacuum is less than or equal to 1.0 × 10-10Mbar, radio-frequency power
For 400W, reactant uses N2, high-purity Ga sources.
Step 6. extension Al0.5Ga0.5N, makes barrier layer 7, such as Fig. 3 f.
The Al that epitaxial thickness is 5nm on channel layer 6 using molecular beam epitaxy technique0.5Ga0.5N materials, form barrier layer
7, wherein：
The process conditions of molecular beam epitaxy are：Vacuum is less than or equal to 1.0 × 10-10Mbar, radio-frequency power is 400W, instead
Agent is answered to use N2, high-purity Ga sources, high-purity Al sources.
Step 7. is in the upper epitaxial p-type cap layers 8 of barrier layer 7, such as Fig. 3 g.
Using molecular beam epitaxy technique, in the p-type GaN material that the upper epitaxial thickness of barrier layer 7 is 0.02 μm, to make p
Type cap layers 8；
The molecular beam epitaxy technique, its process conditions is：Vacuum is less than or equal to 1.0 × 10-10Mbar, radio-frequency power
For 400W, reactant uses N2, high-purity Ga sources, high-purity Mg sources.
Step 8. makes step 9, such as Fig. 3 h in the arranged on left and right sides of p-type cap layers 8 etching.
Mask is made in p-type cap layers 8, is cap in cap layers arranged on left and right sides etching depth using reactive ion etching technology
The etched area of thickness degree, the p-type cap layers 8 formed between step 9, two steps and two current barrier layers 4 are in the horizontal direction
Overlapping length be 0.5 μm；
The process conditions of reactive ion etching are：Cl2Flow is 15sccm, and pressure is 10mTorr, and power is 100W.
Step 9. makes source slot 10, such as Fig. 3 i in barrier layer 7 and the left and right sides of channel layer 6 etching.
First mask is made on the top of barrier layer 7 not covered by p-type cap layers 8 and the top of p-type cap layers 8；
Reactive ion etching technology is reused, is performed etching in the arranged on left and right sides of barrier layer 7, and is etched to two electric currents
Untill the upper surface on barrier layer 4, left and right two source slots 10 are formed；
The process conditions of reactive ion etching are：Cl2Flow is 15sccm, and pressure is 10mTorr, and power is 100W.
Step 10. makes source electrode 11, such as Fig. 3 j.
First two tops of source slot 10, the top of barrier layer 7 not covered by p-type cap layers 8 and the top of p-type cap layers 8 make and covered
Mould；
Electron beam evaporation technique is reused, in two top of source slot 10 deposit Ti/Au/Ni combination metals, source electrode 11 is formed,
Wherein：The metal deposited, from bottom to top, Ti thickness is 0.02 μm, Au thickness is 0.3 μm, Ni thickness is 0.05 μm；
The process conditions of electron beam evaporation are：Vacuum is less than 1.8 × 10-3Pa, power bracket is 200~1000W, evaporation
Speed is less than
Step 11. makes grid 12, such as Fig. 3 k.
The top of barrier layer 7 not covered on the top of source electrode 11, by p-type cap layers 8 11a) and the top of p-type cap layers 8, which make, to be covered
Mould；
Electron beam evaporation technique 11b) is used, Ni/Au/Ni combination metals are deposited in p-type cap layers 8, grid 12 is formed, its
In：From bottom to top, Ni thickness is 0.02 μm to the metal deposited, Au thickness is 0.2 μm, Ni thickness is 0.04 μm；
The process conditions of electron beam evaporation are：Vacuum is less than 1.8 × 10-3Pa, power bracket is 200~1000W, evaporation
Speed is less than
Step 12. makes drain electrode 13, such as Fig. 3 l.
Using electron beam evaporation technique, metal Ti, Au, Ni are deposited successively on the back side of whole substrate 1, form drain electrode
13, wherein：The metal deposited, Ti thickness is 0.02 μm, and Au thickness is 0.7 μm, and Ni thickness is 0.05 μm, is completed whole
The making of individual device；
The process conditions that are used of deposit metal for：Vacuum is less than 1.8 × 10-3Pa, power bracket is 200~1000W,
Evaporation rate is less than
Embodiment two：Make the grading current barrier layer vertical-type power device that current barrier layer ladder series m is 2.
First step extension n on substrate-Type GaN, forms drift layer 2, such as Fig. 3 a.
It it is 1000 DEG C in temperature, pressure is 45Torr, with SiH4For doped source, hydrogen flowing quantity is 4400sccm, ammonia flow
Measure as 4400sccm, under gallium source flux is 110 μm of ol/min process conditions, using n+Type GaN does substrate 1, is had using metal
Machine thing chemical vapor deposition techniques, on substrate 1 epitaxial thickness be 5 μm, doping concentration be 1 × 1016cm-3N-Type GaN material,
Complete the making of drift layer 2.
Second step extension n-type GaN on drift layer, form aperture layer 3, such as Fig. 3 b.
It it is 1000 DEG C in temperature, pressure is 45Torr, with SiH4For doped source, hydrogen flowing quantity is 4400sccm, ammonia flow
Measure as 4400sccm, under gallium source flux is 110 μm of ol/min process conditions, use metal organic chemical vapor deposition skill
Art, on drift layer 2 epitaxial thickness be 3 μm, doping concentration be 1 × 1016cm-3N-type GaN material, complete aperture layer 3 system
Make.
3rd step makes the first barrier layer 41, such as Fig. 3 c.
3.1) mask is made for the first time on aperture layer 3；
3.2) ion implantation technique is used, the two side position implantation dosages in aperture layer are 4 × 1015cm-2P-type it is miscellaneous
Matter Mg, forms thickness T1For 3 μm, width S1For 0.6 μm of two the first barrier layers 41.
4th step makes the second barrier layer 42, such as Fig. 3 d.
4.1) second of making mask on aperture layer 3 and two the first barrier layers 41；
4.2) ion implantation technique is used, both sides implantation dosage is 5 in the aperture layer between left and right first barrier layer 41
×1015cm-2N-type impurity Mg, form thickness T2For 1 μm, width S2Stop for 1.5 μm of two the second barrier layers 42, first
The barrier layer 42 of layer 41 and second is constituted to be formed between current barrier layer 4, the current barrier layer 4 of two symmetrical two grades of hierarchic structure
Aperture 5.
5th step extension GaN materials, make channel layer 6, such as Fig. 3 e.
It is less than or equal to 1.0 × 10 in vacuum-10Mbar, radio-frequency power is 400W, and reactant uses N2, high-purity Ga sources
Under process conditions, using molecular beam epitaxy technique, on two the first barrier layers 41, two the second barrier layers 42 and the tops of aperture 5,
Epitaxial thickness is 0.1 μm of GaN material, completes the making of channel layer 6.
6th step extensions Al0.3Ga0.7N, makes barrier layer 7, such as Fig. 3 f.
It is less than or equal to 1.0 × 10 in vacuum-10Mbar, radio-frequency power is 400W, and reactant uses N2, high-purity Ga sources, height
Under the process conditions in pure Al sources, using molecular beam epitaxy technique, epitaxial thickness is 30nm Al on channel layer 60.3Ga0.7N materials
Material, completes the making of barrier layer 7.
7th step is in the upper epitaxial p-type cap layers 8 of barrier layer 7, such as Fig. 3 g.
It is less than or equal to 1.0 × 10 in vacuum-10Mbar, radio-frequency power is 400W, and reactant uses N2, high-purity Ga sources, height
Under the process conditions in pure Mg sources, using molecular beam epitaxy technique, in the p-type GaN materials that the upper epitaxial thickness of barrier layer 7 is 0.15 μm
Material, completes the making of p-type cap layers 8.
8th step makes step 9, such as Fig. 3 h in the arranged on left and right sides of p-type cap layers 8 etching.
8.1) mask is made in p-type cap layers 8；
8.2) in Cl2Flow is 15sccm, and pressure is 10mTorr, power under 100W process conditions, using reaction from
Sub- lithographic technique, is 0.15 μm of etched area in cap layers arranged on left and right sides etching depth, completes the making of step 9, two steps it
Between p-type cap layers 8 and two current barrier layers 4 overlapping length in the horizontal direction be 0.5 μm.
9th step makes source slot 10, such as Fig. 3 i in barrier layer 7 and the left and right sides of channel layer 6 etching.
9.1) mask is made on the top of barrier layer 7 not covered by p-type cap layers 8 and the top of p-type cap layers 8；
9.2) in Cl2Flow is 15sccm, and pressure is 10mTorr, power under 100W process conditions, using reaction from
Sub- lithographic technique, is performed etching in the arranged on left and right sides of barrier layer 7, and untill being etched to the upper surface of two current barrier layers 4,
Form left and right two source slots 10.
Tenth step makes source electrode 11, such as Fig. 3 j.
10.1) in two tops of source slot 10, the top of barrier layer 7 not covered by p-type cap layers 8 and the top system of p-type cap layers 8
Make mask；
10.2) it is less than 1.8 × 10 in vacuum-3Pa, power bracket is 200~1000W, and evaporation rate is less thanWork
Under the conditions of skill, using electron beam evaporation technique, in two top of source slot 10 deposit Ti/Au/Ni combination metals, source electrode 11 is formed,
Wherein：The metal deposited, from bottom to top, Ti thickness is 0.02 μm, Au thickness is 0.3 μm, Ni thickness is 0.05 μm.
11st step makes grid 12, such as Fig. 3 k.
11.1) top of barrier layer 7 not covered on the top of source electrode 11, by p-type cap layers 8 and the top of p-type cap layers 8, which make, to be covered
Mould；
11.2) it is less than 1.8 × 10 in vacuum-3Pa, power bracket is 200~1000W, and evaporation rate is less thanWork
Under the conditions of skill, using electron beam evaporation technique, Ni/Au/Ni combination metals are deposited in p-type cap layers 8, the system of grid 12 is completed
Make, and from bottom to top, Ni thickness is 0.02 μm, Au thickness is 0.2 μm, Ni thickness is 0.04 μm.
12nd step makes drain electrode 13, such as Fig. 3 l.
It is less than 1.8 × 10 in vacuum-3Pa, power bracket is 200~1000W, and evaporation rate is less thanTechnique bar
Under part, using electron beam evaporation technique, metal Ti, Au, Ni are deposited successively at the whole back side of substrate 1, form Ti/Au/Ni combinations
Metal, to make drain electrode 13, and Ti thickness is 0.02 μm, Au thickness is 0.7 μm, Ni thickness is 0.05 μm, and completed
The making of whole device.
Embodiment three：Make the grading current barrier layer vertical-type power device that current barrier layer ladder series m is 4
Step A. uses temperature for 950 DEG C, and pressure is 40Torr, with SiH4For doped source, hydrogen flowing quantity is 4000sccm,
Ammonia flow is 4000sccm, and gallium source flux is 100 μm of ol/min process conditions, using n+Type GaN does substrate 1, uses gold
Belong to organic chemical vapor deposition technology, on substrate epitaxial thickness be 10 μm, doping concentration be 1 × 1018cm-3N-Type GaN
Material, makes drift layer 2, such as Fig. 3 a.
Step B. uses temperature for 950 DEG C, and pressure is 40Torr, with SiH4For doped source, hydrogen flowing quantity is 4000sccm,
Ammonia flow is 4000sccm, and gallium source flux is 100 μm of ol/min process conditions, uses metal organic chemical vapor deposition
Technology, on drift layer 2 epitaxial thickness be 10 μm, doping concentration be 1 × 1018cm-3N-type GaN material, make aperture layer 3,
Such as Fig. 3 b.
Step C. makes mask for the first time on aperture layer 3, reuses ion implantation technique, the both sides position in aperture layer
It is 1 × 10 to put implantation dosage16cm-2N-type impurity Mg, form thickness T1It is equal with aperture layer thickness, width S1For two of 1 μm
First barrier layer 41, such as Fig. 3 c.
Step D. makes two the second barrier layers 42, such as two the 3rd barrier layers 43 and two the 4th barrier layers 44, Fig. 3 d.
D1) first make mask for the second time on aperture layer 3 and two the first barrier layers 41, reuse ion implantation technique,
Inner side implantation dosage on left and right first barrier layer 41 is 1 × 1016cm-2N-type impurity Mg, form thickness T2For 0.8 μ
M, width S2For 1.1 μm of two the second barrier layers 42；
D2 mask) is made for the third time on aperture layer 3, two the first barrier layers 41 and two the second barrier layers 42, then is made
With ion implantation technique, two side position implantation dosages are 1 × 10 in the aperture layer between left and right second barrier layer 4216cm-2
N-type impurity Mg, form thickness T3For 0.5 μm, width S3For 1.5 μm of two the 3rd barrier layers 43；
D3) on aperture layer 3, two the first barrier layer 41, two the second barrier layers 42 and two the 3rd barrier layers 43
Four making masks, reuse ion implantation technique, two side positions inject in the aperture layer between left and right 3rd barrier layer 43
Dosage is 1 × 1016cm-2N-type impurity Mg, form thickness T4For 0.15 μm, width S4For 2 μm of two the 4th barrier layers 44,
First barrier layer 41, the second barrier layer 42, the 3rd barrier layer 43 and the 4th barrier layer 44 constitute current barrier layer 4, and two symmetrical
Level Four stairstepping current barrier layer 4 between formed aperture 5.
Step E. is less than or equal to 1.0 × 10 using vacuum-10Mbar, radio-frequency power is 400W, and reactant uses N2, it is high
The process conditions in pure Ga sources, using molecular beam epitaxy technique, two the first barrier layers 41, two the second barrier layers 42, two
3rd barrier layer 43, two the 4th barrier layers 44 and the upper epitaxial thickness of aperture 5 for 0.2 μm of GaN materials channel layer 6, such as
Fig. 3 e.
Step F. is less than or equal to 1.0 × 10 using vacuum-10Mbar, radio-frequency power is 400W, and reactant uses N2, it is high
Pure Ga sources, the process conditions in high-purity Al sources, using molecular beam epitaxy technique, epitaxial thickness is 50nm's on channel layer 6
Al0.1Ga0.9The barrier layer 7 of N materials, such as Fig. 3 f.
Step G. is less than or equal to 1.0 × 10 using vacuum-10Mbar, radio-frequency power is 400W, and reactant uses N2, it is high
Pure Ga sources, the process conditions in high-purity Mg sources, using molecular beam epitaxy technique, in the p that the upper epitaxial thickness of barrier layer 7 is 0.25 μm
Type GaN material, completes the making of p-type cap layers 8, such as Fig. 3 g.
Step H. makes mask in p-type cap layers 8, then using Cl2Flow is 15sccm, and pressure is 10mTorr, and power is
100W process conditions, using reactive ion etching technology, in the etched area that cap layers arranged on left and right sides etching depth is 0.25 μm,
Complete the overlapping length of p-type cap layers 8 and two current barrier layers 4 in the horizontal direction between the making of step 9, two steps
For 0.6 μm, such as Fig. 3 h.
Step I. makes mask on the top of barrier layer 7 not covered by p-type cap layers 8 and the top of p-type cap layers 8, then uses
Cl2Flow is 15sccm, and pressure is 10mTorr, and power is 100W process conditions, using reactive ion etching technology, in gesture
The arranged on left and right sides of barrier layer 7 is performed etching, and untill being etched to the upper surface of two current barrier layers 4, forms left and right two sources
Groove 10, such as Fig. 3 i.
Step J. is on two tops of source slot 10, the top of barrier layer 7 and the top of p-type cap layers 8 that are not covered by p-type cap layers 8
Make mask；It is less than 1.8 × 10 using vacuum again-3Pa, power bracket is 200~1000W, and evaporation rate is less thanWork
Skill condition, using electron beam evaporation technique, in two top of source slot 10 deposit metals, makes source electrode 11, wherein the gold deposited
Belong to for Ti/Au/Ni metallic combinations, i.e., be respectively Ti, Au and Ni from bottom to top, its thickness is followed successively by 0.02 μm, 0.3 μm, 0.05 μ
M, such as Fig. 3 j.
The top of barrier layer 7 and the top of p-type cap layers 8 that step K. is not covered on the top of source electrode 11, by p-type cap layers 8 make
Mask；It is less than 1.8 × 10 using vacuum again-3Pa, power bracket is 200~1000W, and evaporation rate is less thanTechnique bar
Part, using electron beam evaporation technique, deposits metal in p-type cap layers 8, makes grid 12, wherein the metal deposited is Ni/
Au/Ni metallic combinations, i.e., be respectively Ni, Au and Ni from bottom to top, and its thickness is followed successively by 0.02 μm, 0.2 μm, 0.04 μm, such as schemed
3k。
Step L. is less than 1.8 × 10 using vacuum-3Pa, power bracket is 200~1000W, and evaporation rate is less than
Process conditions, using electron beam evaporation technique, deposit metal Ti, Au, Ni successively on the back side of whole substrate 1, form leakage
Pole 13, wherein：The metal deposited, Ti thickness is 0.02 μm, and Au thickness is 0.7 μm, and Ni thickness is 0.05 μm, and complete
Into the making of whole device.Such as Fig. 3 l.
The effect of the present invention can be further illustrated by following emulation：
Emulation 1：To traditional GaN base current apertures hetero junction field effect device and device of the present invention in the case of a breakdown two
Dimension Electric Field Distribution is emulated, as a result such as Fig. 4, and wherein Fig. 4 (a) is traditional devices, and its breakdown voltage is 890V, and Fig. 4 (b) is this
Invention device, employs 3 grades of hierarchic structure current barrier layers, and its breakdown voltage is 1830V.
In the case of puncturing it can be seen from Fig. 4 (a), electric-field intensity distribution is extremely uneven in traditional devices, in current blocking
Layer in the semi-conducting material of aperture area interface close beneath with occurring in that high peak electric field, so as to cause device too early
Puncture.In the case of puncturing it can be seen from Fig. 4 (b), barrier layers at different levels and the aperture layer interface lower section of device inside of the present invention
Nearby generate in an approximately equalised peak electric field, device that Electric Field Distribution is more uniform, illustrate device architecture of the present invention
More efficiently modulation device internal electric field it can be distributed.Therefore the breakdown voltage of device of the present invention is apparently higher than traditional devices
Breakdown voltage.
Emulation 2：To traditional GaN base current apertures hetero junction field effect device and device of the present invention in the case of forward conduction
Output current emulated, as a result such as Fig. 5, wherein device of the present invention employs 3 grades of hierarchic structure current barrier layers.
As seen from Figure 5, in the case of forward conduction, device output current curve of the present invention is bigger in the slope of linear zone
In traditional devices output current curve in the slope of linear zone, illustrate that the conducting resistance of device of the present invention is less than leading for traditional devices
Be powered resistance.
Above description is only several specific embodiments of the present invention, is not construed as limiting the invention, it is clear that for this
, can be without departing substantially from the principle and scope of the present invention after present invention and principle has been understood for the professional in field
In the case of, the method according to the invention carries out the various modifications and variations in form and details, but these are based on the present invention
Modifications and variations still the present invention claims within.
Claims (7)
1. a kind of grading current barrier layer vertical-type power device, including:Substrate (1), drift layer (2), aperture layer (3), two
The both sides of symmetrical current barrier layer (4), channel layer (6) and barrier layer (7), channel layer (6) and barrier layer (7) are etched with source slot
(10) extension on the barrier layer between two source electrodes (11), source electrode (11), is deposited with both sides source slot (10) p-type cap layers (8),
Two steps (9) are carved with p-type cap layers (8) both sides, and p-type cap layers (8) are deposited over grid (12), and substrate (1) is deposited with below
Drain (13), aperture (5) formed between two symmetrical current barrier layers (4), it is characterised in that：
Described two current barrier layers (4), are by the first barrier layer (41), the second barrier layer from aperture layer (3) both sides inwardly
(42), two symmetrical m grades of hierarchic structures that the 3rd barrier layer (43) to m barrier layers (4m) is collectively formed, wherein the first resistance
Barrier (41) is located at the outermost both sides in aperture layer (3).
2. device according to claim 1, it is characterised in that the hierarchic structure series m of current barrier layer (4) is according to device
Part actual operation requirements determine that its value is the integer more than or equal to 2.
3. device according to claim 1, it is characterised in that the depth of source slot (10) is equal to channel layer (6) and barrier layer
(7) gross thickness.
4. device according to claim 1, it is characterised in that the thickness of source electrode (11) is more than the depth of source slot (10).
5. device according to claim 1, it is characterised in that first to m barrier layers thickness is Ti, width is Si, and
From aperture layer (3) both sides inwardly, TiIt is sequentially reduced, S1≤S2≤...≤Si≤…≤Sm, i is integer and m >=i >=1, T1For 1~
10 μm, width S1For 0.5~1 μm.
6. a kind of method for making grading current barrier layer vertical-type power device, including following process：
A. the extension n on substrate (1)-Type GaN semi-conducting materials, form drift layer (2)；
B. extension n-type GaN semi-conducting materials on drift layer (2), formed thickness be 1~10 μm, doping concentration be 1 × 1015~1
×1018cm-3Aperture layer (3)；
C. make mask for the first time on aperture layer (3), using two side position implantation dosages of the mask in aperture layer be 1 ×
1015~1 × 1016cm-2N-type impurity, make thickness T1For 1~10 μm, width S1For 0.5~1 μm of two the first barrier layers
(41)；
D. carry out m-1 mask successively on aperture layer (3), and utilize mask successively, on preceding two barrier layers once formed
Between the interior both sides implantation dosage of aperture layer (3) be 1 × 1015~1 × 1016cm-2N-type impurity, sequentially form the second barrier layer
(42) to m barrier layers (4m), the m level hierarchic structure current barrier layers that the first barrier layer (41) to m barrier layers (4m) are constituted
(4) aperture (5), are formed between two symmetrical current barrier layers (4), m determines that its value is big according to device actual operation requirements
In the integer equal to 2；
E. in two current barrier layers (4) and aperture (5) upper epitaxial GaN semi-conducting materials, thickness is formed for 0.04~0.2 μm
Channel layer (6)；
F. in channel layer (6) upper epitaxial GaN base semiconductor material with wide forbidden band, the barrier layer (7) that thickness is 5~50nm is formed；
G. in the upper epitaxial p-type GaN semi-conducting materials of barrier layer (7), the p-type cap layers that thickness is 0.02~0.25 μm are formed
(8)；
H. mask is made in p-type cap layers (8), is performed etching using the mask in the p-type cap layers left and right sides, and etched area depth
Equal to the thickness of p-type cap layers, step (9) is formed；
I. mask is made on barrier layer (7) top and p-type cap layers top not covered by p-type cap layers (8), is existed using the mask
Barrier layer (7) arranged on left and right sides is performed etching, and untill being etched to the upper surface of two current barrier layers (4), forms left and right two
Individual source slot (10)；
J. barrier layer (7) top and p-type cap layers (8) top not covered by p-type cap layers (8) on two source slot (10) tops,
Mask is made, metal is deposited in two source slots (10) using the mask, and the thickness of deposited metal is more than source slot (10)
Depth, to make source electrode (11)；
K. barrier layer (7) top and p-type cap layers (8) top not covered on source electrode (11) top, by p-type cap layers (8) make
Mask, deposits metal, to make grid (12) using the mask on p-type cap layers (8) top；
L. metal is deposited on the back side of substrate (1), to make drain electrode (13).
7. method according to claim 6, it is characterised in that the thickness T of the first barrier layer (41)1For 1~10 μm.
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| CN113707713A (en) * | 2021-08-31 | 2021-11-26 | 西安电子科技大学 | Multi-stage petal-shaped body region metal oxide semiconductor power device and manufacturing method thereof |
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| US20120319127A1 (en) * | 2011-06-20 | 2012-12-20 | The Regents Of The University Of California | Current aperture vertical electron transistors with ammonia molecular beam epitaxy grown p-type gallium nitride as a current blocking layer |
| WO2015176002A1 (en) * | 2014-05-15 | 2015-11-19 | The Regents Of The University Of California | Doping in iii-nitride devices |
| WO2015175915A1 (en) * | 2014-05-15 | 2015-11-19 | The Regents Of The University Of California | Trenched vertical power field-effect transistors with improved on-resistance and breakdown voltage |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111354777A (en) * | 2018-12-24 | 2020-06-30 | 东南大学 | Heterojunction semiconductor device with low on-resistance |
| CN113707713A (en) * | 2021-08-31 | 2021-11-26 | 西安电子科技大学 | Multi-stage petal-shaped body region metal oxide semiconductor power device and manufacturing method thereof |
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