CN107154435B - Grading current barrier layer vertical-type power device - Google Patents

Grading current barrier layer vertical-type power device Download PDF

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CN107154435B
CN107154435B CN201710198227.5A CN201710198227A CN107154435B CN 107154435 B CN107154435 B CN 107154435B CN 201710198227 A CN201710198227 A CN 201710198227A CN 107154435 B CN107154435 B CN 107154435B
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barrier layer
layer
aperture
cap layers
thickness
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CN107154435A (en
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毛维
石朋毫
边照科
郝跃
马晓华
李康
谢涌
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Xian University of Electronic Science and Technology
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0626Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a localised breakdown region, e.g. built-in avalanching region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Abstract

The invention discloses a kind of grading current barrier layer vertical-type power devices, it is big with conducting resistance mainly to solve the problems, such as that existing similar device breakdown potential is forced down, comprising: substrate (1), drift layer (2), aperture layer (3), the symmetrical multistage hierarchic structure current barrier layer (4) in left and right two, channel layer (6) and barrier layer (7), the two sides of channel layer (6) and barrier layer (7) are etched with source slot (10), there are two source electrode (11) for deposit in two sides source slot (10), extension has p-type cap layers (8) on barrier layer between source electrode (11), it is carved with step (9) in p-type cap layers (8) two sides, p-type cap layers (8) are deposited over grid (12), substrate (1) is deposited with drain electrode (13) below, aperture (5) are formed between two symmetrical current barrier layers (4).Breakdown voltage height of the present invention, simple process, conducting resistance be small, high yield rate, can be used for power electronic system.

Description

Grading current barrier layer vertical-type power device
Technical field
The invention belongs to microelectronics technologies, are related to semiconductor devices, especially grading current barrier layer vertical-type function Rate device, can be used for power electronic system.
Technical background
Power semiconductor is the core element of power electronic technique, with becoming increasingly conspicuous for energy and environmental problem, Research and develop novel high-performance, low-loss power device just becomes raising utilization rate of electrical, energy saving, alleviating energy crisis effective One of approach.And in power device research, between high speed, high pressure and low on-resistance, there is serious restricting relations, close Managing, effectively improving this restricting relation is the key that improve device overall performance.With the development of microelectric technique, tradition the Generation Si semiconductor and second generation GaAs semiconductor power device performance have been approached the theoretical limit that its material itself determines.In order to It can be further reduced chip area, working frequency is improved, improve operating temperature, reduce conducting resistance, improve breakdown voltage, reduce Machine volume improves overall efficiency, using GaN as the semiconductor material with wide forbidden band of representative, by its bigger forbidden bandwidth, higher Critical breakdown electric field and higher electronics saturation drift velocity, and stable chemical performance, high temperature resistant, anti-radiation etc. protrusion it is excellent Point, shows one's talent in terms of preparing high performance power device, and application potential is huge.Especially with GaN base heterojunction structure Lateral high electron mobility transistor, i.e., lateral GaN base high electron mobility transistor (HEMT) device, even more because of its low electric conduction The characteristics such as resistance, high-breakdown-voltage, high working frequency become the hot spot studied and applied both at home and abroad, focus.
However, in order to obtain higher breakdown voltage, need to increase grid leak spacing in lateral GaN base HEMT device, this It will increase device size and conducting resistance, reduce effective current density and chip performance on unit chip area, so as to cause The increase of chip area and development cost.In addition, in lateral GaN base HEMT device, as caused by high electric field and surface state Current collapse problem is more serious, although currently having numerous braking measures, current collapse problem is not obtained still thoroughly It solves.To solve the above-mentioned problems, researchers propose vertical-type GaN base current apertures hetero junction field effect device, and A kind of current barrier layer vertical-type power device, referring to AlGaN/GaN current aperture vertical electron transistors,IEEE Device Research Conference,pp.31-32,2002.GaN base current apertures hetero-junctions Fieldtron can improve breakdown voltage by increasing drift layer thickness, avoid and sacrifice asking for device size and conducting resistance Topic, therefore high power density chip may be implemented.And in GaN base current apertures hetero junction field effect device, high electric field area Domain is located in semiconductor material body, this can thoroughly eliminate current collapse problem.2004, Ilan Ben-Yaacov et al. AlGaN/GaN current apertures hetero junction field effect device is developed using MOCVD regrowth trench technology after etching, the device is not Using passivation layer, maximum output current 750mA/mm, mutual conductance 120mS/mm, both ends grid breakdown voltage is 65V, and electric current collapses Effect of collapsing is significantly inhibited, referring to AlGaN/GaN current aperture vertical electron transistors with regrown channels,Journal of Applied Physics,Vol.95,No.4, pp.2073-2078,2004.2012, Srabanti Chowdhury et al. utilized Mg ion implanting current barrier layer combination etc. The technology of ion auxiliary MBE regrowth AlGaN/GaN hetero-junctions develops the current apertures heterojunction field effect based on GaN substrate Device is answered, which uses 3 μm of drift regions, maximum output current 4kAcm-2, conducting resistance is 2.2m Ω cm2, breakdown Voltage is 250V, and inhibits current collapse effect good, referring to CAVET on Bulk GaN Substrates Achieved With MBE-Regrown AlGaN/GaN Layers to Suppress Dispersion,IEEE Electron Device Letters,Vol.33,No.1,pp.41-43,2012.The same year, a kind of enhancing proposed by Masahiro Sugimoto et al. Type GaN base current apertures hetero junction field effect device is authorized, referring to Transistor, US8188514B2,2012.In addition, 2014, Hui Nie et al. was based on GaN substrate and develops a kind of enhanced GaN base current apertures hetero junction field effect device, should Device threshold voltage is 0.5V, and saturation current is greater than 2.3A, breakdown voltage 1.5kV, and conducting resistance is 2.2m Ω cm2, ginseng See 1.5-kV and 2.2-m Ω-cm2Vertical GaN Transistors on Bulk-GaN Substrates,IEEE Electron Device Letters,Vol.35,No.9,pp.939-941,2014。
Traditional GaN base current apertures hetero junction field effect device is to be based on GaN base wide bandgap semiconductor heterojunction structure, It include: substrate 1, drift layer 2, aperture layer 3, left and right two symmetrical current barrier layers 4, aperture 5, channel layer 6 and barrier layer 7; The two sides of channel layer 6 and barrier layer 7 are etched with source slot 10, source electrode 11 there are two deposits in two sides source slot 10, between source electrode 11 Extension has p-type cap layers 8 on barrier layer, and 8 two sides of p-type cap layers quarter, there are two steps 9, and p-type cap layers 8 are deposited over grid 12, lining Bottom 1 is deposited with drain electrode 13 below, as shown in Figure 1.
By the theory and experimental study of more than ten years, researchers' discovery, above-mentioned tradition GaN base current apertures heterojunction field There are inherent shortcoming in effect device structure, it is extremely uneven to will lead to electric-field intensity distribution in device, especially in current blocking Layer with, there are high peak electric field, hit too early so as to cause device in the semiconductor material of aperture area interface close beneath It wears.This to be difficult to realize the thickness by increasing N-shaped GaN drift layer in actual process come the breakdown potential of constantly improve device Pressure.Therefore, the breakdown voltage of traditional structure GaN base current apertures hetero junction field effect device is not generally high.It is higher in order to obtain Device electric breakdown strength, and can by increasing the thickness of N-shaped GaN drift layer come the breakdown voltage of constantly improve device, 2013 Year, it is heterogeneous that Zhongda Li et al. people using technology of numerical simulation has studied a kind of enhanced GaN base current apertures based on superjunction Junction field effect device, result of study shows the field distribution that super-junction structure can effectively inside modulation device, when making in OFF state Electric field strength tends to be uniformly distributed device inside everywhere, therefore device electric breakdown strength is up to 5~20kV, and wide using 3 μm of attached columns When breakdown voltage be 12.4kV, and conducting resistance be 4.2m Ω cm2, referring to Design and Simulation of 5-20- kV GaN Enhancement-Mode Vertical Superjunction HEMT,IEEE Transactions on Electron Decices,Vol.60,No.10,pp.3230-3237,2013.Using the GaN base current apertures hetero-junctions of superjunction Fieldtron can theoretically obtain high-breakdown-voltage, and breakdown voltage can be realized with the increase of N-shaped GaN drift layer thickness And it is constantly improve, it is to have reported the highest a kind of very effective high power device knot of breakdown voltage in document both at home and abroad at present Structure.However, in the GaN base current apertures hetero junction field effect device using super-junction structure, when break-over of device near superjunction Additional conducting resistance can be generated, and the conducting resistance can be continuously increased with the increase of drift layer thickness, thus while device The breakdown voltage of part is improved with the increase of drift layer thickness, but the conducting resistance of device can also accordingly increase, device There is no thoroughly solve for contradiction between middle breakdown voltage and conducting resistance.Therefore, explore and research and develop breakdown voltage height, electric conduction Small novel GaN base current apertures hetero junction field effect device is hindered, it is very necessary, urgent, it has important practical significance.
Summary of the invention
It is an object of the invention to be directed to the deficiency of above-mentioned prior art, a kind of grading current barrier layer vertical-type function is provided Rate device improves the breakdown voltage of device to reduce the conducting resistance of device, and realizes the sustainable increase of breakdown voltage, shows The contradiction alleviated between device electric breakdown strength and conducting resistance is write, the breakdown characteristics of device are improved.
To achieve the goals above, the technical scheme of the present invention is realized as follows:
One, device architecture
A kind of grading current barrier layer vertical-type power device, comprising: substrate 1, drift layer 2, aperture layer 3, two are symmetrically Current barrier layer 4, channel layer 6 and barrier layer 7, the two sides of channel layer 6 and barrier layer 7 are etched with source slot 10, two sides source slot 10 Middle deposit is there are two source electrode 11, and extension has a p-type cap layers 8 on the barrier layer between source electrode 11, and 8 two sides of p-type cap layers carve that there are two platforms Rank 9, p-type cap layers 8 are deposited over a grid 12, and substrate 1 is deposited with drain electrode 13 below, between two symmetrical current barrier layers 4 Form aperture 5, it is characterised in that:
Described two current barrier layers 4, be by from the first inside barrier layer 41 of 3 two sides of aperture layer, the second barrier layer 42, Two symmetrical m grades of hierarchic structures that third barrier layer 43 to the barrier layer m 4m is collectively formed, wherein the first barrier layer 41 is located at Outermost two sides in aperture layer 3.
Two, production method
The method that the present invention makes grading current barrier layer vertical-type power device, comprises the following processes:
A. n is being used+Epitaxial thickness is 3~10 μm on the substrate 1 of profile material GaN, doping concentration is 1 × 1015~1 × 1018cm-3N-Type GaN semiconductor material forms drift layer 2;
B. the extension N-shaped GaN semiconductor material on drift layer 2, being formed with a thickness of 1~10 μm, doping concentration is 1 × 1015 ~1 × 1018cm-3Aperture layer 3;
C. mask is made for the first time on aperture layer 3, be 1 using two side position implantation dosages of the mask in aperture layer ×1015~1 × 1016cm-2N-type impurity, make thickness T1It is 1~10 μm, width S1For 0.5~1 μm of two first blockings Layer 41;
D. m-1 mask is successively carried out on aperture layer 3, and successively utilizes mask, is stopped in preceding two once formed Two sides implantation dosage is 1 × 10 in aperture layer 3 between layer15~1 × 1016cm-2N-type impurity, sequentially form the second barrier layer 42 to the barrier layer m 4m, the m grade hierarchic structure current barrier layer 4 that the first barrier layer 41 to the barrier layer m 4m is constituted, two right Aperture 5 is formed between the current barrier layer 4 of title, m is determined according to device actual operation requirements, and value is the integer more than or equal to 2;
E. it in 5 upper epitaxial GaN semiconductor material of two current barrier layers 4 and aperture, is formed with a thickness of 0.04~0.2 μm Channel layer 6;
F. in 6 upper epitaxial GaN base semiconductor material with wide forbidden band of channel layer, the barrier layer 7 with a thickness of 5~50nm is formed;
G. in the upper epitaxial p-type GaN semiconductor material of barrier layer 7, the p-type cap layers with a thickness of 0.02~0.25 μm are formed 8;
H. mask is made in p-type cap layers 8, is performed etching at left and right sides of p-type cap layers using the mask, and etched area is deep Degree is equal to the thickness of p-type cap layers, forms step 9, and the p-type cap layers 8 and two current barrier layers 4 between two steps 9 are in level Overlapping length on direction is all larger than 0 μm;
I. mask is made on 7 top of potential barrier not covered by p-type cap layers 8 and p-type cap layers top, using the mask in gesture 7 arranged on left and right sides of barrier layer performs etching, and until being etched to the upper surface of two current barrier layers 4, forms left and right two source slots 10;
J. 7 top of barrier layer not covered on two 10 tops of source slot, by p-type cap layers 8 and the production of 8 top of p-type cap layers Mask deposits metal using the mask in two source slots 10, and the thickness of deposited metal is greater than the depth of source slot 10, with system Make source electrode 11;
K. 7 top of barrier layer covered on 11 top of source electrode, not by p-type cap layers 8 and 8 top of p-type cap layers make mask, Metal is deposited on 8 top of p-type cap layers using the mask, to make grid 12;
L. metal is deposited on the back side of substrate 1, with production drain electrode 13.
Device of the present invention has the advantage that compared with traditional GaN base current apertures hetero junction field effect device
1. realizing breakdown voltage to continue to increase.
The present invention makes the barrier layers at different levels of device inside and aperture layer have a common boundary using the current barrier layer of multistage stepped-style Face close beneath can generate a peak electric field, and by adjusting the thickness, width and doping concentration on barrier layers at different levels, can be with So that barrier layers at different levels are approximately equal with the peak electric field of aperture layer interface close beneath, and it is less than GaN base broad stopband and partly leads The breakdown electric field of body material, to improve the breakdown voltage of device;In addition, can by the ladder number for increasing current barrier layer Realize continuing to increase for breakdown voltage.
2. device on-resistance can be slightly reduced while improving device electric breakdown strength.
The present invention improves device electric breakdown strength by using the current barrier layer structure of multistage stepped-style, due to first Barrier layer to the barrier layer m is sequentially reduced away from the horizontal distance at drift layer center, when break-over of device, is removed in device drift layer Depletion region caused by the barrier layer m can have an impact to transporting for electric current, generate outside conducting resistance, remaining barrier layer institute at different levels The depletion region of generation is due to separate aperture center, i.e. current path, so hardly influencing the conducting resistance of device.Pass through tune Thickness, width and the doping concentration on barrier layer at different levels, can also further decrease the conducting resistance of device in whole device of the present invention. Therefore, as current barrier layer step number purpose increases, the breakdown voltage of device continues to increase, and conducting resistance can slightly subtract It is small.
Technology contents and effect of the invention are further illustrated below in conjunction with drawings and examples.
Detailed description of the invention
Fig. 1 is the structure chart of traditional GaN base current apertures hetero junction field effect device;
Fig. 2 is the structure chart of grading current barrier layer vertical-type power device of the present invention;
Fig. 3 is the flow chart of present invention production grading current barrier layer vertical-type power device;
Fig. 4 is to the two dimensional electric field distribution map in the case of breakdown obtained by traditional devices and device simulation of the present invention;
Fig. 5 is to the output current graph in the case of forward conduction obtained by traditional devices and device simulation of the present invention.
Specific embodiment
Referring to Fig. 2, grading current barrier layer vertical-type power device of the present invention is heterogeneous based on GaN base wide bandgap semiconductor Junction structure comprising: substrate 1, aperture layer 3, has left and right two symmetrical current barrier layers 4, aperture in aperture layer 3 at drift layer 2 5, the two sides of channel layer 6 and barrier layer 7, channel layer 6 and barrier layer 7 are etched with source slot 10, in two sides source slot 10 there are two deposits Source electrode 11, extension has a p-type cap layers 8 on the barrier layer between source electrode 11, and 8 two sides of p-type cap layers carve that there are two step 9, p-type cap layers 8 Deposited over to have grid 12, substrate 1 is deposited with drain electrode 13 below.Wherein:
The drift layer 2 is located at 1 top of substrate, is 1 × 10 with a thickness of 3~10 μm, doping concentration15~1 × 1018cm-3
The aperture layer 3 is located at 2 top of drift layer, is 1 × 10 with a thickness of 1~10 μm, doping concentration15~1 × 1018cm-3
Described two current barrier layers 4, be by from the first inside barrier layer 41 of 3 two sides of aperture layer, the second barrier layer 42, Two symmetrical m grades of hierarchic structures that third barrier layer 43 to the barrier layer m 4m is collectively formed, series m are according to device reality Requirement determines that value is the integer more than or equal to 2;First barrier layer 41 is located at the outermost two sides in aperture layer 3, each to stop Layer is all made of p-type doping;First to the barrier layer m with a thickness of Ti, width Si, and, T inside from 3 two sides of aperture layeriSuccessively Reduce, S1≤S2≤...≤Si≤…≤Sm, i is integer and m >=i >=1, T1It is 1~10 μm, width S1It is 0.5~1 μm, T1For The thickness on the first barrier layer 41, S1For the width on the first barrier layer 41;
The aperture 5 is located between two current barrier layers 4;
The channel layer 6 is located at 5 top of two current barrier layers 4 and aperture, with a thickness of 0.04~0.2 μm;
The barrier layer 7 is located at 6 top of channel layer, by the identical or different GaN base wide bandgap semiconductor material of several layers Material composition, with a thickness of 5~50nm;
The p-type cap layers 8 are all larger than 0 μm with the overlapping length of two current barrier layers 4 in the horizontal direction;
The source slot 10, depth are equal to the overall thickness of channel layer 6 and barrier layer 7;
The source electrode 11, thickness are greater than the depth of source slot 10.
Referring to Fig. 3, the present invention makes the process of grading current barrier layer vertical-type power device, provides following three kinds of implementation Example:
Embodiment one: the grading current barrier layer vertical-type power device that production current barrier layer ladder series m is 2.
Step 1. extension n on substrate 1-Type GaN forms drift layer 2, such as Fig. 3 a.
Using n+Type GaN does substrate 1, and using metal organic chemical vapor deposition technology, epitaxial thickness is on substrate 1 3 μm, doping concentration be 1 × 1015cm-3N-Type GaN material forms drift layer 2, in which:
The process conditions that extension uses are as follows: temperature is 950 DEG C, pressure 40Torr, with SiH4For doped source, hydrogen flowing quantity For 4000sccm, ammonia flow 4000sccm, gallium source flux is 100 μm of ol/min.
Step 2. extension N-shaped GaN on drift layer forms aperture layer 3, such as Fig. 3 b.
Using metal organic chemical vapor deposition technology, on drift layer 2 epitaxial thickness be 1 μm, doping concentration be 1 × 1015cm-3N-shaped GaN material, formed aperture layer 3, in which:
The process conditions that extension uses are as follows: temperature is 950 DEG C, pressure 40Torr, with SiH4For doped source, hydrogen flowing quantity For 4000sccm, ammonia flow 4000sccm, gallium source flux is 100 μm of ol/min.
Step 3. makes the first barrier layer 41, such as Fig. 3 c.
First mask is made for the first time on aperture layer 3;
Ion implantation technique is reused, the two side position implantation dosages in aperture layer are 1 × 1015cm-2N-type impurity Mg makes thickness T1It is 1 μm, width S1For 0.5 μm of two the first barrier layers 41.
Step 4. makes the second barrier layer 42, such as Fig. 3 d.
First second of production mask on aperture layer 3 and two the first barrier layers 41;
Ion implantation technique is reused, two side positions inject in the aperture layer between left and right two the first barrier layers 41 Dosage is 4.5 × 1015cm-2N-type impurity Mg, formed thickness T2It is 0.5 μm, width S2For 1 μm of two the second barrier layers 42, First barrier layer 41 and the second barrier layer 42 constitute current barrier layer 4, the current barrier layer 4 of two symmetrical second level hierarchic structure Between formed aperture 5.
Step 5. extension GaN material makes channel layer 6, such as Fig. 3 e.
Using molecular beam epitaxy technique, outside the top in two the second barrier layers 42 of 41, two, the first barrier layer and aperture 5 Prolong the GaN material with a thickness of 0.04 μm, forms channel layer 6;
The molecular beam epitaxy technique, process conditions are as follows: vacuum degree is less than or equal to 1.0 × 10-10Mbar, radio-frequency power For 400W, reactant uses N2, the high-purity source Ga.
Step 6. extension Al0.5Ga0.5N makes barrier layer 7, such as Fig. 3 f.
The Al that epitaxial thickness is 5nm on channel layer 6 using molecular beam epitaxy technique0.5Ga0.5N material forms barrier layer 7, in which:
The process conditions of molecular beam epitaxy are as follows: vacuum degree is less than or equal to 1.0 × 10-10Mbar, radio-frequency power 400W, instead Answer agent using N2, the high-purity source Ga, high-purity source Al.
Step 7. is in 7 upper epitaxial p-type cap layers 8 of barrier layer, such as Fig. 3 g.
Using molecular beam epitaxy technique, in 7 upper epitaxial of barrier layer with a thickness of 0.02 μm of p-type GaN material, to make p Type cap layers 8;
The molecular beam epitaxy technique, process conditions are as follows: vacuum degree is less than or equal to 1.0 × 10-10Mbar, radio-frequency power For 400W, reactant uses N2, the high-purity source Ga, high-purity source Mg.
Step 8. etches production step 9 in 8 arranged on left and right sides of p-type cap layers, such as Fig. 3 h.
Mask is made in p-type cap layers 8, is cap in cap layers arranged on left and right sides etching depth using reactive ion etching technology The etched area of thickness degree forms step 9, and the p-type cap layers 8 and two current barrier layers 4 between two steps are in the horizontal direction Overlapping length be 0.5 μm;
The process conditions of reactive ion etching are as follows: Cl2Flow is 15sccm, pressure 10mTorr, power 100W.
Step 9. etches production source slot 10 at left and right sides of barrier layer 7 and channel layer 6, such as Fig. 3 i.
First mask is made on 7 top of barrier layer not covered by p-type cap layers 8 and 8 top of p-type cap layers;
Reactive ion etching technology is reused, is performed etching in the arranged on left and right sides of barrier layer 7, and is etched to two electric currents Until the upper surface on barrier layer 4, left and right two source slots 10 are formed;
The process conditions of reactive ion etching are as follows: Cl2Flow is 15sccm, pressure 10mTorr, power 100W.
Step 10. makes source electrode 11, such as Fig. 3 j.
First two 10 tops of source slot, do not covered by 7 top of barrier layer that p-type cap layers 8 cover and the production of 8 top of p-type cap layers Mould;
Electron beam evaporation technique is reused, metal is combined in two 10 top of source slot deposit Ti/Au/Ni, forms source electrode 11, Wherein: the metal deposited, from bottom to top, Ti with a thickness of 0.02 μm, Au with a thickness of 0.3 μm, Ni with a thickness of 0.05 μm;
The process conditions of electron beam evaporation are as follows: vacuum degree is less than 1.8 × 10-3Pa, power bracket are 200~1000W, evaporation Rate is less than
Step 11. makes grid 12, such as Fig. 3 k.
11a) covered on 11 top of source electrode, not by 7 top of barrier layer that p-type cap layers 8 cover and the production of 8 top of p-type cap layers Mould;
Electron beam evaporation technique 11b) is used, Ni/Au/Ni is deposited in p-type cap layers 8 and combines metal, forms grid 12, In: the metal deposited from bottom to top, Ni with a thickness of 0.02 μm, Au with a thickness of 0.2 μm, Ni with a thickness of 0.04 μm;
The process conditions of electron beam evaporation are as follows: vacuum degree is less than 1.8 × 10-3Pa, power bracket are 200~1000W, evaporation Rate is less than
Step 12. production drain electrode 13, such as Fig. 3 l.
Using electron beam evaporation technique, metal Ti, Au, Ni are successively deposited on the back side of entire substrate 1, form drain electrode 13, in which: the metal deposited, Ti with a thickness of 0.02 μm, Au with a thickness of 0.7 μm, Ni with a thickness of 0.05 μm, complete whole The production of a device;
Deposit process conditions used by metal are as follows: vacuum degree is less than 1.8 × 10-3Pa, power bracket are 200~1000W, Evaporation rate is less than
Embodiment two: the grading current barrier layer vertical-type power device that production current barrier layer ladder series m is 2.
First step extension n on substrate-Type GaN forms drift layer 2, such as Fig. 3 a.
It is 1000 DEG C in temperature, pressure 45Torr, with SiH4For doped source, hydrogen flowing quantity 4400sccm, ammonia flow Amount is 4400sccm, and gallium source flux is under the process conditions of 110 μm of ol/min, using n+Type GaN does substrate 1, is had using metal Machine object chemical vapor deposition techniques, epitaxial thickness is 5 μm on substrate 1, doping concentration is 1 × 1016cm-3N-Type GaN material, Complete the production of drift layer 2.
Second step extension N-shaped GaN on drift layer forms aperture layer 3, such as Fig. 3 b.
It is 1000 DEG C in temperature, pressure 45Torr, with SiH4For doped source, hydrogen flowing quantity 4400sccm, ammonia flow Amount is 4400sccm, and gallium source flux is to use metal organic chemical vapor deposition skill under the process conditions of 110 μm of ol/min Art, epitaxial thickness is 3 μm on drift layer 2, doping concentration is 1 × 1016cm-3N-shaped GaN material, complete aperture layer 3 system Make.
Third step makes the first barrier layer 41, such as Fig. 3 c.
3.1) mask is made for the first time on aperture layer 3;
3.2) ion implantation technique is used, the two side position implantation dosages in aperture layer are 4 × 1015cm-2P-type it is miscellaneous Matter Mg forms thickness T1It is 3 μm, width S1For 0.6 μm of two the first barrier layers 41.
4th step makes the second barrier layer 42, such as Fig. 3 d.
4.1) second of production mask on aperture layer 3 and two the first barrier layers 41;
4.2) ion implantation technique is used, two sides implantation dosage is 5 in the aperture layer between left and right first barrier layer 41 ×1015cm-2N-type impurity Mg, formed thickness T2It is 1 μm, width S2Stop for 1.5 μm of two the second barrier layers 42, first Layer 41 and the second barrier layer 42 constitute current barrier layer 4, are formed between the current barrier layer 4 of two symmetrical second level hierarchic structure Aperture 5.
5th step extension GaN material makes channel layer 6, such as Fig. 3 e.
It is less than or equal to 1.0 × 10 in vacuum degree-10Mbar, radio-frequency power 400W, reactant use N2, the high-purity source Ga Under process conditions, using molecular beam epitaxy technique, on two the second barrier layers 42 of 41, two, the first barrier layer and 5 top of aperture, The GaN material that epitaxial thickness is 0.1 μm completes the production of channel layer 6.
6th step extension Al0.3Ga0.7N makes barrier layer 7, such as Fig. 3 f.
It is less than or equal to 1.0 × 10 in vacuum degree-10Mbar, radio-frequency power 400W, reactant use N2, the high-purity source Ga, height Under the process conditions in the pure source Al, using molecular beam epitaxy technique, epitaxial thickness is the Al of 30nm on channel layer 60.3Ga0.7N material Material completes the production of barrier layer 7.
7th step is in 7 upper epitaxial p-type cap layers 8 of barrier layer, such as Fig. 3 g.
It is less than or equal to 1.0 × 10 in vacuum degree-10Mbar, radio-frequency power 400W, reactant use N2, the high-purity source Ga, height Under the process conditions in the pure source Mg, using molecular beam epitaxy technique, in 7 upper epitaxial of barrier layer with a thickness of 0.15 μm of p-type GaN material Material completes the production of p-type cap layers 8.
8th step etches production step 9 in 8 arranged on left and right sides of p-type cap layers, such as Fig. 3 h.
8.1) mask is made in p-type cap layers 8;
8.2) in Cl2Flow is 15sccm, pressure 10mTorr, and power is under the process conditions of 100W, using reaction from Sub- lithographic technique is 0.15 μm of etched area in cap layers arranged on left and right sides etching depth, completes the production of step 9, two steps it Between p-type cap layers 8 and two current barrier layers 4 overlapping length in the horizontal direction be 0.5 μm.
9th step etches production source slot 10 at left and right sides of barrier layer 7 and channel layer 6, such as Fig. 3 i.
9.1) mask is made on 7 top of barrier layer not covered by p-type cap layers 8 and 8 top of p-type cap layers;
9.2) in Cl2Flow is 15sccm, pressure 10mTorr, and power is under the process conditions of 100W, using reaction from Sub- lithographic technique is performed etching in the arranged on left and right sides of barrier layer 7, and until being etched to the upper surface of two current barrier layers 4, Form left and right two source slots 10.
Tenth step makes source electrode 11, such as Fig. 3 j.
10.1) the 8 top system of 7 top of barrier layer and p-type cap layers covered on two 10 tops of source slot, not by p-type cap layers 8 Make mask;
10.2) in vacuum degree less than 1.8 × 10-3Pa, power bracket are 200~1000W, and evaporation rate is less than's Under process conditions, using electron beam evaporation technique, metal is combined in two 10 top of source slot deposit Ti/Au/Ni, forms source electrode 11, in which: the metal deposited, from bottom to top, Ti with a thickness of 0.02 μm, Au with a thickness of 0.3 μm, Ni with a thickness of 0.05 μm。
11st step makes grid 12, such as Fig. 3 k.
11.1) it is covered on 11 top of source electrode, not by 7 top of barrier layer that p-type cap layers 8 cover and the production of 8 top of p-type cap layers Mould;
11.2) in vacuum degree less than 1.8 × 10-3Pa, power bracket are 200~1000W, and evaporation rate is less than's Under process conditions, using electron beam evaporation technique, Ni/Au/Ni is deposited in p-type cap layers 8 and combines metal, completes the system of grid 12 Make, and from bottom to top, Ni with a thickness of 0.02 μm, Au with a thickness of 0.2 μm, Ni with a thickness of 0.04 μm.
12nd step production drain electrode 13, such as Fig. 3 l.
In vacuum degree less than 1.8 × 10-3Pa, power bracket are 200~1000W, and evaporation rate is less thanTechnique item Under part, using electron beam evaporation technique, metal Ti, Au, Ni is successively deposited at entire 1 back side of substrate, forms Ti/Au/Ni combination Metal, with production drain electrode 13, and Ti with a thickness of 0.02 μm, Au with a thickness of 0.7 μm, Ni with a thickness of 0.05 μm, and complete The production of entire device.
Embodiment three: the grading current barrier layer vertical-type power device that production current barrier layer ladder series m is 4
Step A. uses temperature for 950 DEG C, pressure 40Torr, with SiH4For doped source, hydrogen flowing quantity 4000sccm, Ammonia flow is 4000sccm, and gallium source flux is the process conditions of 100 μm of ol/min, using n+Type GaN does substrate 1, uses gold Belong to organic chemical vapor deposition technology, epitaxial thickness is 10 μm on substrate, doping concentration is 1 × 1018cm-3N-Type GaN Material makes drift layer 2, such as Fig. 3 a.
Step B. uses temperature for 950 DEG C, pressure 40Torr, with SiH4For doped source, hydrogen flowing quantity 4000sccm, Ammonia flow is 4000sccm, and gallium source flux is the process conditions of 100 μm of ol/min, uses metal organic chemical vapor deposition Technology, epitaxial thickness is 10 μm on drift layer 2, doping concentration is 1 × 1018cm-3N-shaped GaN material, make aperture layer 3, Such as Fig. 3 b.
Step C. makes mask on aperture layer 3 for the first time, reuses ion implantation technique, the two sides position in aperture layer Setting implantation dosage is 1 × 1016cm-2N-type impurity Mg, formed thickness T1It is equal with aperture layer thickness, width S1For two of 1 μm First barrier layer 41, such as Fig. 3 c.
Step D. makes two 42, two, the second barrier layer third barrier layers 43 and two the 4th barrier layers, such as Fig. 3 d.
D1 it) first makes mask for the second time on aperture layer 3 and two the first barrier layers 41, reuses ion implantation technique, Inner side implantation dosage on left and right first barrier layer 41 is 1 × 1016cm-2N-type impurity Mg, formed thickness T2For 0.8 μ M, width S2For 1.1 μm of two the second barrier layers 42;
D2 mask) is made for the third time on 3, two the first barrier layers 41 of aperture layer and two the second barrier layers 42, then is made With ion implantation technique, two side position implantation dosages are 1 × 10 in the aperture layer between left and right second barrier layer 4216cm-2 N-type impurity Mg, formed thickness T3It is 0.5 μm, width S3For 1.5 μm of two third barrier layers 43;
D3) on aperture layer 3, two the first barrier layers, 41, two the second barrier layers 42 and two third barrier layers 43 Four production masks, reuse ion implantation technique, and two side positions inject in the aperture layer between left and right third barrier layer 43 Dosage is 1 × 1016cm-2N-type impurity Mg, formed thickness T4It is 0.15 μm, width S4For 2 μm of two the 4th barrier layers, One barrier layer 41, the second barrier layer 42, third barrier layer 43 and the 4th barrier layer composition current barrier layer 4, two symmetrical four Aperture 5 is formed between grade stairstepping current barrier layer 4.
Step E. is less than or equal to 1.0 × 10 using vacuum degree-10Mbar, radio-frequency power 400W, reactant use N2, it is high The process conditions in the pure source Ga, using molecular beam epitaxy technique, on two 41, two, the first barrier layers, 42, two, the second barrier layer The 4th barrier layer of 43, two, third barrier layer and 5 upper epitaxial of aperture are such as schemed with a thickness of the channel layer 6 of 0.2 μm of GaN material 3e。
Step F. is less than or equal to 1.0 × 10 using vacuum degree-10Mbar, radio-frequency power 400W, reactant use N2, it is high The process conditions in the pure source Ga, high-purity source Al, using molecular beam epitaxy technique, epitaxial thickness is 50nm's on channel layer 6 Al0.1Ga0.9The barrier layer 7 of N material, such as Fig. 3 f.
Step G. is less than or equal to 1.0 × 10 using vacuum degree-10Mbar, radio-frequency power 400W, reactant use N2, it is high The process conditions in the pure source Ga, high-purity source Mg, using molecular beam epitaxy technique, in 7 upper epitaxial of barrier layer with a thickness of 0.25 μm of p Type GaN material completes the production of p-type cap layers 8, such as Fig. 3 g.
Step H. makes mask in p-type cap layers 8, then uses Cl2Flow is 15sccm, pressure 10mTorr, and power is The process conditions of 100W, using reactive ion etching technology, in the etched area that cap layers arranged on left and right sides etching depth is 0.25 μm, The production of step 9 is completed, the overlapping length of p-type cap layers 8 and two current barrier layers 4 in the horizontal direction between two steps It is 0.6 μm, such as Fig. 3 h.
Step I. makes mask on 7 top of barrier layer not covered by p-type cap layers 8 and 8 top of p-type cap layers, then uses Cl2Flow is 15sccm, and pressure 10mTorr, power is the process conditions of 100W, using reactive ion etching technology, in gesture The arranged on left and right sides of barrier layer 7 performs etching, and until being etched to the upper surface of two current barrier layers 4, forms left and right two sources Slot 10, such as Fig. 3 i.
8 top of 7 top of barrier layer and p-type cap layers that step J. is covered on two 10 tops of source slot, not by p-type cap layers 8 Make mask;Again using vacuum degree less than 1.8 × 10-3Pa, power bracket are 200~1000W, and evaporation rate is less than's Process conditions are deposited metal on two 10 tops of source slot, are made source electrode 11 using electron beam evaporation technique, wherein deposited Metal be Ti/Au/Ni metallic combination, i.e., from bottom to top be respectively Ti, Au and Ni, thickness be followed successively by 0.02 μm, 0.3 μm, 0.05 μm, such as Fig. 3 j.
7 top of barrier layer and the production of 8 top of p-type cap layers that step K. is covered on 11 top of source electrode, not by p-type cap layers 8 Mask;Again using vacuum degree less than 1.8 × 10-3Pa, power bracket are 200~1000W, and evaporation rate is less thanTechnique Condition deposits metal using electron beam evaporation technique in p-type cap layers 8, makes grid 12, wherein the metal deposited is Ni/ Au/Ni metallic combination is respectively Ni, Au and Ni from bottom to top, thickness is followed successively by 0.02 μm, 0.2 μm, 0.04 μm, is such as schemed 3k。
Step L. is using vacuum degree less than 1.8 × 10-3Pa, power bracket are 200~1000W, and evaporation rate is less than Process conditions metal Ti, Au, Ni are successively deposited on the back side of entire substrate 1 using electron beam evaporation technique, form leakage Pole 13, in which: the metal deposited, Ti with a thickness of 0.02 μm, Au with a thickness of 0.7 μm, Ni with a thickness of 0.05 μm, and it is complete At the production of entire device.Such as Fig. 3 l.
Effect of the invention can be further illustrated by following emulation:
Emulation 1: to traditional GaN base current apertures hetero junction field effect device and device of the present invention in the case of a breakdown two Dimension field distribution is emulated, and as a result such as Fig. 4, wherein Fig. 4 (a) is traditional devices, and breakdown voltage 890V, Fig. 4 (b) are this Invention device uses 3 grades of hierarchic structure current barrier layers, breakdown voltage 1830V.
In the case of puncturing it can be seen from Fig. 4 (a), electric-field intensity distribution is extremely uneven in traditional devices, in current blocking Layer with there is high peak electric field in the semiconductor material of aperture area interface close beneath, it is too early so as to cause device Breakdown.In the case of puncturing it can be seen from Fig. 4 (b), below the barrier layers at different levels of device inside of the present invention and aperture layer interface An approximately equal peak electric field is nearby produced, field distribution is more uniform in device, illustrates device architecture of the present invention It can more efficiently modulation device internal electric field be distributed.Therefore the breakdown voltage of device of the present invention is apparently higher than traditional devices Breakdown voltage.
Emulation 2: to traditional GaN base current apertures hetero junction field effect device and device of the present invention in forward conduction Output electric current emulated, as a result such as Fig. 5, wherein device of the present invention is using 3 grades of hierarchic structure current barrier layers.
As seen from Figure 5, in the case of forward conduction, device output current curve of the present invention is bigger in the slope of linear zone In traditional devices output current curve in the slope of linear zone, illustrate that the conducting resistance of device of the present invention is less than leading for traditional devices Be powered resistance.
Above description is only several specific embodiments of the invention, is not construed as limiting the invention, it is clear that for this It, can be without departing substantially from the principle and scope of the present invention after having understood the content of present invention and principle for the professional in field In the case where, various modifications and variations in form and details are carried out according to the method for the present invention, but these are based on the present invention Modifications and variations still within the scope of the claims of the present invention.

Claims (6)

1. a kind of grading current barrier layer vertical-type power device, comprising: substrate (1), drift layer (2), aperture layer (3), two The two sides of symmetrical current barrier layer (4), channel layer (6) and barrier layer (7), channel layer (6) and barrier layer (7) are etched with source slot (10), in two sides source slot (10) there are two deposits source electrode (11), extension has p-type cap layers (8) on the barrier layer between source electrode (11), P-type cap layers (8) two sides quarter, there are two step (9), and p-type cap layers (8) are deposited over to be had grid (12), and substrate (1) is deposited with below It drains (13), forms aperture (5) between two symmetrical current barrier layers (4), it is characterised in that:
Described two symmetrical current barrier layers (4) are by from inside the first barrier layer (41) in aperture layer (3) two sides, second Two symmetrical m grades of hierarchic structures that barrier layer (42), third barrier layer (43) to the barrier layer m (4m) collectively form, wherein First barrier layer (41) is located at the outermost two sides in aperture layer (3).
2. device according to claim 1, it is characterised in that the hierarchic structure series m of current barrier layer (4) is according to device Part actual operation requirements determine that value is the integer more than or equal to 2.
3. device according to claim 1, it is characterised in that the depth of source slot (10) is equal to channel layer (6) and barrier layer (7) overall thickness.
4. device according to claim 1, it is characterised in that the thickness of source electrode (11) is greater than the depth of source slot (10).
5. device according to claim 1, it is characterised in that first to the barrier layer m with a thickness of Ti, width Si, and Inside, the T from aperture layer (3) two sidesiIt is sequentially reduced, S1≤S2≤...≤Si≤…≤Sm, i is integer and m >=i >=1, T1For 1~ 10 μm, width S1It is 0.5~1 μm.
6. a kind of method for making grading current barrier layer vertical-type power device, comprises the following processes:
A. the extension n on substrate (1)-Type GaN semiconductor material is formed drift layer (2);
B. the extension N-shaped GaN semiconductor material on drift layer (2), being formed with a thickness of 1~10 μm, doping concentration is 1 × 1015~1 ×1018cm-3Aperture layer (3);
C. make mask for the first time on aperture layer (3), using two side position implantation dosages of the mask in aperture layer be 1 × 1015~1 × 1016cm-2N-type impurity, make thickness T1It is 1~10 μm, width S1For 0.5~1 μm of two the first barrier layers (41);
D. m-1 mask is successively carried out on aperture layer (3), and successively utilizes mask, on preceding two once formed barrier layer Between the interior two sides implantation dosage of aperture layer (3) be 1 × 1015~1 × 1016cm-2N-type impurity, sequentially form the second barrier layer (42) to the barrier layer m (4m), m grade hierarchic structure current barrier layer that the first barrier layer (41) to the barrier layer m (4m) are constituted (4), aperture (5) are formed between two symmetrical current barrier layers (4), m determines that value is big according to device actual operation requirements In the integer for being equal to 2;
E. it in two current barrier layers (4) and aperture (5) upper epitaxial GaN semiconductor material, is formed with a thickness of 0.04~0.2 μm Channel layer (6);
F. in channel layer (6) upper epitaxial GaN base semiconductor material with wide forbidden band, the barrier layer (7) with a thickness of 5~50nm is formed;
G. in the upper epitaxial p-type GaN semiconductor material of barrier layer (7), the p-type cap layers with a thickness of 0.02~0.25 μm are formed (8);
H. mask is made on p-type cap layers (8), is performed etching at left and right sides of p-type cap layers using the mask, and etched area depth Equal to the thickness of p-type cap layers, formed step (9);
I. mask is made on barrier layer (7) top and p-type cap layers top not covered by p-type cap layers (8), is existed using the mask Barrier layer (7) arranged on left and right sides performs etching, and until being etched to the upper surface of two current barrier layers (4), forms left and right two A source slot (10);
J. barrier layer (7) top and p-type cap layers (8) top covered on two source slot (10) tops, not by p-type cap layers (8) Mask is made, deposits metal in two source slots (10) using the mask, and the thickness of deposited metal is greater than source slot (10) Depth, to make source electrode (11);
K. barrier layer (7) top and p-type cap layers (8) top covered on source electrode (11) top, not by p-type cap layers (8) makes Mask deposits metal on p-type cap layers (8) top using the mask, to make grid (12);
L. metal is deposited on the back side of substrate (1), (13) is drained with production.
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