CN103794560B - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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CN103794560B
CN103794560B CN201210432008.6A CN201210432008A CN103794560B CN 103794560 B CN103794560 B CN 103794560B CN 201210432008 A CN201210432008 A CN 201210432008A CN 103794560 B CN103794560 B CN 103794560B
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substrate
device stack
semiconductor layer
grid
side wall
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CN103794560A (zh
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朱慧珑
骆志炯
尹海洲
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201210432008.6A priority Critical patent/CN103794560B/zh
Priority to US14/439,179 priority patent/US9691899B2/en
Priority to PCT/CN2012/085359 priority patent/WO2014067200A1/zh
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Abstract

本发明提供了一种半导体结构，包括衬底(130)、支撑结构(131)、基底区(100)、栅堆叠、侧墙(240)以及源/漏区，其中，所述栅堆叠位于所述基底区(100)之上，所述基底区(100)由支撑结构(131)支撑于所述衬底(130)之上，其中：所述支撑结构(131)的侧壁截面为∑形；在所述基底区(100)两侧边缘下方存在隔离结构(123)，其中，部分所述隔离结构(123)与所述衬底(130)相连接；在所述隔离结构(123)和所述支撑结构(131)之间存在空腔(112)；以及至少在所述基底区(100)和隔离结构(123)的两侧存在源/漏区。相应地，本发明还提供了该半导体结构的制造方法。

Description

半导体结构及其制造方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体结构及其制造方法。
背景技术
工业需求要求IC电路具有更高的密度并由此减小MOS晶体管的尺寸。然而，MOS晶体管的缩小导致了两个众所周知的寄生效应的出现，即，随着栅极长度的减小而出现的短沟道效应和漏致势垒降低效应，易于恶化器件的电学性能，如造成栅极阈值电压下降、功耗增加以及信噪比下降等问题。从物理上，上述效应可以解释为：当晶体管关断时(栅极电压为零)，非常小的器件中的源/漏区的静电影响或在沟道区上向漏极施加的电压降低了沟道中电子或空穴的能量势垒，并且导致较高的关断电流。
为了控制短沟道效应，人们不得不向沟道中掺杂更多的磷、硼等杂质元素，但此举易导致器件沟道中载流子迁移率下降；而且用来向沟道中掺杂杂质的分布也存在很难控制陡度的问题，容易造成严重的短沟道效应；栅极氧化物介质的厚度方面也将出现发展瓶颈问题，栅极氧化物厚度减薄的速度已经很难再跟上栅极宽度缩小的步伐，栅介质漏电越来越大；关键尺寸不断缩小，易于导致源漏区电阻的不断增大和器件的功耗越来越大。
应变硅技术可以有效地控制短沟道效应，已有使用应变硅作为衬底的MOS晶体管，其利用硅锗的晶格常数与单晶硅不同的特性，使硅锗外延层产生结构上应变而形成应变硅。由于硅锗层的晶格常数比硅大，这使得沟道区中产生机械应力，而造成载流子移动性改变。在FET中，拉应力能够提高电子迁移率，降低空穴迁移率，可以有利地提高NMOS的性能；而压应力可以提高空穴迁移率，降低电子迁移率，可以有利地提高PMOS的性能。
但是，传统的硅锗应变硅技术也开始面临瓶颈，很难再为沟道提供更强的应变，无法有效提升半导体器件的工作性能。
发明内容
为了解决上述问题，本发明提供了一种半导体结构及其制造方法，利于向沟道提供良好的应力效果，以及利于增强源/漏区的陡直性以此抑制短沟道效应。
根据本发明的一个方面，提供了一种半导体结构的制造方法，该制造方法包括以下步骤：
a)提供衬底，在该衬底之上形成栅堆叠以及围绕该栅堆叠的第一侧墙；
b)去除位于所述栅堆叠两侧的部分所述衬底，形成器件堆叠；
c)在所述器件堆叠的侧壁上形成第二侧墙；
d)以带有第二侧墙的器件堆叠为掩模刻蚀位于所述器件堆叠两侧的衬底，形成位于器件堆叠两侧的凹槽以及在所述器件堆叠下方的支撑结构，其中通过控制刻蚀使得所述凹槽的侧壁截面为∑形，该∑形的顶点凸出至器件堆叠正下方；
e)形成填充所述凹槽的第一半导体层；
f)去除位于所述器件堆叠两侧的部分所述第一半导体层，保留一定厚度的第一半导体层；
g)在所述器件堆叠的宽度方向上的部分区域中，去除位于所述器件堆叠两侧的所述第一半导体层，以暴露所述衬底；
h)在所述器件堆叠的宽度方向上的所述部分区域中，在第二侧墙以及器件堆叠的两侧边缘下方形成连接衬底的隔离结构；
i)去除剩余的所述第一半导体层，在所述支撑结构和所述隔离结构之间形成空腔；
j)去除第二侧墙，并在所述器件堆叠的两侧形成源/漏区。
根据本发明的另一个方面，还提供了一种半导体结构，包括衬底、支撑结构、基底区、栅堆叠、侧墙以及源/漏区，其中：
所述栅堆叠位于所述基底区之上，所述基底区由支撑结构支撑于所述衬底之上；
所述支撑结构的侧壁截面为∑形；
在所述基底区两侧边缘下方存在隔离结构，其中，部分所述隔离结构与所述衬底相连接；
在所述隔离结构和所述支撑结构之间存在空腔；以及
至少在所述基底区和隔离结构的两侧存在源/漏区。
与现有技术相比，采用本发明提供的技术方案具有如下优点：由于沟道下方存在空腔，所以位于沟道两侧的应力材料层的应力可以更为集中地作用于沟道，从而有效地提升了应力对沟道载流子迁移率的影响，增强对沟道性能的控制作用；此外，沟道下方空腔的存在还有利于增强源/漏区的陡直性，从而抑制短沟道效应，提高半导体器件的性能。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显。
图1为根据本发明的半导体结构制造方法的流程图；
图2为衬底的剖面示意图；
图3为形成栅堆叠后的剖面示意图；
图4为形成器件堆叠后的剖面示意图；
图5为在器件堆叠的侧面形成刻蚀停止层以及第二侧墙后的剖面示意图；
图6为在器件堆叠的两侧形成凹槽后的剖面示意图；
图7为继续刻蚀形成侧壁为顶点凸出至器件堆叠正下方的Sigma形凹槽后的剖面示意图；
图8为填充凹槽形成半导体层后的剖面示意图；
图9为刻蚀部分半导体层后的剖面示意图；
图10为覆盖光刻掩模后的俯视示意图；
图11为刻蚀半导体层以暴露部分衬底并去除光刻掩模后的俯视示意图；
图11a和图11b分别为图11所示结构沿剖线AA’和沿剖线BB’的剖视示意图；
图12为对半导体层进行横向选择性腐蚀后的俯视示意图；
图12a和图12b分别为图12所示结构沿剖线AA’和沿剖线BB’的剖视示意图；
图13为形成隔离结构后的俯视示意图；
图13a和图13b分别为图13所示结构沿剖线AA’和沿剖线BB’的剖视示意图；
图14为去除半导体层在所述栅堆叠下方形成空腔后的俯视示意图；
图14a和图14b分别为图14所示结构沿剖线AA’和沿剖线BB’的剖视示意图；
图15为在栅堆叠的两侧填充应力材料后的俯视示意图；以及
图15a和图15b分别为图15所示结构沿剖线AA’和沿剖线BB’的剖视示意图。
具体实施方式
下面详细描述本发明的实施例。
所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。另外，以下描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
根据本发明的一个方面，提供了一种半导体结构，请参考图15、图15a和图15b，其中，图15为该半导体结构的俯视示意图，图15a和图15b分别为图15的沿剖线AA’和沿剖线BB’的剖视示意图。如图所示，所述半导体结构包括衬底130、支撑结构131、基底区100、栅堆叠、侧墙240以及源/漏区113，其中，所述栅堆叠位于所述基底区100之上，所述基底区100由支撑结构131支撑于所述衬底130之上；所述支撑结构131的侧壁截面为Sigma(∑)形状；在所述基底区100两侧边缘下方存在隔离结构123，其中，部分所述隔离结构123与所述衬底130相连接；在所述隔离结构123和所述支撑结构131之间存在空腔112；以及至少在所述基底区100和隔离结构123的两侧存在源/漏区113。
具体地，在本实施例中，所述衬底130的材料为单晶Si，在其他实施例中，所述衬底130的材料还可以是其他单晶半导体材料。所述衬底130的厚度范围为0.1nm-2mm。在本实施例中，衬底130的晶向为<100>。
基底区100由支撑结构131支撑于衬底130上方。半导体结构的沟道形成于所述基底区100中。在本实施例中，所述基底区100的材料为单晶硅，在其他实施例中，所述基底区100的材料还可以是其他合适半导体材料。所述基底区100的厚度范围为10nm-30nm。从图15a和图15b可以看出，基底区100和支撑结构131突出于所述衬底130上并与衬底130是一体的，是通过刻蚀所述衬底130形成的。
部分隔离结构123与所述衬底130连接，即，存在部分所述隔离结构123和所述衬底130之间具有一定的距离，并非直接接触。由于支撑结构131的侧壁截面为Sigma(∑)形状，隔离结构123与位于基底区100和衬底130之间的支撑结构131围成空腔112。在本实施例中，所述隔离结构123的材料与所述衬底130和所述基底区100的材料相同，为单晶Si，在其他实施例中，所述隔离结构123的材料还可以是其他合适半导体材料。
所述栅堆叠包括栅介质层102、栅极200、以及帽层220。其中，所述栅介质层102位于基底区100之上，所述栅极200位于所述栅介质层102之上，所述帽层220位于所述栅极200的上方，用以保护栅极200在后续的步骤中不受到破坏。所述栅极200的材料可以选用Poly-Si、Ti、Co、Ni、Al、W、合金、金属硅化物及其组合。所述栅介质层102其可以是热氧化层，包括氧化硅、氮氧化硅，也可为高K介质，例如HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合，栅介质层102的厚度可以为2nm-10nm，例如5nm或8nm。所述帽层220可以选用硅的氮化物，厚度范围为10nm-40nm，例如10nm或20nm。侧墙240（文中也称为“第一侧墙”）环绕在所述栅介质层102、栅极200和帽层220的侧壁上。第一侧墙240的材料包括氮化硅、氧化硅、氮氧化硅、碳化硅中的一种及其组合，和/或其他合适的材料形成。第一侧墙240可以是单层结构，也可以具有多层结构。所述第一侧墙240的厚度范围为10nm-100nm，如30nm、50nm或80nm。
源/漏区113位于带有侧墙240的栅堆叠、基底区100和隔离结构123的两侧。源/漏区113的上表面优选高于所述栅堆叠的底部或者与所述栅堆叠的底部齐平。其中，对于PFET器件，所述源/漏区113的材料为掺杂硼的Si1-XGeX，X的取值范围为0.1～0.7，如0.2、0.3、0.4、0.5或0.6；对于NFET器件，所述源/漏区113的材料为掺杂磷或砷的Si:C，C的原子数百分比的取值范围为0.2%～2%，如0.5%、1%或1.5%。应力材料硅锗或硅碳的存在利于进一步调节沟道区内的应力，以提高沟道区内载流子的迁移率。此外，由于应力材料硅锗或硅碳的存在，所以，对于PFET器件来说，使其具有N型超陡后退阱结构，对于NFET器件来说，使其具有P型超陡后退阱结构。
优选地，本发明所提供的半导体结构还包括源/漏延伸区150，位于所述基底区100中靠近所述源/漏区的部分。
本发明提供的半导体结构具有以下优点：由于沟道下方存在空腔，所以位于沟道两侧的硅锗或硅碳的应力可以更为集中地作用于沟道，从而有效地提升了应力对沟道载流子迁移率的影响，增强对沟道性能的控制作用；此外，沟道下方空腔的存在还有利于增强源/漏区的陡直性，从而抑制短沟道效应，提高半导体器件的性能。
根据本发明的另一个方面，还提供了一种半导体结构的制造方法。下面，将结合图2至图15b通过本发明的一个实施例对图1形成半导体结构的方法进行具体描述。如图1所示，本发明所提供的制造方法包括以下步骤：
在步骤S101中，提供衬底130，在该衬底130上形成栅堆叠以及围绕该栅堆叠的第一侧墙240。
具体地，如图2所示，首先，提供衬底130，在本实施例中，所述衬底130的材料为单晶Si。在其他实施例中，所述衬底130的材料还可以是其他单晶半导体材料。在本实施例中，衬底130的晶向为<100>。如下文所述，这将便于对其进行各向异性刻蚀。所述衬底130的厚度范围为0.1nm-2mm。典型地，在所述衬底130中形成隔离区，例如浅沟槽隔离(STI)结构120，以便电隔离连续的半导体器件。
接着，如图3所示，在所述衬底130之上形成由栅介质层102、栅极200以及帽层220所构成的栅堆叠。其中，所述栅介质层102位于衬底130上，所述栅极200位于所述栅介质层102之上，所述帽层220位于所述栅极200的上方，用以保护栅极200在后续的步骤中不受到破坏。其中，所述栅极200的材料可以选用Poly-Si、Ti、Co、Ni、Al、W、合金、金属硅化物及其组合。所述栅介质层102其可以是热氧化层，包括氧化硅、氮氧化硅，也可为高K介质，例如HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合，栅介质层102的厚度可以为2nm-10nm，例如5nm或8nm。所述帽层220可以选用硅的氮化物，厚度范围为10nm-40nm，例如10nm或20nm。形成栅堆叠后，对位于栅堆叠两侧的所述衬底130的表面进行轻掺杂，用以形成源/漏延伸区150。对于PFET器件，向所述衬底130中掺杂P型杂质，例如硼和铟，对于NFET器件，向所述衬底130中掺杂N型杂质，例如砷和磷。源/漏延伸区150形成后，形成环绕在所述栅介质层102、栅极200和帽层220的侧壁上的第一侧墙240。第一侧墙240的材料包括氮化硅、氧化硅、氮氧化硅、碳化硅中的一种及其组合，和/或其他合适的材料形成。第一侧墙240可以是单层结构，也可以具有多层结构。第一侧墙240的厚度范围为10nm-100nm，如30nm、50nm或80nm。
在步骤S 102中，去除位于所述栅堆叠两侧的部分所述衬底130，形成器件堆叠。
具体地，如图4所示，以带有第一侧墙240的栅堆叠为掩模刻蚀去除所述栅堆叠两侧的部分衬底130，在栅堆叠下方形成基底区100。基底区100和其上的栅堆叠以及第一侧墙240一同构成器件堆叠。在本实施例中，刻蚀深度的范围为10nm-30nm。刻蚀优选为干法刻蚀，所述干法刻蚀的方法包括等离子体刻蚀、离子铣、反溅射、反应离子刻蚀，在本实施例中，采用反应离子刻蚀。
在步骤S 103中，在所述器件堆叠的侧壁上形成第二侧墙260。
具体地，如图5所示，首先，在整个半导体结构上沉积第一绝缘层(未示出)，然后在所述第一绝缘层上沉积第二绝缘层(未示出)。接着，对第二绝缘层和第一绝缘层进行刻蚀，以形成环绕器件堆叠的刻蚀停止层250、以及环绕该刻蚀停止层250的侧墙260(下文中以第二侧墙260表示)。其中，所述第二侧墙260的材料包括氮化硅、氧化硅、氮氧化硅、碳化硅中的一种及其组合，和/或其他合适的材料，其厚度范围在5nm-10nm，所述刻蚀停止层250的材料优选为不同于所述第一侧墙240和第二侧墙260的绝缘材料，例如，所述第一侧墙240和第二侧墙260的材料为氮化硅，而所述刻蚀停止层250的材料为氧化硅。所述刻蚀停止层250的厚度范围为1nm-3nm。
在步骤S104中，以带有第二侧墙260的器件堆叠为掩模刻蚀位于所述器件堆叠两侧的衬底130，形成位于器件堆叠两侧的凹槽160以及在所述器件堆叠下方的支撑结构131，其中通过控制刻蚀使得凹槽160的侧壁截面为∑形，该∑形的顶点凸出至器件堆叠正下方。
具体地，首先，如图6所示，以带有第二侧墙260的器件堆叠为掩模，利用各向异性的方式对位于所述器件堆叠两侧的部分所述衬底130进行刻蚀，形成位于器件堆叠两侧的凹槽160，以及在基底区100下方的支撑结构131。在本实施例中，刻蚀方式优选为干法刻蚀RIE，通过调整和控制RIE设备的气体流量、组分、功耗等，可以获得具有近乎陡直侧壁的凹槽160和支撑结构131。
接着，如图7所示，利用对晶向具有选择性的各向异性湿法刻蚀，继续对凹槽160的底面以及凹槽160和支撑结构131的侧壁进行刻蚀，使得凹槽160的侧壁截面为∑形，该∑形的顶点凸出至器件堆叠正下方。在本实施例中，所述衬底130的晶向为<100>，湿法刻蚀的腐蚀溶液可以是氢氧化钾（KOH）、四甲基氢氧化铵（TMAH）或乙二胺-邻苯二酚（EDP）等，或其组合，腐蚀液的浓度为5~40%质量百分比，反应温度为40℃~90℃。由于KOH、TMAH等腐蚀液对单晶Si腐蚀具有各向异性，对{111}晶面的腐蚀速率与其他晶面的腐蚀速率之比约为1:100，因此对{111}晶面基本不腐蚀。如图7所示，所述凹槽160的侧壁皆为腐蚀停止面，晶面为{111}。因此，利用各向异性腐蚀，使得凹槽的侧壁截面为∑形，该∑形的顶点凸出至器件堆叠正下方，相应地，所述支撑结构131的侧壁截面为内凹的Sigma形。另外，由于凹槽的底面晶向为<100>，湿法刻蚀会使得凹槽160变深。
在步骤S105中，形成填充所述凹槽的第一半导体层110。
具体地，如图8所示，通过选择性外延生长的方式对位于带有第二侧墙260的器件堆叠两侧的凹槽进行填充，以形成半导体层110（下文中以第一半导体层110表示）。在本实施例中，第一半导体层110的材料为SiGe，其中，Ge元素比例在10%-20%之间。需要说明的是，第一半导体层110的上表面不低于刻蚀停止层250的下表面。另外，如图8所示，由于凹槽160的侧壁截面为∑形，该∑形的顶点凸出至器件堆叠正下方，选择性外延生长的第一半导体层110凸出至器件堆叠正下方。
在步骤S106中，去除位于所述器件堆叠两侧的部分所述第一半导体层110，保留一定厚度的第一半导体层110。
具体地，如图9所示，以带有第二侧墙260的器件堆叠为掩模，采用例如干法刻蚀等方式对位于所述第二侧墙260两侧的第一半导体层110进行刻蚀。在刻蚀过程中，并不完全去除所述第一半导体层110，而是在所述第二侧墙260的两侧仍保留了一定厚度的第一半导体层110。另外，由于所选用的刻蚀基本是各向异性的（基本只在垂直方向刻蚀），第一半导体层110凸出至器件堆叠正下方的部分得以保留。
在步骤S107中，在所述器件堆叠的宽度方向上的部分区域中，去除位于所述器件堆叠两侧的所述第一半导体层110，以暴露所述衬底130。上述的宽度，是以将要形成半导体器件的沟道为基准进行定义的，沟道中电流方向为长度方向，与之垂直的方向为宽度方向。即：图10中左右方向为长度方向，纸面上与之垂直的方向为宽度方向。
具体地，在本实施例中，如图10所示，在半导体结构上形成光刻掩模300，覆盖中间部分而露出半导体结构宽度方向上的末端区域，使得在后续步骤中，位于所述光刻掩模300下的第一半导体层110不被刻蚀掉。所述光刻掩模300的材料可以是光刻胶、有机聚合物、氧化硅、氮化硅、硼硅玻璃、硼磷硅玻璃及其组合。其中，形成光刻掩模300的方法为本领域技术人员所熟悉的工艺。为了简明起见，在此不再赘述。光刻掩模300的作用是对在半导体结构的宽度方向上位于中间部分的，栅堆叠两侧的部分第一半导体层110进行保护。即，在后续步骤中刻蚀光刻掩模300未覆盖的第一半导体层110之后，使在半导体结构的宽度方向上位于中间部分的栅堆叠两侧还存在部分第一半导体层110。如下面将说明的，本发明中的光刻掩模300的位置不仅限于图10中所示的位置，凡是可以在半导体结构宽度方向上的部分区域中覆盖位于所述器件堆叠两侧的所述第一半导体层110的光刻掩模300均适用于本发明所提供的制造方法，在此不再一一列举说明。
接着，以光刻掩模300和带有第二侧墙260的器件堆叠为掩模，以及以所述衬底130为刻蚀停止层，对在所述器件堆叠的宽度方向上的两个末端区域中(在其他实施例中，为在所述器件堆叠的宽度方向上未被光刻掩模300所覆盖的区域中)，位于栅堆叠和第二侧墙260以外的第一半导体层110进行刻蚀，直至暴露衬底130。然后，去除所述光刻掩模300。请参考图11、图11a和图11b，其中，图11为刻蚀第一半导体层110以暴露部分衬底并去除光刻掩模300后的俯视示意图，图11a和图11b分别为图11的沿剖线AA’和沿剖线BB’的剖视示意图。如图11a所示，在半导体结构的宽度方向上的中间部分，位于第二侧墙260两侧的、且被光刻掩模300所覆盖的第一半导体层110得以保留，而在半导体结构的宽度方向上的两个末端区域中，位于第二侧墙260两侧的、且未被光刻掩模300所覆盖的第一半导体层110被去除，并暴露出位于其下方的衬底130，如图11b所示。由于所选用的刻蚀基本是各向异性的（基本只在垂直方向刻蚀），第一半导体层110凸出至器件堆叠正下方的部分得以保留。
在步骤S108中，在所述器件堆叠的宽度方向上的所述部分区域中，在第二侧墙260以及器件堆叠的两侧边缘下方形成连接衬底的隔离结构123。
具体地，请参考图12、图12a和图12b所示，其中，图12为对第一半导体层110进行横向选择性腐蚀后的俯视示意图，图12a和图12b分别为图12的沿剖线AA’和沿剖线BB’的剖视示意图。如图所示，对位于栅堆叠和第二侧墙260下方的第一半导体层110进行回刻蚀，通过控制刻蚀时间使横向腐蚀深度略大于第二侧墙260和刻蚀停止层250的厚度之和。
接着，请参考图13、图13a和图13b所示，其中，图13为形成隔离结构后的俯视示意图，图13a和图13b分别为图13的沿剖线AA’和沿剖线BB’的剖视示意图。如图所示，利用例如外延生长的方法在暴露的衬底130的上表面以及的第一半导体层110的上表面和侧壁上形成第二半导体层(未示出)，并通过各向异性的刻蚀方式（例如RIE，基本上仅在垂直方向上刻蚀）去除位于暴露的衬底130的上表面以及位于第一半导体层110上表面上第二半导体层，而保留带有第二侧墙260的器件堆叠下方（主要在第二侧墙260下方）的第二半导体层，以形成隔离结构123。在横向上隔离结构123大致位于第二侧墙260以及器件堆叠的两侧边缘下方。在本实施例中，所述隔离结构123的材料为单晶硅，在其他实施例中，所述隔离结构123的材料还可以是其他不同于所述第一半导体层110的半导体材料。如图13a所示，由于在半导体结构的宽度方向上的中间部分，所述第一半导体层110在所述光刻掩模300(请参考图10)的保护下没有刻蚀完全，所以，在先前被所述光刻掩模300所覆盖的第一半导体层110的侧壁上形成隔离结构123的时候，该隔离结构123是形成在所述第一半导体层110之上的，即，所述隔离结构123与衬底130之间存在第一半导体层110；而如图13b所示，在没有所述光刻掩模300保护的在半导体结构的宽度方向上的两个末端区域中，刻蚀停止在所述衬底130的表面，所以在形成所述隔离结构123时，其下方没有第一半导体层110，即，所述隔离结构123直接形成在所述衬底130之上，与所述衬底130相连接。尽管本实施例中以在半导体结构的宽度方向上的两个末端区域形成隔离结构123为例进行了说明，但是本领域的技术人员应该可以理解，所述隔离结构123的具体位置不限于此。例如，本领域技术人员可以理解，只要是与衬底相连接、且后续可以达到形成空腔的目的，隔离结构123可以位于半导体结构的宽度方向上的任何位置，为简明起见，在此不再赘述。如图所示，隔离结构123和支撑结构131之间存在未被刻蚀掉的、第一半导体层110凸出至器件堆叠正下方的部分。
在步骤S109中，去除剩余的所述第一半导体层110，在所述支撑结构131和所述隔离结构123之间形成空腔112。
具体地，如图14、图14a和图14b，其中，图14为去除第一半导体层110在所述栅堆叠下方形成空腔112后的俯视示意图，图14a和图14b分别为图14的沿剖线AA’和沿剖线BB’的剖视示意图。如图所示，利用湿法刻蚀的方式，选择性去除剩余的所述第一半导体层110，在所述栅堆叠的下方形成在所述支撑结构131和所述隔离结构123之间的空腔112，该空腔112中原来填充了第一半导体层110凸出至器件堆叠正下方的部分。由于所述第一半导体层110的材料不同于衬底130、支撑结构131、基底区100和隔离结构123的材料，所以通过选择相应的腐蚀溶液，可以仅仅将剩余的第一半导体层110去除。腐蚀溶液首先对位于隔离结构123之外的第一半导体层110进行腐蚀，然后将位于半导体结构的宽度方向上的中间部分的隔离结构123和衬底130之间的第一半导体层110去除，这时，在半导体结构的宽度方向上的中间部分，在所述隔离结构123和衬底130之间形成间隙，腐蚀溶液通过该间隙对位于栅堆叠下方的第一半导体层110继续进行腐蚀，直至将所有第一半导体层110完全被去除，从而在栅堆叠下方的支撑结构131和隔离结构123之间形成空腔112。此时，如图14a所示，对于之前隔离结构123和衬底130之间存在第一半导体层110的区域，在所述第一半导体层110被去除后，所述隔离结构123和衬底130之间形成间隙，而如图14b所示，对于之前隔离结构123和衬底130之间不存在第一半导体层110的区域，所述隔离结构123和衬底130相连接。
在步骤S110中，去除第二侧墙260，并在所述器件堆叠的两侧形成源/漏区。
具体地，请参考图15、图15a和图15b所示，其中，图15为在栅堆叠的两侧填充应力材料后的俯视示意图，图15a和图15b分别为图15的沿剖线AA’和沿剖线BB’的剖视示意图。如图所示，首先，以刻蚀停止层250为刻蚀停止层，利用干法刻蚀的方式去除第二侧墙260；接着，以第一侧墙240为刻蚀停止层，继续利用干法刻蚀的方式去除所述刻蚀停止层250，暴露出器件堆叠；然后，向所述器件堆叠两侧充应力材料，以形成源/漏区113，其中，所述源/漏区113的上表面优选高于所述栅堆叠的底部或者与所述栅堆叠的底部齐平。由于隔离结构123的存在，所以应力材料基本存在于隔离结构123之外，进而保证空腔112不被填充。如图15a所示，在所述隔离结构123没有直接接触衬底130的区域，由于所述隔离结构123和衬底130之间存在一定的间隙，所以会有少量应力材料从该间隙内进入所述空腔112，但该少量应力材料进入缝隙后堆积形成屏障，致使只有该部分应力材料进入了所述空腔112，而大部分应力材料被隔离在外；如图15b所示，在所述隔离结构123和衬底130相连接的区域，所述应力材料完全被所述隔离结构123阻挡在所述空腔112之外。
形成所述源/漏区113的方法优选为外延生长。对于PFET器件，所述源/漏区113的材料为掺杂硼的Si1-XGeX，X的取值范围为0.1～0.7，如0.2、0.3、0.4、0.5或0.6；对于NFET器件，所述源/漏区113的材料为掺杂磷或砷的Si:C，C的原子数百分比的取值范围为0.2%～2%，如0.5%、1%或1.5%。应力材料硅锗或硅碳的存在利于进一步调节沟道区内的应力，以提高沟道区内载流子的迁移率。对于PFET器件来说，填充含掺杂的应力材料后，形成了N型超陡后退阱；对于NFET器件来说，填充含掺杂的应力材料后，形成了P型超陡后退阱。
与现有技术相比，本发明具有以下优点：由于沟道下方存在空腔，所以位于沟道两侧的应力材料层的应力可以更为集中地作用于沟道，从而有效地提升了应力对沟道载流子迁移率的影响，增强对沟道性能的控制作用；此外，沟道下方空腔的存在还有利于增强源/漏区的陡直性，从而抑制短沟道效应，提高半导体器件的性能。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。

Claims (17)

1.一种半导体结构的制造方法，该方法包括以下步骤：
a)提供衬底(130)，在该衬底(130)之上形成栅堆叠以及围绕该栅堆叠的第一侧墙(240)；
b)去除位于所述栅堆叠两侧的部分所述衬底(130)，形成器件堆叠；
c)在所述器件堆叠的侧壁上形成第二侧墙(260)；
d)以带有第二侧墙(260)的器件堆叠为掩模刻蚀位于所述器件堆叠两侧的衬底(130)，形成位于器件堆叠两侧的凹槽(160)以及在所述器件堆叠下方的支撑结构(131)，其中通过控制刻蚀使得所述凹槽(160)的侧壁截面为∑形，该∑形的顶点凸出至器件堆叠正下方；
e)形成填充所述凹槽的第一半导体层(110)；
f)去除位于所述器件堆叠两侧的部分所述第一半导体层(110)，保留一定厚度的第一半导体层(110)；
g)在所述器件堆叠的宽度方向上的部分区域中，去除位于所述器件堆叠两侧的所述第一半导体层(110)，以暴露所述衬底(130)；
h)在所述器件堆叠的宽度方向上的所述部分区域中，在第二侧墙(260)以及器件堆叠的两侧边缘下方形成连接衬底的隔离结构(123)；
i)去除剩余的所述第一半导体层(110)，在所述支撑结构(131)和所述隔离结构(123)之间形成空腔(112)；
j)去除第二侧墙(260)，并在所述器件堆叠的两侧形成源/漏区。
2.根据权利要求1所述的方法，其中所述源/漏区包含应力材料。
3.根据权利要求1所述的制造方法，其中，通过外延生长的方式形成源/漏区。
4.根据权利要求1所述的方法，其中所述器件堆叠的宽度方向上的所述部分区域为所述器件堆叠的宽度方向上的两个末端区域。
5.根据权利要求1所述的制造方法，其中：
所述第一半导体层(110)的材料不同于所述衬底(130)的材料。
6.根据权利要求1所述的制造方法，其中，所述步骤b)包括：
以所述栅堆叠为掩模对所述衬底(130)进行刻蚀，在所述栅堆叠下方形成基底区(100)，该基底区(100)与所述栅堆叠构成器件堆叠。
7.根据权利要求6所述的制造方法，其中，所述步骤d)包括：
刻蚀位于所述器件堆叠两侧的部分所述衬底(130)，在所述器件堆叠两侧形成凹槽(160)；
对所述凹槽(160)的侧壁进行刻蚀，在所述器件堆叠下方形成侧壁截面呈∑形状的支撑结构(131)。
8.根据权利要求7所述的制造方法，其中，所述步骤g)包括：
在所述半导体结构上形成光刻掩模(300)，覆盖所述器件堆叠的宽度方向上的部分区域；
以所述光刻掩模(300)和带有所述第二侧墙(260)的器件堆叠为掩模，刻蚀部分所述第一半导体层(110)；以及
去除所述光刻掩模(300)。
9.根据权利要求8所述的制造方法，其中，所述步骤h)包括：
对位于所述栅堆叠下方的第一半导体层(110)进行回刻蚀；
通过外延生长在暴露的衬底(130)的上表面以及所述第一半导体层(110)的上表面和侧壁上形成第二半导体层；以及
利用各向异性的刻蚀方式去除位于暴露的衬底(130)的上表面以及所述第一半导体层(110)上表面上的第二半导体层，形成隔离结构(123)。
10.根据权利要求1所述的制造方法，其中：
所述源/漏区的上表面高于所述栅堆叠的底部或者与所述栅堆叠的底部齐平。
11.根据权利要求9所述的制造方法，其中所述衬底(130)的材料包括硅，所述第一半导体层的材料包括硅锗，所述第二半导体层的材料包括硅，所述源/漏区的材料包括硅锗或硅碳。
12.一种半导体结构，包括衬底(130)、支撑结构(131)、基底区(100)、栅堆叠、侧墙(240)以及源/漏区，其中，所述栅堆叠位于所述基底区(100)之上，所述基底区(100)由支撑结构(131)支撑于所述衬底(130)之上，其中：
所述支撑结构(131)的侧壁截面为∑形；
在所述基底区(100)两侧边缘下方存在隔离结构(123)，其中，部分所述隔离结构(123)与所述衬底(130)相连接；
在所述隔离结构(123)和所述支撑结构(131)之间存在空腔(112)；以及
至少在所述基底区(100)和隔离结构(123)的两侧存在源/漏区。
13.根据权利要求12所述的半导体结构，其中，进一步包括源/漏延伸区，位于所述基底区中。
14.根据权利要求12所述的半导体结构，其中，所述隔离结构(123)的材料包括硅。
15.根据权利要求12所述的半导体结构，其中，所述隔离结构(123)除了与所述衬底(130)直接接触的部分，其他部分与衬底(130)之间夹有硅锗或硅碳。
16.根据权利要求12所述的半导体结构，其中，所述衬底(130)的材料包括硅。
17.根据权利要求12所述的半导体结构，其中，所述源/漏区的材料包括硅锗或硅碳。
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