CN103700593B - 制备准soi源漏多栅器件的方法 - Google Patents

制备准soi源漏多栅器件的方法 Download PDF

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CN103700593B
CN103700593B CN201310696063.0A CN201310696063A CN103700593B CN 103700593 B CN103700593 B CN 103700593B CN 201310696063 A CN201310696063 A CN 201310696063A CN 103700593 B CN103700593 B CN 103700593B
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source
drain
layer
gate
etching
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CN103700593A (zh
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黄如
樊捷闻
黎明
杨远程
宣浩然
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Peking University
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Priority to PCT/CN2014/074361 priority patent/WO2015089952A1/zh
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Abstract

本发明公开一种制备准SOI源漏多栅器件的方法，属于超大规模集成电路制造技术领域，所述方法依次包括如下步骤：在第一半导体衬底上形成Fin条形状的有源区；形成STI隔离层；淀积栅介质层和栅材料层，形成栅叠层结构；形成源漏延伸区的掺杂结构；形成凹陷源漏结构；形成准SOI源漏隔离层；原位掺杂外延第二半导体材料源漏，并进行退火激活；将假栅去掉，重新进行高k金属栅的淀积；形成接触和金属互联。该方法可有效降低泄漏电流，减小器件的功耗，具有较小的热预算，且工艺简单，能与传统CMOS工艺兼容，还能应用到除硅以外的半导体材料，有利于应有到大规模集成电路制造中。

Description

制备准SOI源漏多栅器件的方法
技术领域
本发明涉及一种制备准SOI源漏多栅器件的方法，属于超大规模集成电路制造技术领域。
背景技术
当今半导体制造业在摩尔定律的指导下迅速发展，在不断提高集成电路的性能和集成密度的同时，需要尽可能的减小功耗。制备高性能，低功耗的超短沟器件是未来半导体制造业的焦点。当进入到22纳米技术节点以后，为了克服上述问题，多栅结构器件由于其优秀的短沟道控制能力和弹道输运能力，成为了当今半导体器件中的热点。Intel的22纳米产品中已经应用了这一结构，并显示出高性能和低功耗的优点。另一方面，准SOI源漏器件通过在源漏两端增加绝缘隔离层，使得泄漏电流进一步减小，特别是针对超低功耗器件领域，拥有巨大的潜力。
但是，目前现有的准SOI源漏多栅结构器件制备工艺，一般通过热氧化形成准SOI隔离层，具有较高的热预算，不能很好的应用到大规模集成制造中；而且现有工艺限制在硅衬底材料上，不能很好地拓展到锗或三五族材料等高迁移率半导体衬底上。
本发明提供的制备准SOI源漏多栅器件的方法同时解决了上述两个问题，制备工艺具有更好的兼容性和扩展性，更进一步地，其具有多栅结构栅控性能好的特点，相比现有的平面准SOI源漏器件制备工艺，具有更小的泄漏电流和更低的功耗。
发明内容
为了解决上述问题，本发明提供一种制备准SOI源漏多栅器件的方法，所述方法的制备工艺具有更好的兼容性和扩展性，更进一步地，具有多栅结构栅控性能好的特点，相比现有的平面准SOI源漏器件制备工艺，具有更小的泄漏电流和更低的功耗。
所述制备准SOI源漏多栅器件的方法依次包括如下步骤：
1)通过光刻和刻蚀，以第一半导体材料为衬底，在其上形成Fin条形状的有源区；
2)进行STI形成STI隔离层，所述STI的回填材料为绝缘介质，通过化学气相淀积技术（CVD）、化学机械抛光技术（CMP）和刻蚀形成STI隔离层，第一半导体衬底的Fin条的高度为H1；
3)在衬底上依次淀积栅介质层和栅材料层，采用前栅工艺或者后栅工艺通过光刻和刻蚀形成栅叠层结构，其中前栅工艺形成的栅叠层结构为真栅，后栅工艺形成的栅叠层结构为假栅；
4)通过注入技术形成源漏延伸区的掺杂结构，并在栅叠层结构两侧形成宽度为L1的第一层侧墙；
5)形成凹陷源漏结构，所述凹陷源漏结构为U型凹陷源漏结构、Σ型凹陷源漏结构或者S型凹陷源漏结构；
6)通过CVD淀积准SOI源漏隔离层，再通过CMP平坦化所述准SOI源漏隔离层，停止在栅材料层上，然后通过刻蚀回刻或者各向同性湿法腐蚀回漂所述准SOI源漏隔离层，在凹陷源漏结构的上面形成厚度为H5的准SOI源漏隔离层，其中所述准SOI源漏隔离层的材料与第一层侧墙的材料不同；
7)原位掺杂外延第二半导体材料源漏，并进行退火激活；
8)将作为假栅牺牲层的栅叠层结构去掉，重新进行高k金属栅的淀积，包括：首先通过各向同性湿法腐蚀去掉假栅牺牲层，其次通过原子层淀积（ALD）重新形成具有高介电常数的栅介质层，然后通过ALD或者物理气相淀积物理气相淀积（PVD）重新形成栅材料层，最后通过CMP平坦化栅材料层；
9)形成接触和金属互联。
上述制备准SOI源漏多栅器件的方法中，所述第一半导体衬底为四族半导体材料或者三五族半导体材料，其中：四族半导体材料为硅、锗或锗硅，三五族半导体材料为砷化镓或砷化铟。
优选地，以上制备准SOI源漏多栅器件的方法中所述的刻蚀为各向异性干法刻蚀方法，可以采用光刻胶或者硬掩膜为阻挡层进行刻蚀，其中的硬掩膜可为氧化硅或者氮化硅。
在所述步骤2）进行STI隔离之后，可选择保留第一半导体衬底Fin条顶部的硬掩膜则最终形成双栅结构器件，或者去除第一半导体材料Fin条顶部的硬掩膜则最终形成三栅结构器件。
所述步骤3）进一步包括如下步骤：首先热氧化在衬底上形成一层氧化物作为栅介质层，其次采用低压化学气相淀积（LPCVD）淀积并CMP平坦化形成栅材料层，然后采用LPCVD淀积形成栅硬掩膜层，最后光刻和刻蚀栅介质层、栅材料层和栅硬掩膜层形成栅叠层结构；其中：栅介质可以是通过氧化和后续退火形成的第一半导体衬底的氧化物和氮氧化合物，或者是通过ALD形成的具有高介电常数的介质材料氧化铝、氧化铪或氧化钇，还可以是第一半导体衬底的氧化物和氮氧化合物及高介电常数介质材料的组合物；栅材料为通过CVD形成的多晶硅，或者是通过ALD或PVD形成的导电材料，具体为氮化钛、氮化钽、钛或铝。
所述制备准SOI源漏多栅器件的方法中的步骤4）中，可选地，形成源漏延伸区的掺杂结构采用的注入技术为传统束线离子注入技术、等离子体掺杂技术或者单分子层淀积掺杂技术；所述栅叠层两侧的第一层侧墙的材料为氮化硅，通过CVD和各向异性干法刻蚀而形成。
所述制备准SOI源漏多栅器件的方法中的步骤5）中，进一步地，所述步骤5）中的U型凹陷源漏结构是通过刻蚀，使得第一半导体衬底的Fin条被完全刻蚀，刻蚀深度为H1，Fin条底部以下的刻蚀深度为H2而形成；所述Σ型凹陷源漏结构是在所述U型凹陷源漏结构的基础上继续使用TMAH腐蚀液采用各向异性湿法腐蚀第一半导体衬底，腐蚀深度为H3，当H3大于H2时形成Σ型凹陷源漏结构；所述S型凹陷源漏结构是在所述U型凹陷源漏结构的基础上，首先通过CVD和各向异性干法刻蚀形成宽度为L2的第二层侧墙，第二层侧墙的材料与第一层侧墙的材料不同且对第一半导体材料具有1:5以上的各向异性干法刻蚀选择比，其次通过各向同性干法刻蚀第一半导体衬底，纵向刻蚀深度为H4，横向刻蚀宽度为L3，当L3大于L2时形成S型凹陷源漏结构，同时通过各向同性湿法腐蚀去掉第二层侧墙。
所述U型凹陷源漏结构的刻蚀深度为H2，Σ型凹陷源漏结构的刻蚀深度为H2+H3，S型凹陷源漏结构的刻蚀深度为H2+H4。在制备准SOI源漏多栅器件的方法中，所述U型凹陷源漏结构的刻蚀深度H5均小于U型凹陷源漏结构的刻蚀深度、Σ型凹陷源漏结构的刻蚀深度或者S型凹陷源漏结构的刻蚀深度，使得凹陷源漏延伸区预留有窗口，后续能够进行外延工艺形成源漏接触。
所述制备准SOI源漏多栅器件的方法中的步骤6）中，准SOI源漏隔离层的材料与第一层侧墙的材料不同，可选氧化硅或具有更好导热性的氧化铝。
所述制备准SOI源漏多栅器件的方法中，可选地，所述步骤7）中的原位掺杂外延第二半导体的材料与第一半导体的材料相同或者不同，原位掺杂外延第二半导体材料形成CMOS源漏，可对PMOS进行P型掺杂或者对NMOS进行N型掺杂；所述步骤7）中采用的退火激活方式选自下列方式中的一种或多种：炉退火、快速热退火、闪耀退火和激光退火。
以硅衬底作为第一半导体衬底为例，本发明制备准SOI源漏硅多栅器件的技术方案包括如下步骤：
I.通过光刻和刻蚀，在硅衬底上形成Fin条形状的有源区
a)通过热氧化在硅衬底上形成第一层氧化硅，作为氮化硅的缓冲层；
b)在第一层氧化硅上LPCVD第一层氮化硅，作为CMP停止层；
c)光刻和各向异性干法刻蚀第一层氮化硅和第一层氧化硅，形成硅Fin条的硬掩膜层；
d)各向异性干法刻蚀硅衬底，形成硅Fin条。
II.进行STI形成STI隔离层
a)通过高密度等离子体化学气相淀积（HDPCVD）淀积第二层氧化硅，作为STI槽回填材料；
b)通过CMP平坦化第二层氧化硅，停止在第一层氮化硅上；
c)各向异性干法刻蚀第二层氧化硅，刻蚀后硅衬底Fin条的高度为H1；
d)各向同性湿法腐蚀去掉第一层氮化硅和第一层氧化硅。
III.在硅衬底上淀积栅介质层和栅材料层，通过后栅工艺形成作为假栅牺牲层的栅叠层结构
a)通过热氧化在硅衬底上形成第三层氧化硅，作为假栅介质层；
b)通过LPCVD淀积第一层多晶硅，作为假栅材料层；
c)CMP平坦化第一层多晶硅；
d)通过LPCVD淀积第二层氮化硅，作为栅硬掩膜层；
e)通过光刻和各向异性干法刻蚀第二层氮化硅、第一层多晶硅和第三层氧化硅，形成栅叠层结构。
IV.通过注入技术形成源漏延伸区的掺杂结构，并在栅叠层两侧形成宽度为L1的第一层侧墙
a)通过注入源漏延伸区形成掺杂结构；
b)通过LPCVD淀积第三层氮化硅，淀积厚度为L1，作为第一层侧墙材料；
c)通过各向异性干法刻蚀第三层氮化硅，利用过刻蚀工艺把硅衬底Fin条两侧的氮化硅去除，形成栅叠层结构两侧的第一层侧墙，第一层侧墙的宽度为L1。
V.形成凹陷源漏结构，凹陷源漏结构可为U型凹陷源漏结构、Σ型凹陷源漏结构或者S型凹陷源漏结构，通过控制凹陷源漏结构的刻蚀深度使得凹陷源漏延伸区预留有窗口
a)通过各向异性干法刻蚀硅衬底，硅衬底的Fin条被完全刻蚀，刻蚀深度为H1，Fin条底部以下的刻蚀深度为H2，形成U型凹陷源漏结构，U型凹陷源漏结构的刻蚀深度为H2；
b)在U型凹陷源漏结构的基础上，通过湿法腐蚀，腐蚀深度为H3，当H3大于H2时形成Σ型凹陷源漏结构，Σ型凹陷源漏结构的刻蚀深度为H2与H3之和；
c)或者在U型凹陷源漏结构的基础上，首先通过LPCVD淀积第四层氧化硅，淀积厚度为L2，作为第二层侧墙的材料；其次通过各向异性干法刻蚀第四层氧化硅，形成宽度为L2的第二层侧墙，第二层侧墙的目的是保护源漏延伸区不被后续各向同性干法刻蚀工艺去除；然后通过各向同性干法刻蚀硅衬底，纵向刻蚀深度为H4，横向刻蚀宽度为L3，当L3大于L2时形成S型凹陷源漏结构，同时通过各向同性湿法腐蚀去除第四层氧化硅（第二层侧墙）；S型凹陷源漏结构的刻蚀深度为H2与H4之和。
VI.在凹陷源漏结构的上面形成准SOI源漏隔离层
a)通过LPCVD淀积第一层氧化铝，作为准SOI源漏隔离层材料；
b)通过CMP平坦化第一层氧化铝，停止在第二层氮化硅上（栅硬掩膜层）；
c)各向异性干法刻蚀第一层氧化铝，停止在第二层氧化硅（STI氧化硅）上；
d)通过各向同性湿法腐蚀第一层氧化铝，形成厚度为H5的准SOI源漏隔离层，在U型凹陷源漏结构的上面形成的准SOI源漏隔离层满足H5小于H2，在Σ型凹陷源漏结构的上面形成的准SOI源漏隔离层满足H5小于H2与H3之和，在S型凹陷源漏结构的上面形成的准SOI源漏隔离层满足H5小于H2与H4之和。
VII.通过形成凹陷源漏结构时预留的凹陷源漏延伸区的外延窗口，原位掺杂外延P型锗硅源漏，并通过激光退火和快速热退火激活
VIII.去掉作为假栅牺牲层的栅叠层结构，重新进行高k金属栅的淀积
a)通过LPCVD淀积第五层氧化硅，作为第零隔离介质层；
b)通过CMP平坦化第五层氧化硅、第二层氮化硅和第三层氮化硅，停止在第一层多晶硅（假栅材料层）上；
c)通过各向同性湿法腐蚀去除第一层多晶硅（假栅材料层）；
d)通过各向同性湿法腐蚀去除第三层氧化硅（假栅介质层）；
e)通过原位蒸汽氧化形成界面层；
f)通过ALD淀积第一层高介电常数介质（真栅介质层）；
g)通过ALD淀积第一层金属功函数（真栅功函数调节层）；
h)通过PVD淀积第一层金属栅（真栅材料层）；
i)通过CMP平坦化第一层金属栅，停止在第五层氧化硅上。
IX.形成接触和金属互联。
本发明具有以下技术效果：
本发明提供的制备准SOI源漏多栅器件的方法，具有多栅结构栅控性能好的特点，相比现有的平面准SOI源漏器件制备工艺，其具有更小的泄漏电流和更低的功耗。同时，本发明提供的制备工艺克服了现有的准SOI源漏多栅结构器件制备工艺热预算较高的不足和只能采用硅衬底材料的限制，其具有较小的热预算；且制备工艺能与传统CMOS工艺兼容；还能应用到除硅以外的如锗、锗硅和三五族等半导体材料；有利于应有到大规模集成电路制造中。
附图说明
图1～22为本发明制备准SOI源漏硅多栅器件具体实施流程中形成的器件结构示意图，其中：
图1为形成硅Fin条之后的器件结构示意图。
图2为通过STI形成STI隔离层之后的器件结构示意图。
图3为形成带栅硬掩膜的栅叠层结构之后的器件结构示意图。
图4为形成栅叠层结构两侧的第一层侧墙之后的器件结构示意图。
图5为形成U型凹陷源漏结构之后的器件结构示意图。
图6为图5在AA切线方向上的剖面图。
图7为形成Σ型凹陷源漏结构之后的器件结构示意图。
图8为图7在AA切线方向上的剖面图。
图9为形成S型凹陷源漏结构过程中形成第二层侧墙之后的器件结构示意图。
图10为图9在AA切线方向上的剖面图。
图11为形成S型凹陷源漏结构过程中去除第二层侧墙之后的器件结构示意图。
图12为图11在AA切线方向上的剖面图。
图13为在U型凹陷源漏结构上形成准SOI源漏隔离层之后的器件结构示意图。
图14为图13在AA切线方向上的剖面图。
图15为在Σ型凹陷源漏结构上形成准SOI源漏隔离层之后的器件结构示意图。
图16为图15在AA切线方向上的剖面图。
图17为在S型凹陷源漏结构上形成准SOI源漏隔离层之后的器件结构示意图。
图18为图17在AA切线方向上的剖面图。
图19为原位掺杂外延源漏并退火激活后的器件结构示意图。
图20为后栅工艺中去除假栅之后的器件结构示意图。
图21为重新形成高k金属栅之后的器件结构示意图。
图22为形成接触和金属互联之后的器件结构示意图。
在图1～图22中：
1—硅衬底；2—第一层氧化硅（氮化硅的缓冲层）；3—第一层氮化硅（CMP的停止层）；4—硅Fin条；5—第二层氧化硅（STI槽回填材料）；6—第三层氧化硅（假栅栅介质层）；7-第一层多晶硅（假栅栅材料层）；8—第二层氮化硅（栅硬掩膜层）；9—第三层氮化硅（第一层侧墙）；10-U型凹陷源漏结构；11-Σ型凹陷源漏结构；12-第四层氧化硅（第二层侧墙）；13-S型凹陷源漏结构；14-第一层氧化铝（凹陷源漏隔离材料）；15-外延源漏；16-第五层氧化硅（第零隔离介质层）；17-铝。
图23为所用材料的说明。
具体实施方式
下面结合附图，通过具体实施例详细说明本发明，具体给出实现本发明提出的制备准SOI源漏多栅器件的一个工艺方案，但不以任何方式限制本发明的范围。
在硅衬底上通过后栅工艺制备准SOI源漏多栅器件的具体实施步骤如下：
1.通过热氧化在硅衬底1上形成的第一层氧化硅2，作为氮化硅的缓冲层。
2.在第一层氧化硅上通过LPCVD淀积的第一层氮化硅3，作为CMP停止层。
3.光刻和各向异性干法刻蚀的第一层氮化硅3和的第一层氧化硅2，形成硅Fin条硬掩膜层。
4.各向异性干法刻蚀硅衬底形成硅Fin条4，刻蚀后硅Fin条的宽度为10nm，如图1所示。
5.通过HDPCVD淀积的第二层氧化硅5，作为STI槽回填材料。
6.通过CMP平坦化第二层氧化硅5，停止在第一层氮化硅3上。
7.各向异性干法刻蚀的第二层氧化硅5，刻蚀后硅Fin条的高度为H1=30nm。
8.浓磷酸溶液170℃各向同性湿法腐蚀去掉的第一层氮化硅3，氢氟酸溶液各向同性湿法腐蚀去掉的第一层氧化硅2，如图2所示。
9.通过热氧化在硅衬底上形成的第三层氧化硅6，作为假栅介质层。
10.通过LPCVD淀积的第一层多晶硅7，作为假栅材料层。
11.通过CMP平坦化第一层多晶硅7，至厚度为
12.通过LPCVD淀积的第二层氮化硅8，作为栅硬掩膜层。
13.光刻和各向异性干法刻蚀的第二层氮化硅8、的第一层多晶硅6和的第三层氧化硅6，形成栅叠层结构，栅长为30nm，如图3所示。
14.源漏延伸区离子注入，注入As，剂量为1e15cm-2，能量为5keV，角度为10°，分四次注入，形成掺杂。
15.通过LPCVD淀积第三层氮化硅9，作为第一层侧墙材料，淀积厚度为16.各向异性干法刻蚀的第三层氮化硅9，利用过刻蚀把硅Fin条两侧的第三层氮化硅9去除，形成栅叠层结构两侧的第一层侧墙，侧墙宽度为如图4所示。
17.各向异性干法刻蚀硅衬底，总刻蚀深度为硅Fin条被完全刻蚀，刻蚀深度为H1=30nm，硅Fin条底部以下的刻蚀深度为形成U型的凹陷源漏结构10，如图5所示，图6为图5在AA切线方向上的剖面图。
18.各向异性湿法腐蚀硅衬底，腐蚀深度为满足H3>H2，形成Σ型凹陷源漏结构11，如图7所示，图8为图7在AA切线方向上的剖面图。
19.通过LPCVD淀积的第四层氧化硅12，作为第二层侧墙材料。
20.各向异性干法刻蚀的第四层氧化硅12，形成保护源漏延伸区不被后续各向同性干法刻蚀工艺去除的第二层侧墙，侧墙宽度为如图9所示，图10为图9在AA切线方向上的剖面图。
21.各向同性干法刻蚀硅衬底，纵向刻蚀深度为横向刻蚀宽度为满足L2>L1，形成S型凹陷源漏结构13。
22.各向同性湿法腐蚀去除的第四层氧化硅12（第二层侧墙），如图11所示，图12为图11在AA切线方向上的剖面图。
23.通过LPCVD淀积的第一层氧化铝14，作为准SOI源漏隔离层材料。
24.通过CMP平坦化第一层氧化铝14，停止在第二层氮化硅8（栅硬掩膜层）上。
25.各向异性干法刻蚀的第一层氧化铝14，停止在第二层氧化硅5上，也即STI氧化硅上。
26.盐酸各向同性湿法腐蚀的第一层氧化铝14，腐蚀深度应小于H2，形成准SOI源漏隔离层，隔离层厚度为H5，对于U型凹陷源漏结构，应满足H5<H2，如图13所示，图14为图13切线方向上的剖面图；对于Σ型凹陷源漏结构，应满足H5<H2+H3，如图15所示，图16为图15在AA切线方向上的剖面图；对于S型凹陷源漏结构，应满足H5<H2+H4，如图17所示，图18为图17在AA切线方向上的剖面图。
27.通过之前预留的源漏延伸区外延窗口，原位掺杂外延P型锗硅源漏15。
28.通过激光退火，温度为1200℃，时间为1ms。
29.通过快速热退火，起始温度和终止温度为400℃，峰值温度为900℃，上升温度为200℃/s，下降温度为150℃/s，如图19所示。
采用后栅工艺，应去掉之前的假栅，重新进行高k金属栅的淀积，包括：
30.通过LPCVD淀积的第五层氧化硅16，作为第零隔离介质层；
31.通过CMP平坦化第五层氧化硅16、第二层氮化硅8和第三层氮化硅9，停止在第一层多晶硅7（栅材料层）上；
32.采用TMAH溶液通过各向同性湿法腐蚀去除的第一层多晶硅7，也即假栅材料层；
33.采用氢氟酸溶液通过各向同性湿法腐蚀去除的第三层氧化硅6，也即假栅介质层，如图20所示；
34.通过原位蒸汽氧化形成的氧化硅界面层；
35.通过ALD淀积第一层高介电常数介质，的氧化铪，也即真栅介质层；
36.通过ALD淀积第一层金属功函数，的氮化钛，也即真栅功函数调节层；
37.通过PVD淀积第一层金属栅，的铝17；也即真栅材料层；
38.通过CMP平坦化第一层金属栅17，停止在第五层氧化硅16上，如图21所示。
39.最后，形成接触和金属互联，如图22所示。
上面描述的实施例并非用于限定本发明，任何本领域的技术人员，在不脱离本发明的精神和范围内，可做各种的更动和润饰，因此本发明的保护范围视权利要求范围所界定。

Claims (10)

1.一种制备准SOI源漏多栅器件的方法，其特征在于，依次包括如下步骤：
(1)通过光刻和刻蚀，以第一半导体材料为衬底，在其上形成Fin条形状的有源区；
(2)通过进行STI形成STI隔离层，所述STI的回填材料为绝缘介质，通过化学气相淀积技术、化学机械抛光技术和刻蚀形成STI隔离层，衬底的Fin条的高度为H1；
(3)在衬底上依次淀积栅介质层和栅材料层，采用前栅工艺或者后栅工艺通过光刻和刻蚀形成栅叠层结构，其中前栅工艺形成的栅叠层结构为真栅，后栅工艺形成的栅叠层结构为假栅；
(4)通过注入技术形成源漏延伸区的掺杂结构，并在栅叠层结构两侧形成宽度为L1的第一层侧墙；
(5)形成U型、Σ型或S型凹陷源漏结构；
(6)通过化学气相淀积技术淀积准SOI源漏隔离层，再通过化学机械抛光技术平坦化所述准SOI源漏隔离层，停止在栅材料层上，然后通过刻蚀回刻或者各向同性湿法腐蚀回漂所述准SOI源漏隔离层，在凹陷源漏结构的上面形成厚度为H5的准SOI源漏隔离层，其中所述准SOI源漏隔离层的材料与第一层侧墙的材料不同；
(7)原位掺杂外延第二半导体材料，形成源漏，进行退火激活；
(8)若步骤(3)采用前栅工艺，直接进入步骤(9)；若采用后栅工艺，则将作为假栅牺牲层的栅叠层结构去掉，重新进行高k金属栅的淀积，具体为首先通过各向同性湿法腐蚀去掉假栅牺牲层，其次通过原子层淀积重新形成具有高介电常数的栅介质层，然后通过原子层淀积或者物理气相淀积重新形成栅材料层，最后通过化学机械抛光技术平坦化栅材料层；
(9)形成接触和金属互联。
2.如权利要求1所述制备准SOI源漏多栅器件的方法，其特征在于，所述第一半导体材料为四族半导体材料或者三五族半导体材料。
3.如权利要求1所述制备准SOI源漏多栅器件的方法，其特征在于，所述刻蚀为各向异性干法刻蚀方法，所述各向异性干法刻蚀以光刻胶或者硬掩膜为阻挡层进行刻蚀，其中的硬掩膜为氧化硅或者氮化硅。
4.如权利要求1所述制备准SOI源漏多栅器件的方法，其特征在于，在所述步骤(2)进行STI隔离之后，保留衬底Fin条顶部的硬掩膜，最终形成双栅结构器件；或者去除衬底Fin条顶部的硬掩膜，最终形成三栅结构器件。
5.如权利要求1所述制备准SOI源漏多栅器件的方法，其特征在于，所述步骤(3)包括如下步骤：首先热氧化在衬底上形成一层氧化物作为栅介质层，其次采用低压化学气相淀积并化学机械抛光技术平坦化形成栅材料层，然后采用低压化学气相淀积形成栅硬掩膜层，最后光刻和刻蚀栅介质层、栅材料层和栅硬掩膜层形成栅叠层结构；其中：栅介质是通过氧化和后续退火形成的衬底材料的氧化物或氮氧化合物，或者是通过原子层淀积形成的高介电常数介质材料，或者是衬底材料的氧化物或氮氧化合物与高介电常数介质材料的组合物；栅材料为通过化学气相淀积技术形成的多晶硅，或者是通过原子层淀积或物理气相淀积形成的导电材料，所述导电材料为氮化钛、氮化钽、钛或铝。
6.如权利要求1所述制备准SOI源漏多栅器件的方法，其特征在于，所述步骤(4)形成源漏延伸区的掺杂结构采用的注入技术为束线离子注入技术、等离子体掺杂技术或者单分子层淀积掺杂技术；所述栅叠层两侧的第一层侧墙的材料为氮化硅，通过化学气相淀积技术和各向异性干法刻蚀而形成。
7.如权利要求1所述制备准SOI源漏多栅器件的方法，其特征在于，所述步骤(5)中的U型凹陷源漏结构是通过刻蚀，使得衬底的Fin条被完全刻蚀，刻蚀深度为H1，Fin条底部以下的刻蚀深度为H2而形成；所述Σ型凹陷源漏结构是在所述U型凹陷源漏结构的基础上继续使用TMAH腐蚀液采用各向异性湿法腐蚀衬底，腐蚀深度为H3，当H3大于H2时形成；所述S型凹陷源漏结构是在所述U型凹陷源漏结构的基础上，首先通过化学气相淀积技术和各向异性干法刻蚀形成宽度为L2的第二层侧墙，第二层侧墙的材料与第一层侧墙的材料不同且对其第一半导体材料具有1:5以上的各向异性干法刻蚀选择比，其次通过各向同性干法刻蚀衬底，纵向刻蚀深度为H4，横向刻蚀宽度为L3，当L3大于L2时形成，同时通过各向同性湿法腐蚀去掉第二层侧墙。
8.如权利要求1或权利要求7所述制备准SOI源漏多栅器件的方法，其特征在于，所述U型凹陷源漏结构的刻蚀深度为H2，Σ型凹陷源漏结构的刻蚀深度为H2+H3，S型凹陷源漏结构的刻蚀深度为H2+H4，所述U型凹陷源漏结构的刻蚀深度H5小于凹陷源漏结构的刻蚀深度，使得凹陷源漏延伸区预留有窗口。
9.如权利要求1所述制备准SOI源漏多栅器件的方法，其特征在于，所述步骤(6)中准SOI源漏隔离层的材料为氧化硅或氧化铝。
10.如权利要求1所述制备准SOI源漏多栅器件的方法，其特征在于，步骤(7)中所述第二半导体材料与步骤(1)中所述第一半导体材料相同或者不同，原位掺杂外延第二半导体材料形成CMOS源漏，对PMOS进行P型掺杂或者对NMOS进行N型掺杂；所述步骤(7)中采用的退火激活方式选自下列方式中的一种或多种：炉退火、快速热退火、闪耀退火和激光退火。
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