CN102903750B - 一种半导体场效应晶体管结构及其制备方法 - Google Patents
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Abstract
本申请公开了一种半导体场效应晶体管结构及其制备方法，该方法包括：形成具有体接触孔的绝缘体上硅(SOI)结构的半导体衬底；在所述绝缘体上硅(SOI)结构的半导体衬底上形成鳍片；在所述鳍片顶部和侧面形成栅堆叠结构；在所述栅堆叠结构两侧的鳍片中形成源/漏结构；金属化。本发明采用传统的基于准平面的自顶向下工艺实现了与CMOS平面工艺的良好兼容，并且易于集成，有利于抑制短沟道效应，推动MOSFETs尺寸往小尺寸方向发展。
Description
技术领域
本发明属于半导体技术领域，尤其涉及一种鳍型场效应晶体管的制备方法。
背景技术
随着集成电路产业按照Moore定律持续向前发展，CMOS器件的特征尺寸持续缩小，平面体硅CMOS结构器件遇到了严峻的挑战。为了克服这些问题，各种新结构器件应运而生。在众多新结构器件中，鳍型场效应晶体管(FinFET)被认为是最有可能替代平面体硅CMOS器件的新结构器件之一，成为国际研究的热点。
大部分FinFET结构器件主要制备在SOI衬底上，工艺较体硅衬底而言较为简单。但是SOIFinFET存在制备成本高，散热性差，有浮体效应，与CMOS工艺兼容性差等缺点。尤其是浮体效应对器件的性能有较大的影响。浮体效应主要包括：Kink效应、寄生双极晶体管效应、瞬态浮体效应、磁滞效应等。浮体效应会导致器件增益降低，噪声过冲，器件工作不稳定，使源漏击穿电压减小等一系列问题。另外，SOIFinFET器件由于BOX的存在还会降低器件的散热性能，引起自加热效应，使得迁移率、阈值电压、碰撞离化、泄漏电流、亚阈值斜率等受到温度的影响。
为了克服以上问题，推动FinFET结构器件尽快获得应用，需要进一步开展这方面的研究工作。这对于FinFET结构器件的应用以及半导体产业的发展具有重要意义。
发明内容
本发明的第一方面是一种半导体场效应晶体管结构，包括：鳍片，该鳍片位于埋层隔离介质层上，同时鳍片的沟道区域底部通过体接触与衬底相连；隔离介质层，该隔离介质层将鳍片除通过体接触与衬底相连的沟道区域之外的区域与衬底隔离开；体接触，该体接触将至少所述鳍片的所述沟道区域的一部分与衬底形成直接的物理和电学接触；栅电极，栅电极的方向与鳍片的方向垂直，鳍片与栅电极相交的区域形成沟道；栅电极与鳍片之间存在栅介质；源漏区域，位于沟道区域及栅电极的两侧。
本发明的第二方面是一种制备方法，包括：形成具有体接触孔的绝缘体上硅(SOI)结构的半导体衬底；在所述绝缘体上硅(SOI)结构的半导体衬底上形成鳍片；在所述鳍片顶部和侧面形成栅堆叠结构；在所述栅堆叠结构两侧的鳍片中形成源/漏结构；金属化。
为了实现上述目的，本发明的主要步骤包括：形成具有体接触孔的绝缘体上硅(SOI)结构的半导体衬底；在所述绝缘体上硅(SOI)结构的半导体衬底上形成鳍片；在所述鳍片顶部和侧面形成栅堆叠结构；在所述栅堆叠结构两侧的鳍片中形成源/漏结构；金属化。
优选地，形成具有体接触孔的绝缘体上硅(SOI)结构的半导体衬底的步骤包括：在半导体衬底上形成介质层；光刻、刻蚀所述介质层形成介质层岛及体接触孔；在半导体衬底上形成一层非晶硅材料；将非晶硅材料转变为单晶材料并进行化学机械抛光(CMP)形成具有体接触孔的绝缘体上硅(SOI)结构半导体衬底。
优选地，所述介质层包括SiO2、TEOS、LTO或Si3N4，厚度为20-100nm。
优选地，在半导体衬底上形成一层非晶硅材料步骤中，所述非晶硅材料的形成可以采用低压化学气相淀积(LPCVD)、离子束溅射等方法；所述非晶硅材料的厚度为200nm-1000nm。
优选地，所述将非晶硅材料转变为单晶材料并进行化学机械抛光(CMP)形成具有体接触孔的绝缘体上硅(SOI)结构半导体衬底的步骤中，可以采用横向固相外延(LSPE)技术、激光再结晶法、卤素灯或条形加热器再结晶等方法将非晶硅材料转变为单晶材料。
优选地，所述在所述绝缘体上硅(SOI)结构的半导体衬底上形成鳍片的步骤包括：电子束曝光正性抗蚀剂并刻蚀所述局部埋层隔离介质层上方的硅衬底至埋层隔离介质层以嵌入所述半导体衬底形成至少两个凹槽，所述凹槽之间形成鳍片。
优选地，所述鳍片的厚度为10-60nm；
优选地，所述在所述鳍片顶部和侧面形成栅堆叠结构的步骤包括：在鳍片的顶部和侧面形成栅介质层和栅电极材料；光刻、刻蚀形成栅电极堆叠结构；
优选地，在所述栅堆叠结构两侧的鳍片中形成源/漏结构之前，所述方法进一步包括：在鳍片的两侧形成一次侧墙；进行倾角离子注入，以在所述鳍片中形成源/漏延伸区；或进行倾角离子注入，以在所述鳍片中形成晕环注入区。
优选地，所述在栅堆叠结构两侧的鳍片中形成源/漏结构步骤包括：在鳍片的两侧形成二次侧墙；离子注入形成源漏掺杂；形成源漏硅化物。
优选地，所述半导体衬底为体硅衬底。
从上述技术方案可以看出，本发明有以下有益效果：
1、本发明提供的这种半导体场效应晶体管结构及其制备方法在体硅衬底上实现了鳍型场效应晶体管器件的制备，降低了制备的成本，克服了SOIFinFET器件存在的自加热效应和浮体效应，降低了制备成本；
2、本发明提供的这种半导体场效应晶体管结构及其制备方法，非常容易在体硅衬底上形成局部绝缘体上硅结构，很容易制备与衬底相隔离的鳍片结构，大大降低了制备鳍型场效应晶体管的难度；
3、本发明提供的这种半导体场效应晶体管结构及其制备方法，制备工艺简单可行，易于集成，与平面CMOS工艺兼容性好。
附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1、2A-2B、3-5、6A-6C、7A-7C示出了根据本发明实施例的方法制备半导体场效应晶体管的流程中对应的各结构剖面图；
附图标记说明：
101，Si衬底；102，介质层；103，体接触孔；104，非晶硅层；105，STI隔离层；106，凹槽结构；107，鳍片；108，栅介质层；109，栅电极。
应当注意的是，本说明书附图并非按照比例绘制，而仅为示意性的目的，因此，不应被理解为对本发明范围的任何限制和约束。在附图中，相似的组成部分以相似的附图标号标识。
具体实施方式
以下，通过附图中示出的具体实施例来描述本发明。但是应该理解，这些描述只是示例性的，而并非要限制本发明的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本发明的概念。
在附图中示出了根据本发明实施例的层结构示意图。这些图并非是按比例绘制的，其中为了清楚的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
图1、2A-2B、3-5、6A-6C、7A-7C详细示出了根据本发明实施例制备半导体场效应晶体管的各步骤对应的结构剖面图。以下，将参照这些附图来对根据本发明实施例的各个步骤予以详细说明。
首先参考图1，在半导体衬底101上形成介质层102。所述介质层102可以包括：SiO2、TEOS、LTO、Si3N4或其他介质材料，在本发明的实施例中优选为SiO2，可以通过热生长形成，厚度约为20-100nm。所述半导体衬底101可以是半导体制造领域中常用的衬底材料，对于本发明的实施例，优选采用体Si衬底。
接着如图2A和2B所示，在半导体衬底101上形成介质层岛102’和体接触孔103。图2A为沿半导体衬底101表面示意图；图2B为沿AA’方向的剖视图。形成所述介质层岛102’和体接触孔103的方法为：采用光刻或电子束曝光抗蚀剂并反应离子刻蚀介质层102形成介质层岛102’和体接触孔103。
图3为在半导体衬底上形成一层非晶硅层104的示意图。所述非晶硅层104的形成方法可以包括：低压化学气相淀积(LPCVD)、离子束溅射等；在本发明的实施例，优选采用LPCVD方法。所述非晶硅层104的厚度约为200nm-1000nm。
接着如图4所示，将非晶硅层104转变为单晶硅层104’并化学机械抛光(CMP)形成具有隔离介质层的局部绝缘体上硅(SOI)结构的半导体衬底。所述非晶硅层104转变为单晶硅层104’的方法可以包括：横向固相外延(LSPE)技术、激光再结晶法、卤素灯或条形加热器再结晶等；在本发明的实施例，优选采用LSPE技术。所述LSPE技术外延的过程为：首先，将直接与半导体衬底101相接触的非晶硅层104在垂直方向进行垂直固相外延，将其转变为单晶硅层104’；然后，将介质层岛102’上方覆盖的非晶硅层104进行横向固相外延将其转变为单晶硅层104’；最终将所有的非晶硅层104都转变为单晶硅层104’。
接着如图5所示在半导体衬底101上形成STI隔离结构105。
图6A示出了沿半导体衬底101表面的示意图，图6B和6C分别为图6A中沿AA’和BB’方向的剖视图。如图6B、6C所示，对所述单晶硅层104’进行刻蚀形成凹槽结构106，同时两个相邻凹槽之间形成鳍片107。鳍片107的底部通过体接触103’与衬底相连。该体接触有利于消除器件的浮体效应，同时该体接触103’还有利于器件沟道处的散热，提高器件的性能。刻蚀形成所述凹槽结构106的方法例如可以是：采用电子束曝光正性抗蚀剂并反应离子刻蚀形成陡直的宽度约为200-400nm的凹槽结构106。凹槽的形状只是示例，本发明对此不做限制。所述鳍片107的厚度为10-60nm。
接着参考图7A、7B和7C，在整个衬底上形成栅介质层材料108和栅电极材料109，然后刻蚀形成栅电极叠层结构。图7A示出了沿半导体衬底101表面的示意图，图7B和7C分别是沿图7A中AA’和BB’方向的剖视图。所述栅介质层材料108可以是普通栅介质材料，例如SiO2，或者是其他的高k介质材料，例如SiON和HfAlON、HfTaON、HfSiON、Al2O3等，在本发明地实施例中优选HfSiON，可通过低压化学气相沉积、金属有机化学气相沉积或者原子层淀积等方法形成，栅介质的等效氧化层厚度为5至所述栅电极材料109可以是难熔金属W，Ti，Ta，Mo和金属氮化物，例如TiN，TaN，HfN，MoN等或其他材料，栅电极材料可采用低压化学气相淀积，金属有机化学气相沉积、原子层淀积或其他方法形成，厚度可选为2000至
接着，在所述栅堆叠结构两侧的鳍片中形成源/漏结构之前，所述方法进一步包括：在鳍片的两侧形成一次侧墙；进行倾角离子注入，以在所述鳍片中形成源/漏延伸区；或进行倾角离子注入，以在所述鳍片中形成晕环注入区。
接着，可以在栅堆叠的侧壁上形成二次侧墙。二次侧墙的形成可以参照常规技术，这里不再赘述。
接着，在栅堆叠两侧的半导体衬底中进行离子注入形成源/漏区并形成源漏硅化物。
最后，金属化形成互连结构将电极引出。金属化的形成可以参照常规技术，这里不再赘述。
此外，本发明的实施例能够在体硅衬底上实现了半导体器件的制备。该方法采用传统的基于准平面的自顶向下工艺，制备工艺简单可行，与CMOS平面工艺具有良好的兼容性，并且易于集成。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过现有技术中的各种手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。
以上参照本发明的实施例对本发明予以了说明。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本发明的范围。本发明的范围由所附权利要求及其等价物限定。不脱离本发明的范围，本领域技术人员可以做出多种替换和修改，这些替换和修改都应落在本发明的范围之内。
Claims (10)
1.一种制备半导体场效应晶体管结构的方法，包括：
形成具有体接触孔的绝缘体上硅(SOI)结构的第一半导体衬底；
在所述绝缘体上硅(SOI)结构的第一半导体衬底上形成鳍片；
在所述鳍片顶部和侧面形成栅堆叠结构；
在所述栅堆叠结构两侧的鳍片中形成源/漏结构；
金属化，其中，形成具有体接触孔的绝缘体上硅(SOI)结构的第一半导体衬底的步骤包括：
在第二半导体衬底上形成介质层；
光刻、刻蚀所述介质层形成介质层岛及体接触孔；
在第二半导体衬底上形成一层非晶硅材料；
将非晶硅材料转变为单晶材料并进行化学机械抛光(CMP)形成具有体接触孔的绝缘体上硅(SOI)结构的第一半导体衬底。
2.根据权利要求1所述的方法，其中，所述介质层包括SiO2、TEOS、LTO或Si3N4，厚度为20-100nm。
3.根据权利要求1所述的方法，其中，在第二半导体衬底上形成一层非晶硅材料步骤中，所述非晶硅材料的形成采用低压化学气相淀积(LPCVD)或离子束溅射的方法；所述非晶硅材料的厚度为200nm-1000nm。
4.根据权利要求1所述的方法，其中，所述将非晶硅材料转变为单晶材料并进行化学机械抛光(CMP)形成具有体接触孔的绝缘体上硅(SOI)结构第一半导体衬底的步骤中，采用横向固相外延(LSPE)技术、激光再结晶法、卤素灯或条形加热器再结晶的方法将非晶硅材料转变为单晶材料。
5.根据权利要求1所述的方法，所述在所述绝缘体上硅(SOI)结构的第一半导体衬底上形成鳍片的步骤包括：
电子束曝光正性抗蚀剂并刻蚀所述介质层岛上方的单晶硅层至介质层岛以嵌入所述具有体接触孔的绝缘体上硅(SOI)结构的第一半导体衬底形成至少两个凹槽，所述凹槽之间形成鳍片。
6.根据权利要求5所述的方法，其中，所述鳍片的厚度为10-60nm。
7.根据权利要求1所述的方法，其中，所述在所述鳍片顶部和侧面形成栅堆叠结构的步骤包括：
在鳍片的顶部和侧面形成栅介质层和栅电极材料；
光刻、刻蚀形成栅电极堆叠结构。
8.根据权利要求1所述的方法，其中，在所述栅堆叠结构两侧的鳍片中形成源/漏结构之前，所述方法进一步包括：
在鳍片的两侧形成一次侧墙；
进行倾角离子注入，以在所述鳍片中形成源/漏延伸区；或
进行倾角离子注入，以在所述鳍片中形成晕环注入区。
9.根据权利要求1所述的方法，其中，在所述栅堆叠结构两侧的鳍片中形成源/漏结构步骤包括：
在鳍片的两侧形成二次侧墙；
离子注入形成源漏掺杂；
形成源漏硅化物。
10.根据权利要求1至9中任一项所述的方法，其中，所述第二半导体衬底为体硅衬底。
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