CN103545370A - 用于功率mos晶体管的装置和方法 - Google Patents

用于功率mos晶体管的装置和方法 Download PDF

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CN103545370A
CN103545370A CN201210436625.3A CN201210436625A CN103545370A CN 103545370 A CN103545370 A CN 103545370A CN 201210436625 A CN201210436625 A CN 201210436625A CN 103545370 A CN103545370 A CN 103545370A
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drain
region
groove
field plate
epitaxial loayer
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CN103545370B (zh
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苏柏智
周学良
伍震威
柳瑞兴
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种功率MOS晶体管包括形成在衬底的第一面上方的漏极接触塞；形成在衬底的第二面上方的源极接触塞和形成在第一漏极/源极区和第二漏极/源极区之间的沟槽。沟槽包括第一栅电极、第二栅电极，其中第一栅电极和第二栅电极的顶面与漏极区的底面对准。沟槽进一步包括形成在第一栅电极和第二栅电极之间的场板，其中，场板电连接至源极区。本发明提供用于功率MOS晶体管的装置和方法。

Description

用于功率MOS晶体管的装置和方法
技术领域
本发明涉及用于功率MOS晶体管的装置和方法。
背景技术
由于在各种电气元件(例如，晶体管、二极管、电阻器、电容器等)的集成密度方面的改进，半导体产业经历了快速增长。对于大多数情况，集成密度的这种改进源于收缩半导体工艺节点(例如，朝着sub-20nm节点收缩工艺节点)。随着半导体器件按比例缩小，需要新技术来维持电气元件从一代到下一代的性能。例如，对于高功率应用，期望低接通电阻、低栅极电荷和高击穿电压功率晶体管。
随着半导体技术的进展，金属氧化物半导体(MOS)晶体管已广泛用于现今的集成电路中。MOS晶体管是电压控制型器件。当对MOS晶体管的栅极施加控制电压，并且控制电压大于MOS晶体管的阈值时，在MOS晶体管的漏极和源极之间建立导电沟道。结果，电流在MOS晶体管的漏极和源极之间流动。另一方面，当对MOS晶体管的栅极施加的控制电压小于MOS晶体管的阈值时，相应地关闭MOS晶体管。
MOS晶体管可以包括两大类。一类是n沟道MOS晶体管；另一类是p沟道MOS晶体管。根据结构差异，MOS晶体管可以进一步分成两个子类：平面MOS晶体管和垂直MOS晶体管。
垂直功率MOS晶体管由于它们的低栅极驱动功率、快速开关速率和低导通电阻而广泛用于高电压和电流应用中。在垂直功率MOSFET中，漏极和栅极被设置在晶圆的相对面上。在垂直功率MOS晶体管的漏极和源极之间可能形成有沟槽结构。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种装置，包括：第一漏极/源极接触塞，形成在衬底的第一面的上方，其中，所述第一漏极/源极接触塞连接至第一漏极/源极区；第二漏极/源极接触塞，形成在所述衬底的第二面的上方，其中，所述第二漏极/源极接触塞连接至第二漏极/源极区；以及沟槽，形成在所述第一漏极/源极接触塞和所述第二漏极/源极接触塞之间，其中，所述沟槽包括：第一栅电极；第二栅电极，其中：所述第一栅电极和所述第二栅电极形成在所述沟槽的下部中；以及沿着所述沟槽的上部的侧壁形成两个漂移区；以及场板，形成在所述第一栅电极和所述第二栅电极之间，其中，所述场板电连接至所述第二漏极/源极区。
在上述装置中，进一步包括：第一扩散区，包括第一n型漏极漂移区；以及第二扩散区，包括第二n型漏极漂移区，其中，所述第一n型漏极漂移区和所述第二n型漏极漂移区相对于所述沟槽是对称的。
在上述装置中，进一步包括：p型外延层，形成在所述衬底上方；以及p+区域，形成在所述p型外延层中，其中，所述p+区域电连接至所述场板。
在上述装置中，进一步包括：p型外延层，形成在所述衬底上方；以及p+区域，形成在所述p型外延层中，其中，所述p+区域电连接至所述场板，进一步包括：第二n+区域，形成在所述沟槽的底面和所述p+区域之间。
在上述装置中，进一步包括：p型外延层，形成在所述衬底上方；以及p+区域，形成在所述p型外延层中，其中，所述p+区域电连接至所述场板，进一步包括：第二n+区域，形成在所述沟槽的底面和所述p+区域之间，其中，所述第二n+区域通过所述场板、所述p+区域和所述衬底连接至所述第二漏极/源极接触塞。
在上述装置中，进一步包括：第一介电膜，形成在所述第一栅电极和所述场板之间；以及第二介电膜，形成在所述第二栅电极和所述场板之间。
在上述装置中，进一步包括：第一介电膜，形成在所述第一栅电极和所述场板之间；以及第二介电膜，形成在所述第二栅电极和所述场板之间，其中：所述第一介电膜和所述第二介电膜由氧化物形成并具有介于约0.1μm至约0.5μm范围内的厚度。
在上述装置中，其中：所述第一漏极/源极区是沟槽功率晶体管的漏极；以及所述第二漏极/源极区是所述沟槽功率晶体管的源极。
根据本发明的另一方面，还提供了一种器件，包括：漏极区，具有第一导电类型，所述漏极区形成在具有第二导电类型的衬底上方；源极区，具有所述第一导电类型，所述源极区形成在所述衬底上方；以及沟槽，形成在所述漏极区和所述源极区之间，其中，所述沟槽包括：第一栅电极；场板，邻近所述第一栅电极形成，其中，所述第一栅电极和所述场板通过第一介电膜分开，并且，所述场板电连接至所述源极区；以及第二栅电极，邻近所述场板形成，其中，所述第一栅电极和所述第二栅电极相对于所述场板是对称的。
在上述器件中，进一步包括：第一漏极漂移区，连接至所述漏极区域；以及第二漏极漂移区，连接至所述漏极区域，其中，所述第一漏极漂移区和所述第二漏极漂移区相对于所述沟槽是对称的。
在上述器件中，进一步包括：第一外延层，具有所述第二导电类型，所述第一外延层形成在所述衬底上方；以及第二外延层，具有所述第一导电类型，所述第二外延层形成在所述第一外延层上方。
在上述器件中，其中：所述第一导电类型是n型导电性；以及所述第二导电类型是p型导电性。
在上述器件中，其中：所述第一导电类型是p型导电性；以及所述第二导电类型是n型导电性。
在上述器件中，进一步包括：漏极接触塞，连接至所述漏极区，其中，所述漏极接触塞形成在所述衬底的第一面的上方；以及源极接触塞，连接至所述源极区，其中，所述源极接触塞形成在所述衬底的第二面的上方。
根据本发明的又一方面，还提供了一种方法，包括：提供具有第二导电类型的衬底；生长具有所述第二导电类型的第一外延层；生长具有第一导电类型的第二外延层；在所述第一外延层和所述第二外延层中形成沟槽；在所述沟槽中形成第一栅电极；在所述沟槽中形成第二栅电极；分别使用所述第一栅电极和所述第二栅电极作为离子注入掩模实施离子注入工艺以形成第一漏极漂移区和第二漏极漂移区；在所述沟槽中形成场板，其中，所述场板位于所述第一栅电极和所述第二栅电极之间；在所述第二外延层中形成漏极区，其中，所述漏极区具有所述第一导电类型；以及在所述第一外延层中形成源极区，其中，所述源极区具有所述第一导电类型，并且其中所述源极区电连接至所述场板。
在上述方法中，进一步包括：沿着所述沟槽的第一侧壁形成所述第一漏极漂移区；以及沿着所述沟槽的第二侧壁形成所述第二漏极漂移区，其中，所述第一栅电极和所述第二栅电极的上部与所述第一漏极漂移区和所述第二漏极漂移区的底部对准。
在上述方法中，进一步包括：用第一介电膜填充所述场板和所述第一栅电极之间的空闲空间。
在上述方法中，进一步包括：用第一介电膜填充所述场板和所述第一栅电极之间的空闲空间，其中：所述第一介电膜由氧化物形成；以及所述第一介电膜的厚度介于约0.1μm至约0.5μm的范围内。
在上述方法中，进一步包括：形成连接至所述漏极区的漏极接触塞，其中，所述漏极接触塞形成在所述衬底的第一面的上方；以及形成连接至所述源极区的源极接触塞，其中，所述源极接触塞形成在所述衬底的第二面的上方。
在上述方法中，进一步包括：形成连接至所述漏极区的漏极接触塞，其中，所述漏极接触塞形成在所述衬底的第一面的上方；以及形成连接至所述源极区的源极接触塞，其中，所述源极接触塞形成在所述衬底的第二面的上方，进一步包括：在所述第一外延层中形成p+区域，其中，所述源极区通过所述场板、所述p+区域和所述衬底连接至所述源极接触塞。
附图说明
为了更充分地理解本发明及其优点，现将参考结合附图所进行的以下描述，其中：
图1是根据实施例的底部源极沟槽功率MOSFET的截面图；
图2示出根据实施例的包括底部源极沟槽功率MOSFET的半导体器件的截面图；
图3示出根据实施例的衬底的截面图；
图4示出根据实施例从衬底生长外延层后图3所示的半导体器件的截面图；
图5示出根据实施例从p型外延层生长另一外延层后图4所示的半导体器件的截面图；
图6示出根据实施例在半导体器件上沉积介电层后图5所示的半导体器件的截面图；
图7示出根据实施例在介电层上沉积硬掩模层后图6所示的半导体器件的截面图；
图8示出根据实施例在外延层中形成第一沟槽后图7所示的半导体器件的截面图；
图9示出根据实施例在沟槽中形成第一栅极介电层后图8所示的半导体器件的截面图；
图10示出根据实施例在沟槽中形成栅电极层后图9所示的半导体器件的截面图；
图11示出根据实施例对栅电极层实施蚀刻工艺后图10所示的半导体器件的截面图；
图12示出根据实施例在形成n+区域后图11所示的半导体器件的截面图；
图13示出根据实施例在形成两个n型漏极漂移区后图12所示的半导体器件的截面图；
图14示出根据实施例在沟槽中和在半导体器件的表面上沉积氧化层后图13所示的半导体器件的截面图；
图15示出根据实施例对氧化层的底部实施各向异性蚀刻工艺后图14所示的半导体器件的截面图；
图16示出根据实施例在形成第二沟槽后图15所示的半导体器件的截面图；
图17示出根据实施例在形成p+区域后图16所示的半导体器件的截面图；
图18示出根据实施例在沟槽中形成场板后图17所示的半导体器件的截面图；
图19示出根据实施例对场板实施回蚀工艺后图18所示的半导体器件的截面图；
图20示出根据实施例对半导体器件的顶面实施硬掩模去除工艺后图19所示的半导体器件的截面图；
图21示出根据实施例在n型外延层中形成n+区域后图20所示的半导体器件的截面图；
图22示出根据实施例在沟槽中形成介电区域后图21所示的半导体器件的截面图；以及
图23示出根据实施例在形成漏极和源极接触塞后图22所示的半导体器件的截面图。
除非另有说明，不同附图中的相应数字和符号通常是指相应的部件。绘制附图用于清楚地示出各个实施例的相关方面而不必按比例绘制。
具体实施方式
在下面详细讨论本发明实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的发明构思。所讨论的具体实施例仅是制造和使用本发明实施例的示例性具体方式，而不用于限制本发明的范围。
将参照具体情况下的实施例(底部源极功率金属氧化物半导体场效应晶体管(MOSFET))描述本发明。然而，本发明的实施例也可以适用于各种高电压晶体管。然而，本发明的实施例也可以适用于各种半导体器件结构。下文将参照附图详细说明各个实施例。
图1是根据实施例的底部源极沟槽功率MOSFET的截面图。如图1所示，在晶圆的相对面上制造底部源极沟槽功率MOSFET 100的源极接触塞102和漏极接触塞112。具体而言，源极接触塞102形成在p+衬底104的下方。漏极接触塞112形成在p+衬底104的上方。底部源极沟槽功率MOSFET 100进一步包括从p+衬底104生长的p型外延层106。在p型外延层106中形成n+源极区124。在漏极接触塞112下方形成n+漏极区110。在n+漏极区110和p型外延层106之间形成n型外延层108。
如图1所示，可以在n+源极区124和漏极接触塞112之间形成有沟槽132。沟槽包括场板116、氧化膜114、第一栅极介电层902、第二栅极介电层1402和两个栅极区128。栅极区128形成在沟槽132的下半部。场板116形成在两个栅极区128之间并通过p+区126和p+衬底104电连接至源极接触塞102。
与在栅极沟槽中具有单个栅极区的常规沟槽MOS晶体管相比，底部源极沟槽功率MOSFET 100通过将栅极区分裂成两个较小的栅极区而具有相对较小的栅极区，如1所示。此外，场板116用于填充图1所示的栅极区之间的开口。通过减少栅极区的面积，底部源极沟槽功率MOSFET 100的栅极电荷也相应地减少了。简言之，具有连接至源极接触塞102的场板116的一个有利特征是提高了栅极电荷电容。结果，可以减少底部源极沟槽功率MOSFET 100的开关损耗。
氧化膜114、第一栅极介电层902和第二栅极介电层1402填充沟槽132的空闲空间，从而使栅极区128、场板116和漏极接触塞112彼此绝缘。根据实施例，第二栅极介电层1402充当场板116和栅极区128之间的绝缘膜。第二栅极介电层1402具有厚度D1，其介于约0.1μm至约0.5μm的范围内。
底部源极沟槽功率MOSFET 100可以包括沿着沟槽的外侧周边形成的两个n型漏极漂移(NDD)区。NDD区122相对于沟槽是对称的。NDD区122是漏极的延伸并电连接至漏极接触塞112。
根据实施例，通过n+漏极区110、n型外延层108和NDD区122形成底部源极沟槽功率MOSFET 100的漏极区。为了使漏极区与外部电路(未示出)连接，漏极区连接至漏极接触塞112。为了减少栅漏电容，NDD区122可以形成为与栅极区128对准。具体而言，在NDD离子注入工艺中，栅极区128用作离子注入掩模，从而阻止NDD区的离子进入栅极区128上部区域下方的区域中。结果，NDD区122的下部与栅极区128的上部水平对准。
图2示出根据实施例的包括底部源极沟槽功率MOSFET的半导体器件的截面图。半导体器件200包括5个区域，即，用于形成底部源极沟槽功率MOSFET器件的第一区域202、用于形成平面NMOS器件的第二区域204、用于形成平面PMOS器件的第三区域206、用于形成低电压NMOS器件的第四区域208和用于形成低电压PMOS器件的第五区域210。区域202、204、206、208和210中的每一个区域都通过诸如浅沟槽隔离(STI)区的绝缘区域限定。可选地，场氧化物可以形成为绝缘区域。
如图2所示，为了集成底部源极沟槽功率MOSFET器件与横向MOS器件(例如，平面NMOS器件)，如图2所示的深p型阱用于将横向MOS器件与底部源极沟槽功率MOSFET器件隔离开。具有如图1所示的底部源极沟槽功率MOSFET 100的一个有利特征是底部源极沟槽功率MOSFET结构可以与横向MOS器件集成。鉴于此，可以重新使用现有的横向器件制造工艺。现有的横向器件制造工艺有助于降低制造底部源极沟槽功率MOSFET的成本。
图3至图22示出根据实施例制造图1所示的底部源极沟槽功率MOSFET 100的中间步骤。图3示出根据实施例的衬底104的截面图。衬底104可以由硅、硅锗、碳化硅等形成。根据实施例，衬底104可以是p+衬底，其掺杂有p型杂质，诸如硼、铟等。衬底104的掺杂密度介于约1018/cm3至约1021/cm3的范围内。
图4示出根据实施例从p型衬底104生长外延层后图3所示的半导体器件的截面图。从p型衬底104生长p型外延层106。可以通过采用诸如化学汽相沉积(CVD)、超高真空化学汽相沉积(UHV-CVD)等合适的半导体制造工艺实现p型外延层106的外延生长。根据实施例，p型外延层106的掺杂密度介于约1014/cm3至约1016/cm3的范围内。
图5示出根据实施例从p型外延层生长另一外延层后图4所示的半导体器件的截面图。从p型外延层106生长n型外延层108。可以通过采用诸如CVD、UHV-CVD等合适的制造工艺来实现n型外延层108的外延生长。根据实施例，n型外延层108的掺杂密度介于约1014/cm3至约1016/cm3的范围内。
图6示出根据实施例在半导体器件上沉积介电层后图5所示的半导体器件的截面图。介电层602可以包括氧化层。可以通过任何氧化工艺(诸如在包含氧化物、H2O、NO、或它们的组合的周围环境中的湿法或干法热氧化)或者通过使用原硅酸四乙酯(TEOS)和氧气作为前体的CVD技术形成介电层602。
图7示出根据实施例在介电层上沉积硬掩模层后图6所示的半导体器件的截面图。硬掩模层702充当蚀刻掩模。硬掩模层702可以由合适的材料(诸如氮化硅)形成。在整个说明书中，硬掩模层702可以可选地被称为氮化物层702。通过诸如CVD等合适的制造技术在介电层602的顶部上沉积氮化物层702。
图8示出根据实施例在外延层中形成第一沟槽后图7所示的半导体器件的截面图。考虑到底部源极沟槽功率MOSFET 100的沟槽132的位置(在图1中示出)对氮化物层702进行图案化。此后，实施诸如反应离子蚀刻(RIE)或其他干蚀刻、各向异性湿蚀刻、或任何其他合适的各向异性蚀刻的蚀刻工艺或者图案化工艺以形成沟槽802。对包括n型外延层108和p型外延层106的外延层进行蚀刻以形成第一沟槽802。如图8所示，蚀刻工艺可以蚀刻穿过n型外延层108并部分蚀刻p型外延层106以形成第一沟槽802。
图9示出根据实施例在沟槽中形成第一栅极介电层后图8所示的半导体器件的截面图。如图9所示，在第一沟槽802的底部以及第一沟槽802的侧壁上形成第一栅极介电层902。第一栅极介电层902可以由诸如氧化物、氮化物、氮氧化物、高k材料、它们的组合以及它们的多层的常用介电材料形成。根据实施例，第一栅极介电层902是氧化层。可以通过合适的热处理技术、湿处理技术或诸如PVD、CVD、ALD等沉积技术形成第一栅极介电层902。
图10示出根据实施例在沟槽中形成栅电极层后图9所示的半导体器件的截面图。栅电极层1002可以包含导电材料，诸如金属(例如，钽、钛、钼、钨、铂、铝、铪、钌)、金属硅化物(例如，硅化钛、硅化钴、硅化镍、硅化钽)、金属氮化物(例如，氮化钛、氮化钽)、掺杂的多晶硅、其他导电材料、或这些的组合。在一个实例中，沉积非晶硅并进行重结晶以形成多晶硅(poly-silicon)。
根据实施例，栅电极层1002由多晶硅形成。可以通过经由低压化学汽相沉积(LPCVD)沉积掺杂的或非掺杂的多晶硅来形成栅电极层1002。根据另一实施例，栅电极层1002由诸如氮化钛、氮化钽、氮化钨、钛、钽和/或这些的组合的金属材料形成。采用诸如ALD、CVD、PVD等合适的沉积技术在第一栅极介电层902上形成金属栅电极层。上述沉积技术均为本领域所熟知的，并因此在此不再讨论。
图11示出根据实施例对栅电极层实施蚀刻工艺后图10所示的半导体器件的截面图。实施蚀刻工艺以去除不想要的栅电极层部分，从而形成栅电极128，如图11中所示。根据实施例，栅电极材料为多晶硅。蚀刻工艺可以是湿法或干法、各向异性或各向同性蚀刻工艺，但优选各向异性干蚀刻工艺。如图11所示，栅电极128的顶面低于n型外延层108的底面。
图12示出根据实施例在p型外延层中形成n+区域后图11所示的半导体器件的截面图。如图12所示，通过合适的制造工艺(诸如离子注入工艺)形成n+区域124。根据实施例，n+区域124可以充当图1所示的底部源极沟槽功率MOSFET 100的源极区。
在衬底104是p型衬底的实施例中，可以通过注入诸如磷、砷等适当的n型掺杂物来形成源极区124。可选地，在衬底104是n型衬底的实施例中，可以通过注入诸如硼、镓、铟等适当的p型掺杂物来形成源极区124。根据实施例，源极区124的掺杂密度介于约1019/cm3至约1021/cm3的范围内。
图13示出根据实施例在形成两个n型漏极漂移区后图12所示的半导体器件的截面图。如图13所示，可以通过合适的制造工艺(诸如倾斜角离子注入工艺)形成n型漏极漂移区122。根据实施例，可以通过注入适当的n型掺杂物(诸如磷)形成n型漏极漂移区122。还应当注意到，可以可选地使用其他n型掺杂物，诸如砷、氮、锑、它们的组合等。根据实施例，n型漏极漂移区122的掺杂密度介于约1015/cm3至约1018/cm3的范围内。
如图13所示，箭头1302表示倾斜角离子注入工艺的方向。通过控制如图13中的箭头1302所示的离子注入的方向，栅极区128可以充当离子注入掩模。结果，栅极区128阻止离子进入栅极区128上部下方的区域。如图13所示，在实施离子注入工艺之后，n型漏极漂移区122的底部与栅电极128的上部几乎对准。
在n型漏极漂移区122和栅电极128之间具有这种对准的一个有利特征是可以相应地减少底部源极沟槽功率MOSFET 100的栅漏电容。这种减少的栅漏电容有助于进一步改善底部源极沟槽功率MOSFET 100的开关损耗。
图14示出根据实施例在沟槽中和半导体器件表面上沉积第二栅极介电层后图13所示的半导体器件的截面图。第二栅极介电层1402可以包含氧化物。可以通过任何合适的氧化工艺(诸如湿法或干法热氧化工艺)、CVD等形成第二栅极介电层1402。根据实施例，可以控制氧化工艺从而使第二栅极介电层1402的厚度介于约0.1μm至约0.5μm的范围内。
图15示出根据实施例对氧化层的底部实施各向异性蚀刻工艺后图14所示的半导体器件的截面图。实施诸如反应离子蚀刻(RIE)或其他干蚀刻、各向异性湿蚀刻或任何其他合适的各向异性蚀刻的蚀刻工艺或者图案化工艺以去除第二栅极介电层1402的底部。结果，n+区域124的顶面的中间部分不包含氧化物。
图16示出根据实施例在形成第二沟槽之后图15所示的半导体器件的截面图。与图8所示的形成第一沟槽类似，对n+区域124的顶面实施诸如反应离子蚀刻(RIE)或其他干蚀刻、各向异性湿蚀刻、或任何其他合适的各向异性蚀刻的蚀刻工艺或者图案化工艺。结果，形成第二沟槽1602。如图16所示，蚀刻工艺可以蚀刻穿过n+区域124并部分蚀刻p型外延层106从而形成第二沟槽1602。
图17示出根据实施例在形成p+区域后图16所示的半导体器件的截面图。邻近n+区域124形成p+区域126。可以通过以介于约1019/cm3至约1021/cm3之间的浓度注入诸如硼的p型掺杂物来形成p+区域126。如图17所示，第二沟槽1602的底部被p+区域126围绕。
图18示出根据实施例在沟槽中形成场板后图17所示的半导体器件的截面图。场板116可以由导电材料钽、钛、钼、钨、铂、铝、铪、钌或它们的组合形成。根据实施例，场板116由钨形成。可以通过经由合适的制造技术(诸如低压化学汽相沉积(LPCVD))沉积钨形成场板116。
图19示出根据实施例对场板实施回蚀工艺后图18所示的半导体器件的截面图。对场板116的顶部实施回蚀工艺。结果，去除场板116的一部分。根据实施例，图1所示的底部源极沟槽功率MOSFET 100的击穿电压与场板116的高度有关。鉴于此，控制回蚀工艺从而使场板116的高度能够满足底部源极沟槽功率MOSFET 100的击穿电压要求。
图20示出根据实施例对半导体器件的顶面实施硬掩模去除工艺后图19所示的半导体器件的截面图。如图20所示，通过合适的硬掩模层去除工艺(诸如湿蚀刻工艺)去除了图19所示的硬掩模层和氧化层。对半导体器件的顶面实施去除工艺直到暴露出n型外延层108。
图21示出根据实施例在n型外延层中形成n+区域后图20所示的半导体器件的截面图。如图21所示，通过离子注入工艺形成n+区域110。n+区域充当图1所示的底部源极沟槽功率MOSFET的漏极区。应当注意到底部源极沟槽功率MOSFET的漏极可以包括n+区域110、n型外延层108和NDD区122。
在衬底104是p型衬底的实施例中，可以通过注入诸如磷、砷等适当的n型掺杂物形成漏极区110。可选地，在衬底104是n型衬底的实施例中，可以通过注入诸如硼、镓、铟等适当的p型掺杂物形成漏极区110。根据实施例，漏极区110的掺杂密度介于约1019/cm3至约1021/cm3的范围内。
图22示出根据实施例在沟槽中形成介电区域后图21所示的半导体器件的截面图。介电区域114可以由诸如氧化硅的氧化物形成。根据实施例，用氧化物填充沟槽直到氧化物的顶面高于n+区域110的顶面。
如图22所示，场板116通过介电区域114与有源区域(例如，NDD区122和n型外延层108)分开。同样地，场板116与栅电极128绝缘。根据实施例，场板116和栅电极128之间的隔离介于约0.1μm至约0.5μm的范围内。
图23示出根据实施例在形成漏极和源极接触塞后图22所示的半导体器件的截面图。漏极接触塞112和源极接触塞102可以由导电材料形成。可以通过合适的制造工艺(诸如镶嵌工艺)形成漏极接触塞112和源极接触塞102。
如图23所示，在p型衬底104的相对面上形成漏极接触塞112和源极接触塞102。在漏极接触塞112和源极接触塞102之间形成包含栅电极128和场板116的沟槽。而且，场板116通过p+区域126和p型衬底104电连接至源极接触塞102。应该注意到在图23中源极区是n+区域124。场板116、p+区域126和p+衬底104形成源极区(n+区域124)和源极接触塞102之间的低电阻电流路径。
尽管已经详细地描述了本发明实施例及其优点，但应该理解，可以在不背离所附权利要求限定的本发明的精神和范围的情况下，在其中进行各种改变、替换和更改。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明将很容易理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。

Claims (10)

1.一种装置，包括：
第一漏极/源极接触塞，形成在衬底的第一面的上方，其中，所述第一漏极/源极接触塞连接至第一漏极/源极区；
第二漏极/源极接触塞，形成在所述衬底的第二面的上方，其中，所述第二漏极/源极接触塞连接至第二漏极/源极区；以及
沟槽，形成在所述第一漏极/源极接触塞和所述第二漏极/源极接触塞之间，其中，所述沟槽包括：
第一栅电极；
第二栅电极，其中：
所述第一栅电极和所述第二栅电极形成在所述沟槽的下部中；以及
沿着所述沟槽的上部的侧壁形成两个漂移区；以及
场板，形成在所述第一栅电极和所述第二栅电极之间，其中，所述场板电连接至所述第二漏极/源极区。
2.根据权利要求1所述的装置，进一步包括：
第一扩散区，包括第一n型漏极漂移区；以及
第二扩散区，包括第二n型漏极漂移区，其中，所述第一n型漏极漂移区和所述第二n型漏极漂移区相对于所述沟槽是对称的。
3.根据权利要求1所述的装置，进一步包括：
p型外延层，形成在所述衬底上方；以及
p+区域，形成在所述p型外延层中，其中，所述p+区域电连接至所述场板。
4.根据权利要求3所述的装置，进一步包括：
第二n+区域，形成在所述沟槽的底面和所述p+区域之间。
5.一种器件，包括：
漏极区，具有第一导电类型，所述漏极区形成在具有第二导电类型的衬底上方；
源极区，具有所述第一导电类型，所述源极区形成在所述衬底上方；以及
沟槽，形成在所述漏极区和所述源极区之间，其中，所述沟槽包括：
第一栅电极；
场板，邻近所述第一栅电极形成，其中，所述第一栅电极和所述场板通过第一介电膜分开，并且，所述场板电连接至所述源极区；以及
第二栅电极，邻近所述场板形成，其中，所述第一栅电极和所述第二栅电极相对于所述场板是对称的。
6.根据权利要求5所述的器件，进一步包括：
第一漏极漂移区，连接至所述漏极区域；以及
第二漏极漂移区，连接至所述漏极区域，其中，所述第一漏极漂移区和所述第二漏极漂移区相对于所述沟槽是对称的。
7.根据权利要求5所述的器件，进一步包括：
第一外延层，具有所述第二导电类型，所述第一外延层形成在所述衬底上方；以及
第二外延层，具有所述第一导电类型，所述第二外延层形成在所述第一外延层上方。
8.一种方法，包括：
提供具有第二导电类型的衬底；
生长具有所述第二导电类型的第一外延层；
生长具有第一导电类型的第二外延层；
在所述第一外延层和所述第二外延层中形成沟槽；
在所述沟槽中形成第一栅电极；
在所述沟槽中形成第二栅电极；
分别使用所述第一栅电极和所述第二栅电极作为离子注入掩模实施离子注入工艺以形成第一漏极漂移区和第二漏极漂移区；
在所述沟槽中形成场板，其中，所述场板位于所述第一栅电极和所述第二栅电极之间；
在所述第二外延层中形成漏极区，其中，所述漏极区具有所述第一导电类型；以及
在所述第一外延层中形成源极区，其中，所述源极区具有所述第一导电类型，并且其中所述源极区电连接至所述场板。
9.根据权利要求8所述的方法，进一步包括：
沿着所述沟槽的第一侧壁形成所述第一漏极漂移区；以及
沿着所述沟槽的第二侧壁形成所述第二漏极漂移区，其中，所述第一栅电极和所述第二栅电极的上部与所述第一漏极漂移区和所述第二漏极漂移区的底部对准。
10.根据权利要求8所述的方法，进一步包括：
用第一介电膜填充所述场板和所述第一栅电极之间的空闲空间。
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US20170222023A1 (en) 2017-08-03
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