CN106098783B - 一种鳍式场效应晶体管及其制备方法 - Google Patents
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- 238000002360 preparation method Methods 0.000 title claims abstract description 23
- 238000002353 field-effect transistor method Methods 0.000 title abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 37
- 238000005516 engineering process Methods 0.000 claims abstract description 12
- 230000005669 field effect Effects 0.000 claims abstract description 8
- 230000000694 effects Effects 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 39
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims description 23
- 238000002955 isolation Methods 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 230000003647 oxidation Effects 0.000 claims description 14
- 238000007254 oxidation reaction Methods 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 14
- 230000000873 masking effect Effects 0.000 claims description 12
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 10
- 230000007797 corrosion Effects 0.000 claims description 10
- 238000005260 corrosion Methods 0.000 claims description 10
- 238000005498 polishing Methods 0.000 claims description 10
- 238000000231 atomic layer deposition Methods 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 9
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 238000009616 inductively coupled plasma Methods 0.000 claims description 8
- 238000011049 filling Methods 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000003989 dielectric material Substances 0.000 claims description 5
- 238000000609 electron-beam lithography Methods 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- 238000004151 rapid thermal annealing Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 238000001704 evaporation Methods 0.000 claims description 2
- 230000008020 evaporation Effects 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 2
- 238000000671 immersion lithography Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 238000007747 plating Methods 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 238000003786 synthesis reaction Methods 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 238000000992 sputter etching Methods 0.000 claims 1
- 238000001947 vapour-phase growth Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 3
- 238000000407 epitaxy Methods 0.000 abstract description 2
- 239000000243 solution Substances 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000012190 activator Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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-
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Abstract
本发明提供一种低功耗鳍式场效应晶体管及其制备方法,属于超大规模集成电路制造技术领域。该场效应晶体管的侧壁沟道层厚度和顶部沟道层厚度均在10nm以下,且在远离顶栅控制的深体区形成了鳍型隔离条,本发明有利于器件沟长的进一步缩小,可有效提高器件的短沟道效应控制能力,减小了静态功耗。此外本发明器件源漏区是单晶有源岛,具有较小的源漏串联电阻,与传统的使用抬升源漏结构的鳍型场效应晶体管相比,不需要外延工艺抬升源漏,即可获得较高的开态电流。本发明与传统集成电路制造技术相兼容,工艺简单,成本代价小。
Description
技术领域
本发明属于超大规模集成电路制造技术领域,涉及一种低功耗鳍式场效应晶体管及其制备方法。
背景技术
当半导体器件进入22nm技术代后,鳍式场效应晶体管(FinFET)是三维多栅器件(Multi-gate MOSFET,MuGFET)的代表,其具有出众的抑制短沟效应能力和高集成密度,其制备工艺与传统CMOS工艺兼容,目前已成为半导体器件的主流。但是,在向更小尺寸技术节点迈进时,三维多栅器件的深体区由于远离顶栅控制,会出现较大的泄漏电流,增加器件的静态功耗。
为了克服这个问题,通常采用减薄Fin宽度的方法来增加两个侧壁栅对深体区的静电控制能力,同时对Fin进行掺杂以减少泄漏电流。但是若想通过刻蚀的方法形成更薄且大高宽比的Fin,其本身对刻蚀工艺提出了很大的挑战,且刻蚀形成超薄的Fin侧壁会有很大的边缘粗糙度,造成器件特性一致性的退化;另外,为了抑制深体区漏电而对Fin进行掺杂不仅会引起沟道迁移率退化,更会引入较大的随机掺杂涨落(RDF),这些都限制了多栅器件在低功耗领域的应用。
发明内容
针对以上问题,本发明提供了一种形成鳍型隔离结构以阻断深体区泄漏通路的低功耗鳍式场效应晶体管及其制备方法,以改善现有的公知技术。
本发明的一个目的在于提供一种低功耗鳍式场效应晶体管的制备方法,该方法包括以下步骤:
A.提供一半导体衬底,定义器件的有源区,形成器件之间的隔离;
B.形成用于阻断Fin深体区泄漏通路的鳍型隔离条;
B1.淀积一层氧化硅作为掩膜层1;
B2.通过光刻技术定义鳍型隔离条的图形窗口;
B3.利用光刻胶为掩蔽,各向异性刻蚀掩膜层1和有源区,形成鳍型窄槽;
B4.去胶;
B5.通过热氧化工艺的处理,高深宽比间隙的鳍型窄槽将由于氧化物的生长而被填充,
形成鳍型隔离条,而掩膜层1的图形窗口仍然存在;
C.形成顶部沟道层;
C1.利用湿法腐蚀工艺漂洗掩膜层1,掩膜层1的图形窗口会因被各向同性腐蚀而扩大,扩大后的窗口(沟道区图形窗口)宽度与鳍型隔离条宽度之差即为器件的侧壁沟道层厚度;
C2.淀积一层沟道材料,沟道区图形窗口被沟道材料填充;
C3.通过化学机械抛光去除淀积超出掩膜层1上表面的沟道材料,实现平坦化;
C4.通过湿法腐蚀工艺回漂沟道区图形窗口内的沟道材料,沟道区图形窗口内剩余的沟
道材料厚度即为器件顶部沟道层的厚度;
D.形成器件的沟道区和源漏区;
D1.淀积一层介质材料作为掩膜层2,沟道区图形窗口被掩膜层2介质材料填充;
D2.通过化学机械抛光去除淀积超出掩膜层1上表面的掩膜层2介质材料,实现平坦化;
D3.通过湿法腐蚀工艺,大面积去除掩膜层1,露出有源区表面;
D4.通过光刻技术定义器件的源漏图形窗口;
D5.以光刻胶和掩膜层2为掩蔽,各向异性刻蚀有源区,形成源漏区和沟道区,源漏区为单晶有源岛,沟道区由内部的鳍型隔离条、侧壁的两个单晶有源层、顶部沟道层共同组成,器件工作时,沟道载流子在侧壁的两个单晶有源层、顶部沟道层中进行输运;
D6.去胶;
E.源漏注入和制备栅电极;
E1.通过离子注入技术对源漏进行重掺杂,并激活退火;
E2.去除掩膜层2;
E3.形成一层栅电极层;
E4.通过光刻技术定义栅电极的图形;
E5.以光刻胶为掩蔽,各向异性刻蚀栅电极层,形成跨过沟道区的栅线条和栅引出区,栅线条覆盖在两个侧壁单晶有源层和顶部沟道层;
E6.去胶;
F.形成各端的金属接触;
F1.淀积层间介质;
F2.通过化学机械抛光实现平坦化;
F3.通过光刻技术定义源、漏、栅各端的接触孔;
F4.各向异性刻蚀层间介质,露出栅引出区和源、漏区的上表面;
F5.去胶;
F6.在各接触孔中填充金属Metal 0;
F7.通过对金属Metal 0进行化学机械平坦化,实现器件之间的导电层分离,达到器件隔离的效果;
G.后续按已公开的后端工艺完成器件集成。
进一步地,A中所述半导体衬底,包括体硅衬底,SOI衬底,体锗衬底,GOI衬底等;
进一步地,A中所述隔离,对于体衬底(体硅、体锗等),可使用阱隔离加浅槽隔离(Shallow Trench Isolation,STI);对于SOI、GOI等衬底,可仅使用浅槽隔离或岛隔离;
进一步地,B、E中所述光刻为电子束光刻或193nm浸没式光刻等能形成纳米尺度线条的先进光刻技术;
进一步地,B中所述热氧化工艺可以采用干氧氧化、湿氧氧化、氢氧合成氧化等;
进一步地,C、D中所述对于氧化硅掩膜层1的湿法腐蚀,其腐蚀液可以采用HF:H2O=1:40,腐蚀时间根据所需要的侧壁沟道层厚度决定;
进一步地,C、D中所述淀积沟道材料和掩膜层2的方法要求具有较好的保型性和间隙填充能力,优选低压化学气相淀积(Low Pressure Chemical Vapor Deposition,LPCVD)和原子层淀积(Atomic Layer Deposition,ALD);
进一步地,C中所述淀积的沟道材料,对于硅基衬底(体硅衬底,SOI衬底),其材料可以是多晶硅,对于锗基衬底(体锗衬底,GOI衬底),其材料可以是多晶锗;
进一步地,D中所述的掩膜层2的介质材料,要求与掩膜层1不同,且其对掩膜层1的各项同性腐蚀速率大于5:1,保证在去除掩膜层1时不损伤掩膜层2,例如可采用氮化硅,其去除方法可以采用浓磷酸溶液,温度为120-200℃;
进一步地,E中退火方式采用快速热退火(Rapid Thermal Annealing)、尖峰退火(Spike Annealing)、闪耀退火(Flash Annealing)和激光退火(Laser Annealing)中的一种。
进一步地,E中所述栅电极层,当衬底是硅基衬底时,可以是栅氧化层搭配多晶硅栅形成栅电极层,此时采用干氧氧化制备栅氧化层,采用LPCVD制备多晶硅栅;也可以是高K栅介质搭配金属栅形成栅电极层,此时采用ALD制备高K栅介质,采用PVD制备金属栅;衬底为锗基衬底时,只能用高K栅介质搭配金属栅形成栅电极层,此时采用ALD制备高K栅介质,采用PVD制备金属栅;
进一步地,B、D、E和F中各向异性刻蚀采用如反应离子刻蚀(Reactive IonEtching,RIE)或电感耦合等离子体(Inductively Coupled Plasma,ICP)等。
进一步地,F中所述作为导电层的填充金属Metal 0,要求具备低的电阻率以及通孔填充能力,可选择W、Cu、Al、Ti、Pt及其复合金属叠层。
进一步地,F中填充金属采用蒸发、溅射、电镀和化学气相淀积(Chemical VaporDeposition,CVD)中的一种。
本发明的另一个目的在于提供一种低功耗鳍式场效应晶体管。
本发明的低功耗鳍式场效应晶体管包括:半导体衬底、器件隔离、有源区、鳍型隔离条、沟道层、源区、漏区、栅电极层、层间介质、接触孔、Metal 0;其中,在半导体衬底上形成有源区和器件隔离;在有源区的部分表面上形成源区和漏区以及连接二者的鳍型隔离条;在鳍型隔离条的两个侧壁和上表面覆盖沟道层,沟道层同时也与源区和漏区连接;在器件隔离的部分表面上形成栅电极层,栅电极层包括栅线条和栅引出区,栅线条覆盖部分沟道层的两个侧壁和上表面,栅引出区连接栅线条;层间介质覆盖源区、漏区、沟道层、栅电极层和除此之外的有源区和器件隔离;在层间介质中形成接触孔,暴露出部分源区、漏区和栅引出区的上表面;在接触孔中填充金属Metal 0。
本发明的优点和积极效果如下:
1)本发明可以制备侧壁沟道层厚度和顶部沟道层厚度均在10nm以下的超薄沟道,沟道厚度的减薄会提供更好的栅控能力,有利于器件沟长的进一步缩小;
2)本发明在传统的鳍型沟道基础上,在远离顶栅控制的深体区形成了鳍型隔离条,这根隔离条可以阻断深体区的泄露通路,有效地提高了器件的短沟道效应控制能力,减小了静态功耗;
3)本发明提出的形成深体区鳍型隔离条的沟道结构,由于本身具备更优异的短沟道效应控制能力和更小的泄露电流,因此与传统的鳍型场效应晶体管相比,不需要对沟道进行高浓度掺杂以抑制漏电通路,避免了随机掺杂涨落对器件性能的影响;
4)本发明制备的器件源漏区是单晶有源岛,具有较小的源漏串联电阻,与传统的使用抬升源漏结构的鳍型场效应晶体管相比,不需要外延工艺制备抬升源漏即可获得较高的开态电流;
5)完全和与传统集成电路制造技术相兼容,工艺简单,成本代价小。
附图说明
图1-15为SOI衬底上制备带鳍型隔离结构的低功耗N型鳍式场效应晶体管的各关节工艺的示意图。各图中,(a)为俯视图,(b)为(a)中沿A-A’的剖面图,(c)为(a)中沿B-B’的剖面图。
其中:
图1在SOI衬底上形成器件有源区;
图2形成浅槽隔离;
图3淀积氧化硅掩膜层1,光刻并刻蚀形成鳍型窄槽;
图4鳍型窄槽被热生长的氧化硅填充,形成鳍型隔离条;
图5氢氟酸溶液漂洗掩膜层1,定义沟道区图形窗口;
图6淀积多晶硅,沟道区图形窗口被填满,平坦化;
图7HNA溶液回漂窗口内的多晶硅,定义顶部多晶硅沟道的厚度;
图8淀积氮化硅,沟道区图形窗口被填满,形成掩膜层2,平坦化;
图9大面积去除掩膜层1,露出有源区表面;
图10光刻定义源漏,以光刻胶和掩膜层2为掩蔽,各向异性刻蚀有源区;
图11去除掩膜层2,得到器件的源漏和连接源漏的沟道;
图12热氧化形成栅氧化层;
图13淀积多晶硅,离子注入调节多晶硅功函数,光刻并刻蚀形成多晶硅栅;
图14淀积二氧化硅作为层间介质,平坦化;
图15光刻并刻蚀形成各端接触孔,填充金属钨,平坦化;
图16为图1~图15的图例。
具体实施方式
下面结合附图和具体实例对本发明进行详细说明。
根据下列步骤可以实现SOI衬底上制备带鳍型隔离结构的低功耗N型鳍式场效应晶体管:
1)在P型(100)SOI衬底上将利用HNA溶液将顶层硅膜减薄至250nm,通过光刻、RIE刻蚀形成器件的有源区,去胶,如图1所示;
2)LPCVD SiO2 300nm,通过化学机械抛光进行表面平坦化,露出有源区的上表面,形成STI,如图2所示;
3)LPCVD 200nm氧化硅作为掩膜层1,通过电子束光刻定义长100nm,宽30nm的鳍型隔离条的图形窗口,利用光刻胶为掩蔽,各向异性刻蚀掩膜层1和有源区,形成鳍型窄槽,窄槽内露出衬底埋氧层上表面,去胶,如图3所示;
4)在925℃下进行干氧氧化,高深宽比间隙的鳍型窄槽将由于氧化硅的生长而被填充,形成长100nm,宽45nm(热氧化工艺消耗鳍型窄槽侧壁的硅)的鳍型隔离条,而掩膜层1的图形窗口仍然存在,如图4所示;
5)利用HF:H2O=1:40湿法腐蚀掩膜层25s,掩膜层1的图形窗口会因被各向同性腐蚀而各方向扩大25nm,扩大后的窗口(沟道区图形窗口)宽度与鳍型隔离条宽度之差即为器件的侧壁沟道层厚度,为10nm,如图5所示;
6)LPCVD 300nm多晶硅作为沟道材料,沟道区图形窗口被多晶硅填充,通过化学机械抛光去除淀积超出掩膜层1上表面的多晶硅,实现平坦化,如图6所示;
7)通过HNA溶液回漂沟道区图形窗口内的多晶硅,使沟道区图形窗口内剩余多晶硅10nm,即为器件顶部沟道层的厚度,如图7所示;
8)LPCVD 300nm氮化硅作为掩膜层2,沟道区图形窗口被氮化硅填充,通过化学机械抛光去除淀积超出掩膜层1上表面的氮化硅,实现平坦化,如图8所示;
9)利用HF:H2O=1:40溶液大面积去除氧化硅掩膜层1,漂洗时间200s,露出有源区硅表面,如图9所示;
10)通过光刻技术定义器件的源漏图形窗口,以光刻胶和掩膜层2为掩蔽,ICP刻蚀有源区250nm,露出有源层下方的埋氧层,去胶,形成源漏区和沟道区,源漏区为单晶硅岛,沟道区由内部的鳍型隔离条、侧壁沟道厚为10nm的两个单晶硅层、顶部沟道厚为10nm的多晶硅层共同组成,器件工作时,沟道载流子在侧壁的两个单晶硅层、顶部多晶硅层中进行输运,如图10所示;
11)As+注入对源漏进行重掺杂,分三次注入,注入能量分别为30KeV,45KeV,65KeV,注入剂量5E15cm-2,并通过RTA退火1000℃,10s,激活杂质同时使源漏杂质扩散进入源漏延伸区;
12)利用浓磷酸溶液去除氮化硅掩膜层2,腐蚀温度为170℃,如图11所示;
13)干氧氧化形成栅氧化层2nm,如图12所示;
14)LPCVD 250nm多晶硅,As+注入调节多晶硅功函数,注入能量50KeV,注入剂量1E15cm-2,通过电子束光刻定义栅线条,以光刻胶为掩蔽,ICP刻蚀多晶硅250nm,去胶,形成跨过沟道区的栅线条和栅引出区,栅线条宽度为22nm,即器件的栅长为22nm,如图13所示;
15)通过PECVD淀积400nm SiO2作为层间介质,并通过化学机械抛光实现平坦化,如图14所示;
16)通过光刻、ICP刻蚀形成器件栅、源、漏各端的接触孔,去胶;
17)溅射500nm金属钨,器件栅、源、漏各端的接触孔被金属钨填充;
18)通过对金属钨进行化学机械抛光,实现器件之间的导电层分离,达到器件隔离的效果,如图15所示;
19)后续按已公开的后端工艺完成器件集成。
本发明实施例并非用以限定本发明。任何熟悉本领域的技术人员,在不脱离本发明技术方案范围情况下,都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰,或修改为等同变化的等效实施例。因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰,均仍属于本发明技术方案保护的范围内。
Claims (13)
1.一种鳍式场效应晶体管的制备方法,包括以下步骤:
A.提供一半导体衬底,定义器件的有源区,形成器件之间的隔离;
B.形成用于阻断Fin深体区泄漏通路的鳍型隔离条,该步骤具体包括:
B1.淀积一层氧化硅作为第一掩膜层;
B2.通过光刻技术定义鳍型隔离条的图形窗口;
B3.利用光刻胶为掩蔽,各向异性刻蚀第一掩膜层和有源区,形成鳍型窄槽;
B4.去胶;
B5.通过热氧化工艺的处理,高深宽比间隙的鳍型窄槽被填充,形成鳍型隔离条,而第一掩膜层的图形窗口仍然存在;
C.形成顶部沟道层,该步骤具体包括:
C1.利用湿法腐蚀工艺漂洗第一掩膜层,第一掩膜层的图形窗口会因被各向同性腐蚀而扩大,扩大后的窗口宽度与鳍型隔离条宽度之差即为器件的侧壁沟道层厚度;
C2.淀积一层沟道材料,沟道区图形窗口被沟道材料填充;
C3.通过化学机械抛光去除淀积超出第一掩膜层上表面的沟道材料,实现平坦化;
C4.通过湿法腐蚀工艺回漂沟道区图形窗口内的沟道材料,沟道区图形窗口内剩余的沟道材料厚度即为器件顶部沟道层的厚度;
D.形成器件的沟道区和源漏区,该步骤具体包括:
D1.淀积一层介质材料作为第二掩膜层,沟道区图形窗口被第二掩膜层填充;
D2.通过化学机械抛光去除淀积超出第一掩膜层上表面的第二掩膜层,实现平坦化;
D3.通过湿法腐蚀工艺,大面积去除第一掩膜层,露出有源区表面;
D4.通过光刻技术定义器件的源漏图形窗口;
D5.以光刻胶和第二掩膜层为掩蔽,各向异性刻蚀有源区,形成源漏区和沟道区,源漏区为单晶有源岛,沟道区由内部的鳍型隔离条、侧壁的两个单晶有源层、顶部沟道层共同组成,器件工作时,沟道载流子在侧壁的两个单晶有源层、顶部沟道层中进行输运;
D6.去胶;
E.源漏注入和制备栅电极,该步骤具体包括:
E1.通过离子注入技术对源漏进行重掺杂,并激活退火;
E2.去除第二掩膜层;
E3.形成一层栅电极层;
E4.通过光刻技术定义栅电极的图形;
E5.以光刻胶为掩蔽,各向异性刻蚀栅电极层,形成跨过沟道区的栅线条和栅引出区,栅线条覆盖在两个侧壁单晶有源层和顶部沟道层;
E6.去胶;
F.形成各端的金属接触,该步骤具体包括:
F1.淀积层间介质;
F2.通过化学机械抛光实现平坦化;
F3.通过光刻技术定义源、漏、栅各端的接触孔;
F4.各向异性刻蚀层间介质,露出栅引出区和源、漏区的上表面;
F5.去胶;
F6.在各接触孔中填充金属Metal 0;
F7.通过对金属Metal 0进行化学机械平坦化,实现器件之间的导电层分离,达到器件隔离的效果;
G.最后进入常规后端工艺,完成器件集成。
2.如权利要求1所述的制备方法,其特征在于,步骤A中所述半导体衬底为体硅衬底、SOI衬底、体锗衬底或GOI衬底。
3.如权利要求2所述的制备方法,其特征在于,步骤A中对于体硅衬底、体锗衬底使用阱隔离加浅槽隔离;对于SOI衬底、GOI衬底使用浅槽隔离或岛隔离。
4.如权利要求1所述的制备方法,其特征在于,步骤B、E中所述光刻为电子束光刻或193nm浸没式光刻。
5.如权利要求1所述的制备方法,其特征在于,步骤B中所述热氧化工艺采用干氧氧化、湿氧氧化或氢氧合成氧化。
6.如权利要求1所述的制备方法,其特征在于,步骤C、D中所述对于第一掩膜层的湿法腐蚀,其腐蚀液采用HF:H2O=1:40。
7.如权利要求1所述的制备方法,其特征在于,步骤C中所述淀积沟道材料的制备方法为低压化学气相淀积LPCVD或原子层淀积ALD;步骤D中所述第二掩膜层的制备方法为低压化学气相淀积LPCVD或原子层淀积ALD。
8.如权利要求1所述的制备方法,其特征在于,步骤D中所述第二掩膜层材料对第一掩膜层材料的各项同性腐蚀速率大于5:1。
9.如权利要求1所述的制备方法,其特征在于,步骤E中退火方式采用快速热退火,所述快速热退火为尖峰退火、闪耀退火和激光退火中的一种。
10.如权利要求1所述的制备方法,其特征在于,步骤E中,当衬底是硅基衬底时,采用二氧化硅栅介质和多晶硅栅形成栅电极层;或采用高K栅介质和金属栅形成栅电极层;当衬底为锗基衬底时,只能采用高K栅介质和金属栅形成栅电极层。
11.如权利要求1所述的制备方法,其特征在于,步骤B、D、E和F中各向异性刻蚀采用反应离子刻蚀RIE或电感耦合等离子体ICP。
12.如权利要求1所述的制备方法,其特征在于,步骤F中所述作为导电层的填充金属Metal 0为W、Cu、Al、Ti、Pt及其复合金属叠层。
13.如权利要求1所述的制备方法,其特征在于,步骤F中填充金属采用蒸发、溅射、电镀和化学气相淀积CVD中的一种。
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