WO2023010383A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2023010383A1
WO2023010383A1 PCT/CN2021/110743 CN2021110743W WO2023010383A1 WO 2023010383 A1 WO2023010383 A1 WO 2023010383A1 CN 2021110743 W CN2021110743 W CN 2021110743W WO 2023010383 A1 WO2023010383 A1 WO 2023010383A1
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Prior art keywords
layer
forming
channel
isolation
trench
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PCT/CN2021/110743
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English (en)
French (fr)
Inventor
苏博
吴汉洙
庾亚伯拉罕
张海洋
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中芯国际集成电路制造(上海)有限公司
中芯国际集成电路制造(北京)有限公司
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Application filed by 中芯国际集成电路制造(上海)有限公司, 中芯国际集成电路制造(北京)有限公司 filed Critical 中芯国际集成电路制造(上海)有限公司
Priority to PCT/CN2021/110743 priority Critical patent/WO2023010383A1/zh
Priority to CN202180099965.9A priority patent/CN117652014A/zh
Publication of WO2023010383A1 publication Critical patent/WO2023010383A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
  • MOSFET Field-Effect Transistor
  • the channel length of the device shortens, the distance between the source and the drain of the device also shortens, so the ability of the gate structure to control the channel becomes worse, and the gate voltage pinch-off (pinch off) channel is becoming more and more difficult, making the subthreshold leakage (subthreshold leakage) phenomenon, the so-called short-channel effects (SCE: short-channel effects) are more likely to occur.
  • SCE short-channel effects
  • the semiconductor process has gradually begun to transition from planar transistors to three-dimensional transistors with higher power efficiency, such as Gate-all-around (GAA) transistors.
  • GAA Gate-all-around
  • the gate surrounds the area where the channel is located.
  • the gate of a fully surrounded metal gate transistor has a stronger ability to control the channel and can better suppress short channels. road effect.
  • the problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.
  • an embodiment of the present invention provides a semiconductor structure, including: a substrate including a channel region, and the normal direction of the surface of the substrate is a vertical direction; an isolation layer is located on the substrate of the channel region; A channel layer structure, located in the channel region and suspended above the isolation layer, in the longitudinal direction, the channel layer structure includes one or more spaced channel layers; a gate structure, located in the On the substrate and across the channel layer structure, the gate structure includes a gate dielectric layer surrounding the channel layer along the extending direction of the gate structure, and a gate electrode layer located on the gate dielectric layer, In the channel region, the gate structure is located on the isolation layer; source-drain doped layers are located on the substrates on both sides of the gate structure, in the extending direction of the channel layer structure, The source-drain doped layer is in contact with the end of the channel layer structure and the end of the isolation layer.
  • an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, a first sacrificial layer is formed on the substrate, a channel structure is formed on the first sacrificial layer, and the trench
  • the channel structure includes one or more stacked channel stacks, the channel stacks include a second sacrificial layer and a channel layer on the second sacrificial layer, and the substrate is further formed with A dummy gate structure of the channel structure, the dummy gate structure covers part of the sidewall and part of the top of the channel structure, wherein the etch resistance of the first sacrificial layer is lower than the etch resistance of the second sacrificial layer ; removing the channel structure and the first sacrificial layer on both sides of the dummy gate structure to form a first trench penetrating through the channel structure and the first sacrificial layer; removing the channel structure through the first trench The first sacrificial layer at the bottom, forming a second trench
  • the semiconductor structure provided by the embodiment of the present invention includes an isolation layer on the substrate at the bottom of the channel layer structure, and the channel region , the gate structure is located on the isolation layer, and the isolation layer effectively isolates the contact between the gate structure and the base of the channel region, thereby reducing the gate structure in the channel region.
  • the embodiment of the present invention can avoid the leakage caused by ion implantation of the substrate
  • the source-drain doped layer is located on the substrate on both sides of the gate structure and is in contact with the end of the isolation layer, then the source-drain doped layer adjacent to the While the impurity layer is effectively isolated by the isolation layer, the source-drain doped layer is in contact with the substrate, which is beneficial to increase the growth rate of the source-drain doped layer and enhance the growth of the source-drain doped layer Quality, reducing defects generated during the growth process, all of the above are beneficial to improve the working performance of the semiconductor structure.
  • a first sacrificial layer is formed on the substrate, the first sacrificial layer is removed through the first groove, and a layer corresponding to the first groove is formed at the bottom of the channel structure.
  • the grooves are connected to the second groove, and the isolation layer is formed in the second groove, and the isolation layer is formed by first forming the first sacrificial layer to occupy a space position for the isolation layer, and then removing the first sacrificial layer.
  • the embodiment of the present invention can avoid the increase of parasitic capacitance caused by ion implantation of the substrate.
  • 1 to 2 are structural schematic diagrams corresponding to each step in a method for forming a semiconductor structure.
  • 3 to 4 are structural schematic diagrams corresponding to an embodiment of the semiconductor structure of the present invention.
  • 5 to 19 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.
  • 20 to 21 are structural schematic diagrams corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention.
  • 1 to 2 are structural schematic diagrams corresponding to each step in a method for forming a semiconductor structure.
  • a substrate 10 is provided, ion implantation is performed on the top of the substrate 10, and an isolation region (not shown) is formed in the substrate 10; after the isolation region is formed, on the substrate 10 where the isolation region is located forming a channel structure 20, the channel structure 20 comprising one or more channel stacks 21, wherein the channel stack 21 comprises a sacrificial layer 22 and a channel layer 23 located on the sacrificial layer 22; A dummy gate structure 40 spanning the channel structure 20 is formed on the substrate 10 , the dummy gate structure 40 covers part of the sidewall and part of the top of the channel structure 20 .
  • the dummy gate structure 40 is removed to form a gate opening (not shown); the sacrificial layer 22 is removed through the gate opening to expose each surface of the channel layer 23; the sacrificial layer is removed After layer 22, a gate structure 70 surrounding and covering the channel layer 23 is formed in the gate opening.
  • the gate structure 70 is also in contact with the top of the substrate 10 , therefore, in order to isolate the substrate 10 from the gate structure 70 and reduce the leakage current of the semiconductor structure , before forming the channel structure 20, an isolation region is formed, so that an isolation effect is provided between the substrate 10 and the subsequently formed gate structure. Moreover, in order to ensure the isolation effect of the isolation region, a higher concentration of ions is usually implanted on the top of the substrate 10 .
  • an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, a first sacrificial layer is formed on the substrate, a channel structure is formed on the first sacrificial layer, and the The channel structure includes one or more stacked channel stacks, the channel stacks include a second sacrificial layer and a channel layer on the second sacrificial layer, and the substrate is further formed with straddling The dummy gate structure of the channel structure, the dummy gate structure covers part of the sidewall and part of the top of the channel structure, wherein the etch resistance of the first sacrificial layer is lower than that of the second sacrificial layer etching degree; remove the channel structure and the first sacrificial layer on both sides of the dummy gate structure, and form a first trench penetrating through the channel structure and the first sacrificial layer; remove the trench through the first trench A first sacrificial layer at the bottom of the channel structure
  • a first sacrificial layer is formed on the substrate, the first sacrificial layer is removed through the first groove, and a layer corresponding to the first groove is formed at the bottom of the channel structure.
  • the grooves are connected to the second groove, and the isolation layer is formed in the second groove, and the isolation layer is formed by first forming the first sacrificial layer to occupy a space position for the isolation layer, and then removing the first sacrificial layer.
  • the embodiment of the present invention can avoid the increase of parasitic capacitance caused by ion implantation of the substrate.
  • FIG. 3 to 4 are structural schematic diagrams corresponding to an embodiment of the semiconductor structure of the present invention, FIG. 3 is a top view of the gate structure and source-drain doped layers, and FIG. 4 is a cross-sectional view of FIG. 3 based on the AA direction.
  • the semiconductor structure includes: a substrate 101 including a channel region 101c, the normal direction of the surface of the substrate 101 is vertical (as shown in the Z direction in FIG. 4 ); an isolation layer 511 is located on the substrate of the channel region 101c 101; a channel layer structure 201, located in the channel region 101c and suspended above the isolation layer 511, in the longitudinal direction, the channel layer structure 201 includes one or more spaced channel layers 231:
  • the gate structure 701 is located on the substrate 101 and crosses the channel layer structure 201, the gate structure 701 includes a gate dielectric surrounding the channel layer 231 along the extending direction of the gate structure 701 layer 711, and the gate electrode layer 721 located on the gate dielectric layer 711, in the channel region 101c, the gate structure 701 is located on the isolation layer 511;
  • the source-drain doped layer 601 is located on the On the substrate 101 on both sides of the gate structure 701, in the extending direction of the channel layer structure 201, the source-drain doped layer 601 and the end
  • the substrate 101 provides a process operation basis for the formation process of the semiconductor structure.
  • the semiconductor structure includes a gate-all-around (gate-all-around, GAA) transistor and a fork-shaped gate (Forksheet) transistor.
  • the base 101 includes a substrate (not shown).
  • the material of the substrate is silicon.
  • the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, and the substrate can also be a silicon-on-insulator substrate or a silicon-on-insulator substrate.
  • Other types of substrates such as germanium substrates.
  • the material of the substrate may be a material suitable for process requirements or easy to integrate.
  • the base 101 may further include: fins (not shown), located on the substrate.
  • the substrate 101 includes a channel region 101c, and the channel layer structure 201 of the channel region 101c is used as a channel of a transistor.
  • the semiconductor structure further includes: a shallow trench isolation structure 111 located in the substrate 101 .
  • the shallow trench isolation structure 111 is used to realize isolation between different devices. For example, in a CMOS manufacturing process, the shallow trench isolation structure 111 is usually formed between an NMOS transistor and a PMOS transistor.
  • the shallow trench isolation structure 111 is located on the exposed substrate of the fin and covers the sidewall of the fin.
  • the material of the shallow trench isolation structure 111 is insulating material.
  • the material of the shallow trench isolation structure 111 is silicon oxide.
  • the isolation layer 511 is used to isolate the gate structure 701 from the base 101 of the channel region 101c.
  • the gate structure 701 in the channel region 101c, is located on the isolation layer 511, and the isolation layer 511 effectively isolates the gate structure 701 from the channel.
  • the thickness d2 of the isolation layer 511 should not be too large, nor should it be too small. If the thickness d2 of the isolation layer 511 is too large, it is easy to cause unnecessary process waste, and, before forming the isolation layer 511, the first sacrificial layer is formed to occupy a space for the isolation layer 511, and then the first sacrificial layer is removed.
  • the isolation layer 511 is formed after the first sacrificial layer is removed, therefore, if the thickness d2 of the isolation layer 511 is too large, the thickness of the first sacrificial layer is also too large, which will easily cause unnecessary process waste , also increases the process difficulty of removing the first sacrificial layer; if the thickness d2 of the isolation layer 511 is too small, it is easy to affect the isolation performance of the isolation layer 511, so that it is difficult to better integrate the gate structure 701 and The base 101 of the channel region 101c is completely isolated, affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness d2 of the isolation layer 511 is 5 nm to 15 nm.
  • the material of the isolation layer 511 includes a dielectric material that can isolate the gate structure 701 and the base 101 of the channel region 101c, and the process of the dielectric material The compatibility is high, thereby reducing the influence of the isolation layer 511 on the process.
  • the material of the isolation layer 511 includes one or more of silicon oxide and silicon nitride, and the silicon oxide and silicon nitride are beneficial to better isolate the gate structure 701 from the channel.
  • the channel layer structure 201 includes one or more channel layers 231 spaced apart in the longitudinal direction, and the channel layers 231 are used as channels of the semiconductor structure.
  • the material of the channel layer 231 includes silicon, germanium, silicon germanium or III-V semiconductor materials.
  • the material of the channel layer 231 is silicon.
  • the material of the channel layer is determined according to the type and performance of the transistor.
  • the materials of the channel layer 231 and the substrate are the same, and in other embodiments, the materials of the channel layer and the substrate may also be different.
  • the gate structure 701 is used to control the on and off of the channel of the transistor.
  • the gate structure 701 surrounds and covers the channel layer 231, therefore, the top, bottom and sidewalls of the channel layer 231 can all be used as channels, increasing the channel layer 231 used as a channel. area, thereby increasing the operating current of the semiconductor structure.
  • the gate dielectric layer 711 is used to isolate the gate electrode layer 721 from the channel layer 231 , and the gate electrode layer 721 from the base 101 of the channel region 101c.
  • the material of the gate dielectric layer 711 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.
  • the gate dielectric layer 711 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material.
  • the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide.
  • the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3 and the like.
  • the gate dielectric layer 711 may further include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the channel layer 231 .
  • the material of the gate oxide layer may be silicon oxide.
  • the gate structure 701 is a metal gate structure, therefore, the material of the gate electrode layer 721 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN and TiAlC. Various.
  • the gate electrode layer 721 includes a work function layer (not shown), and an electrode layer (not shown) located on the work function layer.
  • the work function layer is used to adjust the threshold voltage of the transistor
  • the electrode layer is used to extract the electricity of the metal gate structure.
  • the gate electrode layer may only include a work function layer.
  • the gate structure may also be a polysilicon gate structure.
  • the semiconductor structure further includes: a gate spacer 411 covering the sidewall of the gate structure 701 .
  • the gate spacer 411 is used to protect the sidewall of the gate structure 701 .
  • the gate spacer 411 can be a single-layer structure or a stacked structure, and the material of the gate spacer 411 includes silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon nitride oxide , one or more of boron nitride and carbon boron nitride.
  • the gate spacer 411 is a single-layer structure, and the material of the gate spacer 411 is silicon nitride.
  • the distance d1 between the gate spacers 411 on opposite sidewalls of adjacent gate structures 701 is greater than the thickness d2 of the isolation layer 511 .
  • an isolation material layer is deposited from the gap between the gate spacers 411 on the opposite side walls of the adjacent gate structure 701, so that the isolation material layer is filled in the trench
  • the isolation material layer will also be deposited on the sidewall of the gap between the gate sidewalls 411 on the opposite sidewalls of the adjacent gate structure 701
  • there is a gap between the isolation material layers on the sidewall of the void therefore, between the gate sidewall 411 on the opposite sidewall of the adjacent gate structure 701
  • the distance d1 between them is greater than the thickness d2 of the isolation layer 511 .
  • the source-drain doped layer 601 is used as a source region or a drain region of a transistor. Specifically, the doping type of the source-drain doping layer 601 is the same as the channel conductivity type of the corresponding transistor.
  • the source-drain doped layer 601 is located on the substrate 101 on both sides of the gate structure 701, and in the extending direction of the channel layer structure 201, the source-drain doped layer 601 and The ends of the isolation layer 511 are in contact, and the adjacent doped source and drain layers 601 are effectively isolated by the isolation layer 511.
  • the doped source and drain layers 601 are formed by an epitaxial growth process.
  • the source-drain doped layer 601 is in contact with the substrate 101, which is conducive to increasing the growth rate of the source-drain doped layer 601, improving the growth quality of the source-drain doped layer 601, and reducing defects generated during the growth process. .
  • the doping type of the source-drain doped layer 601 is the same as the channel conductivity type of the corresponding transistor, specifically, when the substrate 101 is used to form an NMOS transistor, the doping type in the source-drain doped layer 601
  • the hetero ions are N-type ions, and the N-type ions include P ions, As ions or Sb ions; when the substrate 101 is used to form a PMOS transistor, the dopant ions in the source-drain doped layer 601 are P-type ions ions, the P-type ions include B ions, Ga ions or In ions.
  • the material of the source-drain doped layer 601 is Si or SiC doped with N-type ions, and the source-drain doped layer 601 is the channel of the NMOS transistor.
  • the channel region provides tensile stress, which is conducive to improving the carrier mobility of the NMOS transistor;
  • the material of the source-drain doped layer 601 is Si doped with P-type ions or SiGe, the source-drain doped layer 601 provides a compressive stress effect for the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor.
  • the semiconductor structure further includes: an inner wall 281, in the longitudinal direction, the inner wall 281 is located between adjacent channel layers 231, and the bottom channel layer 231 and the isolation layer 511 Between, and in the extending direction of the channel layer structure 201 , the inner wall 281 is located between the gate structure 701 and the source-drain doped layer 601 .
  • the inner wall 281 functions to isolate the gate structure 701 from the source-drain doped layer 601 , so as to reduce the parasitic capacitance between the gate structure 701 and the source-drain doped layer 601 .
  • the material of the inner wall 281 is insulating material.
  • the material of the inner wall 281 includes silicon nitride and silicon oxycarbide.
  • 5 to 19 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.
  • FIG. 5 is a top view of the dummy gate structure and fins
  • FIG. 6 is a cross-sectional view of FIG.
  • a channel structure 200 is formed on the first sacrificial layer 300
  • the channel structure 200 includes one or more stacked channel stacks 210
  • the channel stack 210 includes a second sacrificial layer 220 and a Channel layer 230 on the sacrificial layer 220
  • a dummy gate structure 400 across the channel structure 200 is also formed on the substrate 100
  • the dummy gate structure 400 covers part of the sidewall of the channel structure 200 and part of the top, wherein the etch resistance of the first sacrificial layer 300 is less than the etch resistance of the second sacrificial layer 220 .
  • the substrate 100 provides a process operation basis for the formation process of the semiconductor structure.
  • the semiconductor structure includes a gate-all-around (gate-all-around, GAA) transistor and a fork-shaped gate (Forksheet) transistor.
  • the base 100 includes a substrate (not shown).
  • the material of the substrate is silicon.
  • the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, and the substrate can also be a silicon-on-insulator substrate or a silicon-on-insulator substrate.
  • Other types of substrates such as germanium substrates.
  • the material of the substrate may be a material suitable for process requirements or easy to integrate.
  • the base 100 may further include: fins (not shown) located on the substrate.
  • FIG. 6(a) shows a schematic diagram of the first device region
  • FIG. 6(b) shows a schematic diagram of the second device region.
  • the substrate 100 in the step of providing the substrate 100, includes A first device region 100P for forming a first transistor (as shown in FIG. 6( a )) and a second device region 100N for forming a second transistor (as shown in FIG. 6( b )).
  • the channel conductivity types of the first transistor and the second transistor are different, and the channel conductivity type includes N type or P type.
  • the first transistor is a PMOS transistor
  • the second transistor is an NMOS transistor.
  • the channel conductivity types of the first transistor and the second transistor may also be the same.
  • the substrate 100 further includes a shallow trench isolation structure 110 .
  • the shallow trench isolation structure 110 is used to realize isolation between different devices.
  • the shallow trench isolation structure 110 is usually formed between an NMOS transistor and a PMOS transistor.
  • the shallow trench isolation structure 110 is located on the substrate where the fins are exposed, and covers the sidewalls of the fins.
  • the material of the shallow trench isolation structure 110 is insulating material.
  • the material of the shallow trench isolation structure 110 is silicon oxide.
  • the channel layer 230 in the channel structure 200 is used as a channel of the semiconductor structure, and the sacrificial layer 220 is used to provide a process basis for the subsequent implementation of the floating setting of the channel layer 230, and is also used for the subsequent formation
  • the gate structure occupies a spatial position. In the subsequent process, the sacrificial layer 220 is removed, so that the channel layer 230 is suspended, and a gate structure is formed between the channel layer 230 and the substrate 100 , and between adjacent channel layers 230 .
  • the surface covered by the gate structure in the channel layer 230 is used as a channel.
  • the top, bottom and side walls of the channel layer 230 can all be used as channels, which increases the channel layer 230.
  • the area used as a channel in the middle increases the operating current of the semiconductor structure.
  • the material of the channel layer 230 includes silicon, germanium, silicon germanium or III-V group semiconductor materials.
  • the material of the channel layer 230 is silicon.
  • the material of the channel layer is determined according to the type and performance of the transistor.
  • the materials of the channel layer 230 and the substrate are the same, and in other embodiments, the materials of the channel layer and the substrate may also be different.
  • the material of the second sacrificial layer 220 includes silicon germanium.
  • the silicon germanium and silicon can form a larger etching selectivity ratio, which is beneficial to the subsequent removal of the second sacrificial layer 220 and reduces damage to the channel layer 230 .
  • the second sacrificial layer can be selected from a suitable material having an etching selectivity ratio with the channel layer, so that when the second sacrificial layer is subsequently removed, the damage to the channel layer can be reduced. damage.
  • the first sacrificial layer 300 occupies a spatial position for subsequent formation of an isolation layer.
  • the thickness d2 of the first sacrificial layer 300 should neither be too large nor too small. If the thickness d2 of the first sacrificial layer 300 is too large, it is easy to cause unnecessary process waste, and the first sacrificial layer 300 occupies a space for the subsequent formation of an isolation layer, and then the first sacrificial layer 300 is removed. The isolation layer is formed after removing the first sacrificial layer 300.
  • the thickness d2 of the first sacrificial layer 300 is 5 nm to 15 nm.
  • the etch resistance of the first sacrificial layer 300 is lower than that of the second sacrificial layer 220, which facilitates the subsequent removal of the first sacrificial layer 300 and the subsequent removal of the first sacrificial layer 220. layer 300, the damage to the second sacrificial layer 220 is reduced.
  • the etching selectivity ratio of the first sacrificial layer 300 and the second sacrificial layer 220 should not be too small. If the etching selectivity ratio of the first sacrificial layer 300 and the second sacrificial layer 220 is too small, then in the subsequent process of removing the first sacrificial layer 300, it is easy to cause damage to the second sacrificial layer 220, even If the second sacrificial layer 220 is removed together, in the step of forming the isolation layer, an isolation layer is also filled between the channel layers 230 adjacent in the vertical direction, thereby affecting the adjacent channel layers 230 in the vertical direction. The formation of the gate structure between the channel layers 230 affects the performance of the semiconductor structure. For this reason, the etching selectivity ratio of the first sacrificial layer 300 and the second sacrificial layer 220 is greater than 10.
  • the material of the first sacrificial layer 300 includes a semiconductor material, which is beneficial to the epitaxial growth of the first sacrificial layer 300 on the substrate 100, and is also beneficial to the channel structure 200 on the Epitaxial growth on the first sacrificial layer 300, thereby improving the process compatibility of the first sacrificial layer 300, so that the first sacrificial layer 300 and the channel structure 200 can be formed on the substrate by using an epitaxial growth process in the same process Grow on 100.
  • the material of the first sacrificial layer 300 includes Si1-yGey
  • the material of the second sacrificial layer 220 includes Si1-xGex, where x ⁇ y, that is to say, the first sacrificial layer 300
  • the molar ratio of the Ge element to the Si element in the second sacrificial layer 220 is greater than the molar ratio of the Ge element to the Si element in the second sacrificial layer 220, so that the etch resistance of the first sacrificial layer 300 is lower than that of the second sacrificial layer 220. Erosion.
  • y should not be too small. If in the material Si1-yGey of the first sacrificial layer 300, the y value is too small, the etching resistance of the first sacrificial layer 300 is too large, and the first sacrificial layer 300 is not easy to be etched. Subsequent removal of the first sacrificial layer 300 poses difficulties. Therefore, in this embodiment, in the material Si1-yGey of the first sacrificial layer 300, y ⁇ 0.4.
  • x should neither be too large nor too small. Since the channel layer 230 is obtained by epitaxial growth on the second sacrificial layer 220, if the value of x is too large in the material Si1-xGex of the second sacrificial layer 220, the second sacrificial layer 220 The concentration of the Ge element in the middle is too high, when forming the channel layer 230, the transition layer required for the transition from the material of the second sacrificial layer 220 to the material of the channel layer 230 is too thick, resulting in the formation of the The effective thickness of the channel layer 230 is too small, which affects the quality of the channel layer 230, thereby affecting the performance of the semiconductor structure; if the value of x is too small in the material Si1-xGex of the second sacrificial layer 220, If the etching resistance of the second sacrificial layer 220 is too high, the second
  • the dummy gate structure 400 is used to occupy a space position for subsequent formation of a gate structure.
  • the dummy gate structure 400 is a stacked structure, including a dummy gate oxide layer (not shown in the figure) and a dummy gate layer (not shown in the figure) covering the dummy gate oxide layer.
  • the material of the dummy gate oxide layer is silicon oxide, and the material of the dummy gate layer is polysilicon.
  • a gate spacer 410 covering the top and sidewalls of the dummy gate structure 400 is further formed on the substrate 100 .
  • the gate spacer 410 is used to protect the sidewalls of the dummy gate structure 400, thereby ensuring the formation quality of the subsequent gate structure, and in After forming the gate structure, protect the sidewall of the gate structure.
  • the gate spacer 410 can be a single-layer structure or a stacked structure, and the material of the gate spacer 410 includes silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon nitride oxide , one or more of boron nitride and carbon boron nitride.
  • the gate spacer 410 is a single-layer structure, and the material of the gate spacer 410 is silicon nitride.
  • the gate spacer 410 conformally covers the dummy gate structure 400 and the channel structure 200 .
  • the distance d1 between the gate spacers 410 on opposite sidewalls of adjacent dummy gate structures 400 is greater than the thickness d2 of the first sacrificial layer 300 .
  • the first sacrificial layer 300 is removed to form a second trench, and then an isolation material layer is deposited from the gap between the gate spacers 410 on the opposite side walls of the adjacent dummy gate structure 400, so that the isolation material layer Filling the second trench at the bottom of the trench structure 200 to form an isolation layer, but at the same time, an isolation material layer will also be deposited between the gate spacers 410 on the opposite side walls adjacent to the dummy gate structure 400 In order to better remove the isolation material layer on the side wall of the gap, there is a gap between the isolation material layers on the side wall of the gap. Therefore, on the opposite side wall of the adjacent dummy gate structure 400 The distance d1 between the gate spacers 410 is greater than the thickness d2 of the first sacrificial layer 300 .
  • the channel structure 200 and the first sacrificial layer 300 on both sides of the dummy gate structure 400 are removed to form a first trench 240 penetrating through the channel structure 200 and the first sacrificial layer 300 .
  • the first groove exposes the sidewall of the first sacrificial layer 300, in preparation for subsequent removal of the first sacrificial layer 300, and subsequently forms an isolation layer through the first groove 240, and the first groove
  • the groove 240 also provides a spatial location for the subsequent formation of source and drain doped layers.
  • the first trench 240 is formed together in the first device region 100P and the second device region 100N for forming the source-drain doped layer, compared to the first device region and the second device region Forming the first trenches respectively simplifies the process flow and improves the process efficiency.
  • the channel structure 200 and the first sacrificial layer 300 on both sides of the dummy gate structure 400 are removed by a dry etching process.
  • the dry etching process is an anisotropic dry etching process. Therefore, by selecting a dry etching process, it is beneficial to reduce damage to the substrate 100 at the bottom of the first trench 240. At the same time, The dry etching is more directional, which is beneficial to improving the topography quality and dimensional accuracy of the sidewall of the first trench 240 .
  • the gate spacers on the top of the channel structure 200 on both sides of the dummy gate structure 400 are also removed. 410 , and the gate spacer 410 on the top of the dummy gate structure 400 .
  • FIG. 8 is a top view
  • FIG. 9 is a sectional view of FIG. 8 based on the AA direction
  • FIG. 10 is a sectional view of FIG. 8 based on the BB direction
  • the channel structure 200 is removed through the first trench 240
  • the first sacrificial layer 300 at the bottom forms a second trench 250 communicating with the first trench 240 at the bottom of the channel structure 200 .
  • the second trench 250 is used to provide a space for subsequent formation of isolation layers.
  • the channel structure 200 is supported by the dummy gate structure 400, so that after the second trench 250 is formed, the channel structure 200 is suspended above the substrate 100 .
  • an isotropic etching process is used to remove the first sacrificial layer 300 .
  • the isotropic etching process is beneficial to remove the first sacrificial layer 300 cleanly.
  • the isotropic etching process includes a plasma chemical reaction group etching process or a vapor phase etching process.
  • the plasma chemical reaction group etching process may be a Certas etching process or a SiCoNi etching process
  • the vapor phase etching process may also be a Certas etching process or a SiCoNi etching process.
  • the Certas etching process or SiCoNi etching process has better isotropic properties, which is conducive to removing the first sacrificial layer 300, and the Certas etching process or SiCoNi etching process can have better etching Eclipse selection ratio.
  • an isolation layer 510 is formed in the second trench 250 .
  • the first sacrificial layer 300 By first forming the first sacrificial layer 300 to occupy a space for the isolation layer 510, and then removing the first sacrificial layer 300 to form the isolation layer 510, it is beneficial for the channel structure 200 located on the first sacrificial layer 300 growth, and the material of the first sacrificial layer 300 can be flexibly selected according to process requirements to improve the process compatibility of the first sacrificial layer 300.
  • the second sacrificial layer 220 is subsequently removed to form a gate structure
  • the The gate structure is formed on the isolation layer 510, and the isolation layer 510 effectively isolates the contact between the gate structure and the substrate 100, thereby reducing the possibility of leakage current between the gate structure and the substrate 100.
  • this embodiment can avoid the problem of increasing parasitic capacitance caused by ion implantation into the substrate 100.
  • all It is beneficial to improve the working performance of the semiconductor structure.
  • the material of the isolation layer 510 includes a dielectric material, which can isolate the gate structure and the substrate 100, and the dielectric material has high process compatibility, thereby reducing the The impact of the isolation layer 510 on the process is described.
  • the material of the isolation layer 510 includes one or more of silicon oxide and silicon nitride, and the silicon oxide and silicon nitride are beneficial to better isolate the gate structure and the substrate 100 .
  • the step of forming the isolation layer 510 in the second trench 250 includes: forming the sidewall and top covering the dummy gate structure 400, the sidewall of the trench structure 200, and The first trench 240 exposes the isolation material layer 500 on the top of the substrate 100 , and the isolation material layer 500 is also filled in the second trench 250 .
  • the isolation material layer 500 is used to form an isolation layer 510 .
  • the isolation material layer 500 is formed by an atomic layer deposition process.
  • the isolation material layer 500 formed by the atomic layer deposition process has good thickness uniformity and good step coverage (step coverage), so that the isolation material layer 500 can well cover the sidewall and top of the dummy gate structure 400 and the sidewall of the channel structure 200 while filling the second trench 250 .
  • the material of the isolation material layer 500 includes a dielectric material, and the material of the isolation material layer 500 includes one or more of silicon oxide and silicon nitride.
  • the isolation material layer 500 also covers the gate spacer 410, so that the isolation material layer 500 on the side wall of the dummy gate structure 400 is subsequently removed.
  • the gate spacer 410 can protect the sidewall of the dummy gate structure 400 , thereby ensuring the formation quality of the subsequent gate structure.
  • the distance d1 between the gate spacers 410 on the opposite sidewalls of the adjacent dummy gate structures 400 is greater than the thickness d2 of the first sacrificial layer 300, therefore, a
  • the sidewall of the trench structure 200, and the isolation material layer 500 on the top of the substrate 100 exposed by the first trench 240, the sidewall of the adjacent dummy gate structure 400 There is a gap between the isolation material layers 500 , which facilitates subsequent removal of the isolation material layer 500 adjacent to the sidewall of the dummy gate structure 400 .
  • the step of forming the isolation layer 510 in the second trench 250 further includes: etching the isolation material layer 500 , leaving the isolation layer 500 in the second trench 250 and The remaining isolation material layer 500 on the top of the substrate 100 exposed by the first trench 240 serves as the isolation layer 510 , and the isolation layer 510 exposes sidewalls of the trench structure 200 .
  • the isolation layer 510 exposes the sidewalls of the channel structure 200 to prepare for the subsequent formation of a source-drain doped layer in the first trench 240 .
  • the step of etching the isolation material layer 500 includes: performing a first etching on the isolation material layer 500 to remove the Partial height of the isolation material layer 500 on the top of the dummy gate structure 400 forms an opening 260 .
  • the opening 260 is used to expand the etching process window for removing the isolation material layer 500 between the adjacent dummy gate structures 400 , which facilitates subsequent removal of the isolation material layer 500 higher than the bottom of the trench structure 200 .
  • a dry etching process is used to remove the Layer 500 of isolation material at partial height.
  • the dry etching process is an anisotropic dry etching process. Therefore, by selecting the dry etching process, it is beneficial to reduce the gate area on the side of the opening 260 during the first etching process. Damage to pole sidewall 410 .
  • the step of etching the isolation material layer 500 further includes: after forming the opening 240, performing a second etching on the isolation material layer 500 to remove the Layer 500 of isolation material.
  • the remaining isolation material layer 500 higher than the bottom of the trench structure 200 is removed, and the remaining isolation material layer 500 is retained as the isolation layer 510 .
  • an isotropic etching process is used to remove the isolation material layer 500 higher than the bottom of the trench structure 200 .
  • the aspect ratio of the first trench 240 is large, and it is beneficial to remove the isolation material layer 500 higher than the bottom of the trench structure 200 by using an isotropic etching process.
  • the isotropic etching process includes a plasma chemical reaction group etching process or a vapor phase etching process.
  • the plasma chemical reaction group etching process may be a Certas etching process or a SiCoNi etching process
  • the vapor phase etching process may also be a Certas etching process or a SiCoNi etching process.
  • the Certas etching process or SiCoNi etching process has better isotropic properties, which is beneficial to remove the isolation material layer 500 higher than the bottom of the channel structure 200, and the Certas etching process or SiCoNi etching process The process can have better etching selectivity.
  • the isolation material layer 500 higher than the bottom of the trench structure 200 is removed by controlling the etching time until the isolation layer 500 at the bottom of the trench structure 200 is exposed. Material layer 500 top surface.
  • the isolation material layer 500 higher than the bottom of the trench structure 200 is removed after the second etching.
  • the sidewall of the first trench may still have an isolation material layer. The layer of insulating material is removed cleanly.
  • FIG. 14 is a cross-sectional view based on FIG. 13 .
  • the isolation layer 510 After forming the isolation layer 510 and before subsequently forming the source-drain doped layer, it also includes: along the direction perpendicular to the sidewall of the dummy gate structure 400 , through the In the first trench 240 , a part of the second sacrificial layer 220 exposed on the sidewall of the channel structure 200 is removed to form a third trench 270 .
  • the third groove 270 provides a space for the subsequent formation of the inner wall.
  • FIG. 15 which is a cross-sectional view based on FIG. 14 , an inner wall 280 is formed in the third groove 270 .
  • the inner wall 280 functions to isolate the gate structure and the source-drain doped layer, so as to reduce the parasitic capacitance between the gate structure and the source-drain doped layer.
  • the inner wall 280 is made of insulating material.
  • the material of the inner wall 280 includes silicon nitride and silicon oxycarbide.
  • FIGS. 16 to 18 are cross-sectional views based on FIG. 15 , after the isolation layer 510 is formed, a source-drain doped layer 600 is formed in the first trench 240 .
  • a source-drain doped layer 600 is formed in the first trench 240 .
  • the source-drain doped layer 600 is used as a source region or a drain region of the formed transistor.
  • the source-drain doped layer 600 is epitaxially grown using the channel layer 230 as the basis for epitaxial growth. Therefore, in this embodiment, in the step of forming the source-drain doped layer 600 , the source-drain doped layer 600 is in contact with the inner wall 280 .
  • the doping type of the source-drain doped layer 600 is the same as the channel conductivity type of the corresponding transistor, specifically, when the substrate 100 is used to form an NMOS transistor, the doping in the source-drain doped layer 600
  • the hetero ions are N-type ions, and the N-type ions include P ions, As ions or Sb ions; when the substrate 100 is used to form a PMOS transistor, the dopant ions in the source-drain doped layer 600 are P-type ions ions, the P-type ions include B ions, Ga ions or In ions.
  • the material of the source-drain doped layer 600 is Si or SiC doped with N-type ions, and the source-drain doped layer 600 is the channel of the NMOS transistor.
  • the channel region provides tensile stress, which is conducive to improving the carrier mobility of the NMOS transistor;
  • the material of the source-drain doped layer 600 is Si doped with P-type ions Or SiGe, the source-drain doped layer 600 provides compressive stress for the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor.
  • the first source-drain doped layer 610 is formed in the first device region 100P, and the second source-drain layer 610 is formed in the second device region 100N. Drain doped layer 620.
  • the first transistor is a PMOS transistor
  • the P-type ions in the first source-drain doped layer 610 are B ions
  • the material of the first source-drain doped layer 610 is doped with B ions of SiGe
  • the second transistor is an NMOS transistor
  • the N-type ions in the second source-drain doped layer 620 are P ions
  • the material of the second source-drain doped layer 620 is doped by P ions Si.
  • the step of forming the first source-drain doped layer 610 and the second source-drain doped layer 620 includes: in the first device region 100P and the second device region 100N, forming The sidewall and top of the dummy gate structure 400 , and the protection layer 140 on the sidewall and bottom of the first trench 240 .
  • the protective layer 140 is used to protect the first trench 240, and can reduce the pollution of the first mask layer formed subsequently to the first trench 240 in the second device region 100N, thereby reducing the influence on the formation of the second source The influence of the drain doped layer 620.
  • the protective layer 140 is formed by using an atomic layer deposition process, so that the thickness uniformity of the protective layer 140 is good, and the atomic layer deposition process has good step coverage (step coverage), so that the protective layer 140 can well conformally cover the sidewall and top of the dummy gate structure 400 and the sidewall and bottom of the first trench 240 .
  • the material of the protection layer includes SiC, SiCO, SiCON, BN or BCN.
  • the step of forming the first source-drain doped layer 610 and the second source-drain doped layer 620 further includes: forming a first mask layer 120 covering the protective layer 140 in the second device region 100N, The first mask layer 120 is filled in the first trench 240 , and the first mask layer 120 exposes the first device region 100P.
  • the first mask layer 120 is used to cover the second device region 100N during the process of forming the first source-drain doped layer 610 to protect the second device region 100N from being affected.
  • the first mask layer 120 is a laminated structure, and the first mask layer 120 includes a planarization layer (not shown) and a photoresist layer (not shown) on the planarization layer. Shows).
  • the material of the planarization layer includes spin on carbon (spin on carbon, SOC) material.
  • spin on carbon spin on carbon, SOC
  • Spin-on carbon is formed by a spin-coating process, and the process cost is low.
  • spin-on carbon it is beneficial to improve the flatness of the top surface of the planarization layer, thereby providing a flat surface for forming a photoresist layer, thereby improving photolithographic effect; in addition, by using spin-on-carbon, there is no need for chemical mechanical polishing process for planarization, which improves process efficiency.
  • the protective layer 120 located in the first device region 100P is removed; after removing the protective layer 120 located in the first device region 100P, in the first A first source-drain doped layer 610 is formed in the first trench 240 of the device region 100P.
  • the first mask layer 120 and the protection layer 140 located in the second device region 100N are removed to prepare for forming the second source-drain doped layer 620 .
  • a second mask layer 130 covering the second device region 100N is formed, and the second The mask layer 130 covers the second source-drain doped layer 620 , and the second mask layer 130 exposes the second device region 100N.
  • the second mask layer 130 is used to cover the first device region 100P during the process of forming the second source-drain doped layer 620 to protect the first device region 100P from being affected.
  • the material of the second mask layer 130 includes SiN or SiNC, and the SiN or SiNC can form an etching selectivity with other materials of the semiconductor structure, so that in During the subsequent process of removing the second mask layer 130, the damage to the semiconductor structure is reduced.
  • a second source-drain doped layer 620 is formed in the first trench 240 of the second device region 100N.
  • the second mask layer 130 is removed to prepare for forming a gate structure.
  • the dummy gate structure 400 is removed to form a gate opening (not shown); the second sacrificial layer 220 is removed through the gate opening; after removing the second sacrificial layer 220, the A gate structure 700 is formed in the gate opening, and the gate structure 700 includes a gate dielectric layer 710 surrounding the channel layer 230 along the extending direction of the gate structure 700, and a gate electrode located on the gate dielectric layer 710. Electrode layer 720 .
  • the gate structure 700 is used to control the opening or closing of the channel of the transistor.
  • the gate structure 700 covers the channel layer 230, so the top, bottom and sidewalls of the channel layer 230 can be used as channels, increasing the area of the channel layer 230 used as a channel. , thereby increasing the operating current of the semiconductor structure.
  • the gate dielectric layer 710 is used to isolate the gate electrode layer 720 from the channel layer 230 , and the gate electrode layer 720 from the substrate 100 .
  • the material of the gate dielectric layer 710 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.
  • the gate dielectric layer 710 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material.
  • the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide.
  • the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3 and the like.
  • the gate dielectric layer 710 may further include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the channel layer 230 .
  • the material of the gate oxide layer may be silicon oxide.
  • the gate structure 700 is a metal gate structure, therefore, the material of the gate electrode layer 720 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN and TiAlC. Various.
  • the gate electrode layer 720 includes a work function layer (not shown), and an electrode layer (not shown) on the work function layer.
  • the work function layer is used to adjust the threshold voltage of the transistor
  • the electrode layer is used to extract the electricity of the metal gate structure.
  • the gate electrode layer may only include a work function layer.
  • the gate structure may also be a polysilicon gate structure.
  • 20 to 21 are structural schematic diagrams corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention.
  • the isolation layer 512 exposes the top surface of the substrate 102 .
  • after forming the isolation layer 512 and before forming the source-drain doped layer further include: removing the isolation layer 512 at the bottom of the first trench 242 to expose the base at the bottom of the first trench 242 102 top.
  • the isolation layer 512 at the bottom of the first trench 242 exposing the top surface of the substrate 102, and preparing for forming the source-drain doped layer, so that the source-drain doped layer can be formed on the top surface of the substrate 102 growth, thereby improving the growth rate and formation quality of the source-drain doped layer.
  • a dry etching process is used to remove the isolation layer 512 at the bottom of the first trench 242 .
  • the dry etching process is an anisotropic dry etching process. Therefore, by selecting a dry etching process, it is beneficial to reduce damage to the substrate 102 at the bottom of the first trench 242. At the same time, the The above dry etching has more etching directionality, which is beneficial to improve the topography quality and dimensional accuracy of the sidewall of the remaining isolation layer 512 .
  • the isolation material layer between the adjacent dummy gate structures 402 that is higher than the bottom of the channel structure 202 can be further removed, and the The isolation material layer above the bottom of the trench structure 202 is removed.
  • the source-drain doped layer 602 is in contact with the top surface of the substrate 102 .
  • the doped source and drain layers 602 are in contact with the substrate 102, which is conducive to increasing the growth of the doped source and drain layers 602. rate, improve the growth quality of the source-drain doped layer 602, and reduce defects generated during the growth process.

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Abstract

一种半导体结构及其形成方法，形成方法包括：提供基底，基底上形成有第一牺牲层，第一牺牲层上形成有沟道结构，包括一个或多个堆叠的沟道叠层，沟道叠层包括第二牺牲层和位于第二牺牲层上的沟道层，基底上还形成有横跨沟道结构的伪栅结构，其中，第一牺牲层的耐刻蚀度小于第二牺牲层的耐刻蚀度；去除伪栅结构两侧的沟道结构和第一牺牲层，形成贯穿沟道结构和第一牺牲层的第一沟槽；通过第一沟槽去除沟道结构底部的第一牺牲层，在沟道结构底部形成与第一沟槽相连通的第二沟槽；在第二沟槽中形成隔离层；形成隔离层后，在第一沟槽中形成源漏掺杂层。隔离层有效隔绝栅极结构和基底，从而减小栅极结构和基底之间产生漏电流的概率。

Description

半导体结构及其形成方法 技术领域
本发明实施例涉及半导体制造领域，尤其涉及一种半导体结构及其形成方法。
 背景技术
在半导体制造中，随着超大规模集成电路的发展趋势，集成电路特征尺寸持续减小，为了适应更小的特征尺寸，金属-氧化物-半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)的沟道长度也相应不断缩短。然而，随着器件沟道长度的缩短，器件源极与漏极间的距离也随之缩短，因此栅极结构对沟道的控制能力随之变差，栅极电压夹断(pinch off)沟道的难度也越来越大，使得亚阈值漏电(subthreshold leakage)现象，即所谓的短沟道效应(SCE：short-channel effects)更容易发生。
因此，为了更好的适应器件尺寸按比例缩小的要求，半导体工艺逐渐开始从平面晶体管向具有更高功效的三维立体式的晶体管过渡，如全包围栅极(Gate-all-around，GAA)晶体管。全包围金属栅极晶体管中，栅极从四周包围沟道所在的区域，与平面晶体管相比，全包围金属栅极晶体管的栅极对沟道的控制能力更强，能够更好的抑制短沟道效应。
 技术问题
本发明实施例解决的问题是提供一种半导体结构及其形成方法，提高半导体结构的性能。
 技术解决方案
为解决上述问题，本发明实施例提供了一种半导体结构，包括：基底，包括沟道区，所述基底表面的法线方向为纵向；隔离层，位于所述沟道区的基底上；沟道层结构，位于所述沟道区且悬置于所述隔离层上方，在所述纵向上，所述沟道层结构包括一个或多个间隔的沟道层；栅极结构，位于所述基底上且横跨所述沟道层结构，所述栅极结构包括沿所述栅极结构延伸方向环绕所述沟道层的栅介质层、以及位于所述栅介质层上的栅电极层，在所述沟道区中，所述栅极结构位于所述隔离层上；源漏掺杂层，位于所述栅极结构两侧的基底上，在所述沟道层结构的延伸方向上，所述源漏掺杂层与所述沟道层结构的端部、以及所述隔离层的端部相接触。
相应的，本发明实施例还提供了一种半导体结构的形成方法，包括：提供基底，所述基底上形成有第一牺牲层，所述第一牺牲层上形成有沟道结构，所述沟道结构包括一个或多个堆叠的沟道叠层，所述沟道叠层包括第二牺牲层和位于所述第二牺牲层上的沟道层，所述基底上还形成有横跨所述沟道结构的伪栅结构，所述伪栅结构覆盖所述沟道结构的部分侧壁和部分顶部，其中，所述第一牺牲层的耐刻蚀度小于第二牺牲层的耐刻蚀度；去除所述伪栅结构两侧的沟道结构和第一牺牲层，形成贯穿所述沟道结构和第一牺牲层的第一沟槽；通过所述第一沟槽去除所述沟道结构底部的第一牺牲层，在所述沟道结构底部形成与所述第一沟槽相连通的第二沟槽；在所述第二沟槽中形成隔离层；形成所述隔离层后，在所述第一沟槽中形成源漏掺杂层。
 有益效果
与现有技术相比，本发明实施例的技术方案具有以下优点：本发明实施例提供的半导体结构中，包括位于所述沟道层结构底部的基底上的隔离层，在所述沟道区中，所述栅极结构位于所述隔离层上，则所述隔离层有效隔绝了所述栅极结构和沟道区的基底的接触，从而减小了在沟道区中，所述栅极结构和基底之间产生漏电流的概率，而且，相比于在沟道区的基底中进行离子注入来隔绝栅极结构和基底的方案，本发明实施例能够避免因对基底进行离子注入而引起的寄生电容变大的问题，此外，所述源漏掺杂层位于所述栅极结构两侧的基底上，且与所述隔离层的端部相接触，则在相邻所述源漏掺杂层通过所述隔离层进行有效隔离的同时，所述源漏掺杂层与基底相接触，有利于增加所述源漏掺杂层的生长速率，并提升所述源漏掺杂层的生长质量，减少生长过程中产生的缺陷，综上所述皆有利于提高所述半导体结构的工作性能。
本发明实施例提供的形成方法中，所述基底上形成有第一牺牲层，通过所述第一沟槽去除所述第一牺牲层，在所述沟道结构底部形成与所述第一沟槽相连通的第二沟槽，在所述第二沟槽中形成隔离层，通过采用先形成第一牺牲层为隔离层占据空间位置，再去除所述第一牺牲层，形成隔离层的方法，有利于位于所述第一牺牲层上的沟道结构的生长，并且可以根据工艺需求灵活选用所述第一牺牲层的材料，提高所述第一牺牲层的工艺兼容性，此外，后续去除第二牺牲层形成栅极结构后，所述栅极结构形成于所述隔离层上，则所述隔离层有效隔绝了所述栅极结构和基底的接触，从而减小了所述栅极结构和基底之间产生漏电流的概率，而且，相比于在基底中进行离子注入来隔绝栅极结构和基底的方案，本发明实施例能够避免因对基底进行离子注入而引起的寄生电容变大的问题，综上所述皆有利于提高所述半导体结构的工作性能。
 附图说明
图1至图2是一种半导体结构的形成方法中各步骤对应的结构示意图。
图3至图4是本发明半导体结构一实施例对应的结构示意图。
图5至图19是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
图20至图21是本发明半导体结构的形成方法另一实施例中各步骤对应的结构示意图。
 本发明的实施方式
目前半导体结构的性能有待提高。现结合一种半导体结构的形成方法分析其性能有待提高的原因。
图1至图2是一种半导体结构的形成方法中各步骤对应的结构示意图。
参考图1，提供基底10，对所述基底10顶部进行离子注入，在所述基底10中形成隔离区（图未示）；形成所述隔离区后，在所述隔离区所在的基底10上形成沟道结构20，所述沟道结构20包括一个或多个沟道叠层21，其中，所述沟道叠层21包括牺牲层22和位于所述牺牲层22上的沟道层23；在所述基底10上形成横跨所述沟道结构20的伪栅结构40，所述伪栅结构40覆盖所述沟道结构20的部分侧壁和部分顶部。
参考图2，去除所述伪栅结构40，形成栅极开口（未示出）；通过所述栅极开口去除所述牺牲层22，露出所述沟道层23的各个表面；去除所述牺牲层22后，在所述栅极开口中形成环绕覆盖所述沟道层23的栅极结构70。
形成所述栅极结构70后，所述栅极结构70还与所述基底10顶部相接触，因此，为了使所述基底10和栅极结构70之间相隔绝，减小半导体结构的漏电流，在形成沟道结构20之前，形成隔离区，从而使得所述基底10和后续形成的栅极结构之间具有隔离效果。而且，为了确保所述隔离区的隔离效果，通常会对所述基底10顶部进行较高浓度的离子注入。
然而对所述基底10顶部进行较高浓度的离子注入容易导致所述半导体结构的寄生电容增大，影响所述半导体结构的性能。
为了解决所述技术问题，本发明实施例提供一种半导体结构的形成方法，包括：提供基底，所述基底上形成有第一牺牲层，所述第一牺牲层上形成有沟道结构，所述沟道结构包括一个或多个堆叠的沟道叠层，所述沟道叠层包括第二牺牲层和位于所述第二牺牲层上的沟道层，所述基底上还形成有横跨所述沟道结构的伪栅结构，所述伪栅结构覆盖所述沟道结构的部分侧壁和部分顶部，其中，所述第一牺牲层的耐刻蚀度小于第二牺牲层的耐刻蚀度；去除所述伪栅结构两侧的沟道结构和第一牺牲层，形成贯穿所述沟道结构和第一牺牲层的第一沟槽；通过所述第一沟槽去除所述沟道结构底部的第一牺牲层，在所述沟道结构底部形成与所述第一沟槽相连通的第二沟槽；在所述第二沟槽中形成隔离层；形成所述隔离层后，在所述第一沟槽中形成源漏掺杂层。
本发明实施例提供的形成方法中，所述基底上形成有第一牺牲层，通过所述第一沟槽去除所述第一牺牲层，在所述沟道结构底部形成与所述第一沟槽相连通的第二沟槽，在所述第二沟槽中形成隔离层，通过采用先形成第一牺牲层为隔离层占据空间位置，再去除所述第一牺牲层，形成隔离层的方法，有利于位于所述第一牺牲层上的沟道结构的生长，并且可以根据工艺需求灵活选用所述第一牺牲层的材料，提高所述第一牺牲层的工艺兼容性，此外，后续去除第二牺牲层形成栅极结构后，所述栅极结构形成于所述隔离层上，则所述隔离层有效隔绝了所述栅极结构和基底的接触，从而减小了所述栅极结构和基底之间产生漏电流的概率，而且，相比于在基底中进行离子注入来隔绝栅极结构和基底的方案，本发明实施例能够避免因对基底进行离子注入而引起的寄生电容变大的问题，综上所述皆有利于提高所述半导体结构的工作性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图3至图4是本发明半导体结构一实施例对应的结构示意图，图3是栅极结构和源漏掺杂层的俯视图，图4是图3基于AA方向的剖视图。
所述半导体结构包括：基底101，包括沟道区101c，所述基底101表面的法线方向为纵向（如图4中Z方向所示）；隔离层511，位于所述沟道区101c的基底101上；沟道层结构201，位于所述沟道区101c且悬置于所述隔离层511上方，在所述纵向上，所述沟道层结构201包括一个或多个间隔的沟道层231；栅极结构701，位于所述基底101上且横跨所述沟道层结构201，所述栅极结构701包括沿所述栅极结构701延伸方向环绕所述沟道层231的栅介质层711、以及位于所述栅介质层711上的栅电极层721，在所述沟道区101c中，所述栅极结构701位于所述隔离层511上；源漏掺杂层601，位于所述栅极结构701两侧的基底101上，在所述沟道层结构201的延伸方向上，所述源漏掺杂层601与所述沟道层结构201的端部、以及所述隔离层511的端部相接触。
所述基底101为所述半导体结构的形成工艺提供工艺操作基础。其中，所述半导体结构包括全包围栅极（gate-all-around，GAA）晶体管和叉型栅极（Forksheet）晶体管。
所述基底101包括衬底（未示出）。
本实施例中，所述衬底的材料为硅。在其他实施例中，所述衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料，所述衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。所述衬底的材料可以是适宜于工艺需要或易于集成的材料。
需要说明的是，基底101还可以包括：鳍部（未标示），位于所述衬底上。
本实施例中，所述基底101包括沟道区101c，所述沟道区101c的沟道层结构201用于作为晶体管的沟道。
本实施例中，所述半导体结构还包括：浅沟槽隔离结构111，位于所述基底101中。
所述浅沟槽隔离结构111用于实现不同器件之间的绝缘，例如在CMOS制造工艺中，通常会在NMOS晶体管和PMOS晶体管之间形成浅沟槽隔离结构111。
本实施例中，所述浅沟槽隔离结构111位于所述鳍部露出的衬底上，并覆盖所述鳍部的侧壁。
所述浅沟槽隔离结构111的材料为绝缘材料。本实施例中，所述浅沟槽隔离结构111的材料为氧化硅。
所述隔离层511用于隔绝所述栅极结构701和沟道区101c的基底101。
本实施例提供的半导体结构中，在所述沟道区101c中，所述栅极结构701位于所述隔离层511上，则所述隔离层511有效隔绝了所述栅极结构701和沟道区101c的基底101的接触，从而减小了在沟道区101c中，所述栅极结构701和基底101之间产生漏电流的概率，而且，相比于在沟道区的基底中进行离子注入来隔绝栅极结构和基底的方案，本发明实施例能够避免因对基底101进行离子注入而引起的寄生电容变大的问题，此外，所述源漏掺杂层601位于所述栅极结构701两侧的基底101上，且与所述隔离层511的端部相接触，则在相邻所述源漏掺杂层601通过所述隔离层511进行有效隔离的同时，所述源漏掺杂层601与基底101相接触，有利于增加所述源漏掺杂层601的生长速率，并提升所述源漏掺杂层601的生长质量，减少生长过程中产生的缺陷，综上所述皆有利于提高所述半导体结构的工作性能。
需要说明的是，所述隔离层511的厚度d2不宜过大，也不宜过小。如果所述隔离层511的厚度d2过大，则容易造成不必要的工艺浪费，而且，形成所述隔离层511之前，通过形成第一牺牲层为隔离层511占据空间位置，之后再去除第一牺牲层，去除第一牺牲层之后再形成隔离层511，因此，如果所述隔离层511的厚度d2过大，则所述第一牺牲层的厚度也过大，也容易造成不必要的工艺浪费，还增加了去除第一牺牲层的工艺难度；如果所述隔离层511的厚度d2过小，则容易影响所述隔离层511的隔离性能，从而难以较好地将所述栅极结构701和沟道区101c的基底101完全隔绝，影响所述半导体结构的性能。为此，本实施例中，所述隔离层511的厚度d2为5nm至15nm。
本实施例中，所述隔离层511的材料包括介电材料，所述介电材料能够对所述栅极结构701和沟道区101c的基底101起到隔绝作用，而且，介电材料的工艺兼容性高，从而减小所述隔离层511对工艺制程的影响。
本实施例中，所述隔离层511的材料包括氧化硅和氮化硅中的一种或多种，所述氧化硅和氮化硅有利于较好地隔绝所述栅极结构701和沟道区101c的基底101。
所述沟道层结构201包括一个或多个在纵向上间隔的沟道层231，所述沟道层231用于作为半导体结构的沟道。
本实施例中，所述沟道层231的材料包括硅、锗、锗化硅或Ⅲ-Ⅴ族半导体材料。作为一种示例，所述沟道层231的材料为硅。在其他实施例中，所述沟道层的材料根据晶体管的类型和性能决定。
需要说明的是，在本实施例中，所述沟道层231和衬底的材料相同，在其他实施例中，所述沟道层和衬底的材料还可以不相同。
所述栅极结构701用于控制所述晶体管的沟道的开启和关断。
所述栅极结构701环绕覆盖所述沟道层231，因此，所述沟道层231的顶部、底部和侧壁均能够作为沟道，增大了沟道层231中用于作为沟道的面积，从而增大了所述半导体结构的工作电流。
所述栅介质层711用于隔离栅电极层721与沟道层231、以及栅电极层721与沟道区101c的基底101。
所述栅介质层711的材料包括HfO2、ZrO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、SiO2和La2O3中的一种或多种。本实施例中，所述栅介质层711包括高k栅介质层，高k栅介质层的材料包括高k介质材料。其中，高k介质材料是指相对介电常数大于氧化硅相对介电常数的介质材料。具体地，所述高k栅介质层的材料包括HfO2、ZrO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO或Al2O3等。
需要说明的是，栅介质层711还可以包括栅氧化层，栅氧化层位于高k栅介质层和沟道层231之间。具体地，栅氧化层的材料可以为氧化硅。
本实施例中，所述栅极结构701为金属栅极结构，因此，所述栅电极层721的材料包括TiN、TaN、Ta、Ti、TiAl、W、AL、TiSiN和TiAlC中的一种或多种。
具体地，所述栅电极层721包括功函数层（未示出）、以及位于功函数层上的电极层（未示出）。其中，所述功函数层用于调节晶体管的阈值电压，所述电极层用于将金属栅极结构的电性引出。
在另一些实施例中，栅电极层也可以仅包括功函数层。
在其他实施例中，根据工艺需求，所述栅极结构也可以为多晶硅栅结构。
本实施例中，所述半导体结构还包括：栅极侧墙411，覆盖所述栅极结构701的侧壁。
所述栅极侧墙411用于保护栅极结构701的侧壁。所述栅极侧墙411可以为单层结构或叠层结构，所述栅极侧墙411的材料包括氧化硅、氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼和碳氮化硼中的一种或多种。本实施例中，所述栅极侧墙411为单层结构，所述栅极侧墙411的材料为氮化硅。
本实施例中，相邻所述栅极结构701的相对侧壁上的栅极侧墙411之间的距离d1，大于所述隔离层511的厚度d2。
在所述半导体结构的形成过程中，通过从相邻所述栅极结构701的相对侧壁上的栅极侧墙411之间的空隙沉积隔离材料层，使隔离材料层填充于所述沟道层结构201底部的空间，从而形成隔离层511，但同时，隔离材料层也会沉积在相邻所述栅极结构701的相对侧壁上的栅极侧墙411之间的空隙侧壁上，为了更好地去除空隙侧壁上的隔离材料层，则空隙侧壁上的隔离材料层之间具有间隙，因此，相邻所述栅极结构701的相对侧壁上的栅极侧墙411之间的距离d1，大于所述隔离层511的厚度d2。
所述源漏掺杂层601用于作为晶体管的源区或漏区。具体地，所述源漏掺杂层601的掺杂类型与相对应的晶体管的沟道导电类型相同。
本实施例中，所述源漏掺杂层601位于所述栅极结构701两侧的基底101上，且在所述沟道层结构201的延伸方向上，所述源漏掺杂层601与所述隔离层511的端部相接触，则相邻所述源漏掺杂层601之间通过所述隔离层511进行有效隔离，同时，所述源漏掺杂层601采用外延生长工艺形成，所述源漏掺杂层601与基底101相接触，有利于增加所述源漏掺杂层601的生长速率，并提升所述源漏掺杂层601的生长质量，减少生长过程中产生的缺陷。
所述源漏掺杂层601的掺杂类型与相对应的晶体管的沟道导电类型相同，具体地，当所述基底101用于形成NMOS晶体管时，所述源漏掺杂层601内的掺杂离子为N型离子，所述N型离子包括P离子、As离子或Sb离子；当所述基底101用于形成PMOS晶体管时，所述源漏掺杂层601内的掺杂离子为P型离子，所述P型离子包括B离子、Ga离子或In离子。
具体地，当所述基底101用于形成NMOS晶体管时，所述源漏掺杂层601的材料为掺杂有N型离子的Si或SiC，所述源漏掺杂层601为NMOS晶体管的沟道区提供拉应力作用，从而有利于提高NMOS晶体管的载流子迁移率；当所述基底用于形成PMOS晶体管时，所述源漏掺杂层601的材料为掺杂有P型离子的Si或SiGe，所述源漏掺杂层601为PMOS晶体管的沟道区提供压应力作用，从而有利于提高PMOS晶体管的载流子迁移率。
本实施例中，所述半导体结构还包括：内侧墙281，在所述纵向上，所述内侧墙281位于相邻所述沟道层231之间、以及底部的沟道层231与隔离层511之间，且在所述沟道层结构201的延伸方向上，所述内侧墙281位于所述栅极结构701和源漏掺杂层601之间。
所述内侧墙281起到隔离栅极结构701和源漏掺杂层601的作用，以减小栅极结构701和源漏掺杂层601之间的寄生电容。
所述内侧墙281的材料为绝缘材料。本实施例中，所述内侧墙281的材料包括氮化硅和碳氧化硅。
图5至图19是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
结合参考图5和图6，图5为伪栅结构和鳍部的俯视图，图6为图5基于AA方向的剖视图，提供基底100，所述基底100上形成有第一牺牲层300，所述第一牺牲层300上形成有沟道结构200，所述沟道结构200包括一个或多个堆叠的沟道叠层210，所述沟道叠层210包括第二牺牲层220和位于所述第二牺牲层220上的沟道层230，所述基底100上还形成有横跨所述沟道结构200的伪栅结构400，所述伪栅结构400覆盖所述沟道结构200的部分侧壁和部分顶部，其中，所述第一牺牲层300的耐刻蚀度小于第二牺牲层220的耐刻蚀度。
所述基底100为所述半导体结构的形成工艺提供工艺操作基础。其中，所述半导体结构包括全包围栅极（gate-all-around，GAA）晶体管和叉型栅极（Forksheet）晶体管。
所述基底100包括衬底（未示出）。
本实施例中，所述衬底的材料为硅。在其他实施例中，所述衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料，所述衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。所述衬底的材料可以是适宜于工艺需要或易于集成的材料。
需要说明的是，基底100还可以包括：鳍部（未标示），位于所述衬底上。
结合参考图6，图6（a）表示第一器件区的示意图，图6（b）表示第二器件区的示意图，本实施例中，所述提供基底100的步骤中，所述基底100包括用于形成第一晶体管的第一器件区100P（如图6（a）所示）和用于形成第二晶体管的第二器件区100N（如图6（b）所示）。
本实施例中，所述第一晶体管和第二晶体管的沟道导电类型不同，所述沟道导电类型包括N型或P型。作为一种示例，所述第一晶体管为PMOS晶体管，所述第二晶体管为NMOS晶体管。在其他实施中，所述第一晶体管和第二晶体管的沟道导电类型也可以相同。
本实施例中，所述提供基底100的步骤中，所述基底100还包括浅沟槽隔离结构110。
所述浅沟槽隔离结构110用于实现不同器件之间的绝缘，例如在CMOS制造工艺中，通常会在NMOS晶体管和PMOS晶体管之间形成浅沟槽隔离结构110。
本实施例中，所述浅沟槽隔离结构110位于鳍部露出的衬底上，并覆盖鳍部的侧壁。
所述浅沟槽隔离结构110的材料为绝缘材料。本实施例中，所述浅沟槽隔离结构110的材料为氧化硅。
所述沟道结构200中的沟道层230用于作为半导体结构的沟道，所述牺牲层220用于为后续实现所述沟道层230的悬空设置提供工艺基础，也用于为后续形成的栅极结构占据空间位置。后续制程中，去除所述牺牲层220，使得沟道层230悬空，在所述沟道层230与所述基底100之间，以及相邻所述沟道层230之间形成栅极结构。
沟道层230中被栅极结构所覆盖的表面用来作为沟道，本实施例中，所述沟道层230的顶部、底部和侧壁均能够作为沟道，增大了沟道层230中用于作为沟道的面积，从而增大了所述半导体结构的工作电流。
本实施例中，所述沟道层230的材料包括硅、锗、锗化硅或Ⅲ-Ⅴ族半导体材料。作为一种示例，所述沟道层230的材料为硅。在其他实施例中，所述沟道层的材料根据晶体管的类型和性能决定。
需要说明的是，在本实施例中，所述沟道层230和衬底的材料相同，在其他实施例中，所述沟道层和衬底的材料还可以不相同。
本实施例中，所述第二牺牲层220的材料包括锗化硅。
所述锗化硅与硅能形成较大的刻蚀选择比，有利于后续去除所述第二牺牲层220，并减少对沟道层230的损伤。
在其他实施例中，可以根据沟道层的材料，第二牺牲层选取与沟道层具有刻蚀选择比的相适宜的材料，以便后续去除第二牺牲层时，减小对沟道层的损伤。
所述第一牺牲层300为后续形成隔离层占据空间位置。
需要说明的是，所述第一牺牲层300的厚度d2不宜过大，也不宜过小。如果所述第一牺牲层300的厚度d2过大，则容易造成不必要的工艺浪费，而且，所述第一牺牲层300为后续形成隔离层占据空间位置，之后再去第一除牺牲层300，去除第一牺牲层300之后再形成隔离层，因此，如果所述第一牺牲层300的厚度d2过大，则所述隔离层的厚度也过大，也容易造成不必要的工艺浪费，还增加了去除第一牺牲层300的工艺难度；如果所述第一牺牲层300的厚度d2过小，则后续形成的隔离层的厚度过小，容易影响隔离层的隔离性能，从而难以较好地将栅极结构和基底101完全隔绝，影响所述半导体结构的性能。为此，本实施例中，所述第一牺牲层300的厚度d2为5nm至15nm。
本实施例中，所述第一牺牲层300的耐刻蚀度小于第二牺牲层220的耐刻蚀度，有利于后续去除所述第一牺牲层300，并在后续去除所述第一牺牲层300的过程中，减小对所述第二牺牲层220的损伤。
需要说明的是，所述第一牺牲层300和第二牺牲层220的刻蚀选择比不宜过小。如果所述第一牺牲层300和第二牺牲层220的刻蚀选择比过小，则在后续去除所述第一牺牲层300的过程中，容易对所述第二牺牲层220造成损伤，甚至将所述第二牺牲层220一同去除，则在形成隔离层的步骤中，沿纵向相邻的所述沟道层230之间也填充有隔离层，从而影响在纵向上的相邻所述沟道层230之间栅极结构的形成，进而影响所述半导体结构的性能。为此，所述第一牺牲层300和第二牺牲层220的刻蚀选择比大于10。
本实施例中，所述第一牺牲层300的材料包括半导体材料，有利于所述第一牺牲层300在所述基底100上外延生长，同时，也有利于所述沟道结构200在所述第一牺牲层300上外延生长，从而提高所述第一牺牲层300的工艺兼容性，使得所述第一牺牲层300和沟道结构200可以在同一工序中，采用外延生长工艺在所述基底100上生长。
本实施例中，所述第一牺牲层300的材料包括Si1-yGey，所述第二牺牲层220的材料包括Si1-xGex，其中，x＜y，也就是说，所述第一牺牲层300中Ge元素和Si元素的摩尔比大于所述第二牺牲层220中Ge元素和Si元素的摩尔比，从而使得所述第一牺牲层300的耐刻蚀度小于第二牺牲层220的耐刻蚀度。
本实施例中，在所述第一牺牲层300的材料Si1-yGey中，y不宜过小。如果在所述第一牺牲层300的材料Si1-yGey中，y值过小，则所述第一牺牲层300的耐刻蚀度过大，所述第一牺牲层300不易被刻蚀，对后续去除所述第一牺牲层300造成困难。为此，本实施例中，在所述第一牺牲层300的材料Si1-yGey中，y≥0.4。
本实施例中，在所述第二牺牲层220的材料Si1-xGex中，x不宜过大，也不宜过小。由于所述沟道层230通过在所述第二牺牲层220上外延生长获得，如果在所述第二牺牲层220的材料Si1-xGex中，x值过大，则所述第二牺牲层220中Ge元素的浓度过大，形成所述沟道层230时，由所述第二牺牲层220的材料过渡至所述沟道层230的材料所需的过渡层过厚，导致形成的所述沟道层230的有效厚度过小，影响所述沟道层230的质量，从而影响所述半导体结构的性能；如果在所述第二牺牲层220的材料Si1-xGex中，x值过小，则所述第二牺牲层220的耐刻蚀度过大，所述第二牺牲层220不易被刻蚀，对后续去除所述第二牺牲层220造成困难，同时，容易导致所述第二牺牲层220和沟道层230的刻蚀选择比过小，从而在去除所述第二牺牲层220的过程中，对所述沟道层230造成损伤，影响所述半导体结构的性能。为此，本实施例中，在所述第二牺牲层220的材料Si1-xGex中，0.1≤x≤0.5。
所述伪栅结构400用于为后续形成栅极结构占据空间位置。
具体地，所述伪栅结构400为叠层结构，包括伪栅氧化层（图未示）以及覆盖所述伪栅氧化层的伪栅层（图未示）。
作为一种示例，所述伪栅氧化层的材料为氧化硅，所述伪栅层的材料为多晶硅。
本实施例中，所述提供基底100的步骤中，所述基底100上还形成有覆盖所述伪栅结构400的顶部和侧壁的栅极侧墙410。
后续去除伪栅结构410之间间隙中的隔离材料层的过程中，所述栅极侧墙410用于保护所述伪栅结构400的侧壁，从而保障后续栅极结构的形成质量，并且在形成栅极结构后，保护栅极结构的侧壁。
所述栅极侧墙410可以为单层结构或叠层结构，所述栅极侧墙410的材料包括氧化硅、氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼和碳氮化硼中的一种或多种。本实施例中，所述栅极侧墙410为单层结构，所述栅极侧墙410的材料为氮化硅。
本实施例中，形成所述栅极侧墙410的步骤中，所述栅极侧墙410保形覆盖所述伪栅结构400和沟道结构200。
本实施例中，相邻所述伪栅结构400的相对侧壁上的栅极侧墙410之间的距离d1，大于所述第一牺牲层300的厚度d2。
后续去除所述第一牺牲层300形成第二沟槽，再通过从相邻所述伪栅结构400的相对侧壁上的栅极侧墙410之间的空隙沉积隔离材料层，使隔离材料层填充位于所述沟道结构200底部的第二沟槽，从而形成隔离层，但同时，隔离材料层也会沉积在相邻所述伪栅结构400的相对侧壁上的栅极侧墙410之间的空隙侧壁上，为了更好地去除空隙侧壁上的隔离材料层，则空隙侧壁上的隔离材料层之间具有间隙，因此，相邻所述伪栅结构400的相对侧壁上的栅极侧墙410之间的距离d1，大于所述第一牺牲层300的厚度d2。
需要说明的是，若未做特殊说明，后续附图用于表示第一器件区100P和第二器件区100N中任一区域的附图。
参考图7，去除所述伪栅结构400两侧的沟道结构200和第一牺牲层300，形成贯穿所述沟道结构200和第一牺牲层300的第一沟槽240。
所述第一沟槽露出所述第一牺牲层300的侧壁，为后续去除所述第一牺牲层300做准备，后续还通过所述第一沟槽240形成隔离层，所述第一沟槽240还为后续形成源漏掺杂层提供空间位置。
本实施例中，在所述第一器件区100P和第二器件区100N中一同形成第一沟槽240，用于形成源漏掺杂层，相比于在第一器件区和第二器件区分别形成第一沟槽，简化了工艺流程，提高了工艺效率。
本实施例中，采用干法刻蚀工艺去除所述伪栅结构400两侧的沟道结构200和第一牺牲层300。
所述干法刻蚀工艺为各向异性的干法刻蚀工艺，因此通过选取干法刻蚀工艺，有利于减小对所述第一沟槽240底部的所述基底100的损伤，同时，所述干法刻蚀更具刻蚀方向性，有利于提高第一沟槽240的侧壁形貌质量和尺寸精度。
本实施例中，去除所述伪栅结构400两侧的沟道结构200和第一牺牲层300的步骤中，还去除所述伪栅结构400两侧的沟道结构200顶部的栅极侧墙410、以及所述伪栅结构400顶部的栅极侧墙410。
结合参考图8至图10，图8为俯视图，图9为图8基于AA方向的剖视图，图10为图8基于BB方向的剖视图，通过所述第一沟槽240去除所述沟道结构200底部的第一牺牲层300，在所述沟道结构200底部形成与所述第一沟槽240相连通的第二沟槽250。
所述第二沟槽250用于为后续形成隔离层提供空间位置。
需要说明的是，如图10所示，所述沟道结构200通过所述伪栅结构400支撑，使得在形成第二沟槽250后，所述沟道结构200悬置于所述基底100上方。
本实施例中，通过所述第一沟槽240去除所述第一牺牲层300的步骤中，采用各向同性的刻蚀工艺去除所述第一牺牲层300。
所述各向同性的刻蚀工艺有利于将所述第一牺牲层300去除干净。
本实施例中，所述各向同性的刻蚀工艺包括等离子体化学反应基团刻蚀工艺或气相刻蚀工艺。
具体地，等离子体化学反应基团刻蚀工艺可以为Certas刻蚀工艺或SiCoNi刻蚀工艺，气相刻蚀工艺也可以为Certas刻蚀工艺或SiCoNi刻蚀工艺。
所述Certas刻蚀工艺或SiCoNi刻蚀工艺具有较好的各向同性特性，有利于去除干净所述第一牺牲层300，且所述Certas刻蚀工艺或SiCoNi刻蚀工艺能够具有较好的刻蚀选择比。
结合参考图11至图13，图11至图13为基于图9的剖视图，在所述第二沟槽250中形成隔离层510。
通过采用先形成第一牺牲层300为隔离层510占据空间位置，再去除所述第一牺牲层300，形成隔离层510的方法，有利于位于所述第一牺牲层300上的沟道结构200的生长，并且可以根据工艺需求灵活选用所述第一牺牲层300的材料，提高所述第一牺牲层300的工艺兼容性，此外，后续去除第二牺牲层220形成栅极结构后，所述栅极结构形成于所述隔离层510上，则所述隔离层510有效隔绝了所述栅极结构和基底100的接触，从而减小了所述栅极结构和基底100之间产生漏电流的概率，而且，相比于在基底中进行离子注入来隔绝栅极结构和基底的方案，本实施例能够避免因对基底100进行离子注入而引起的寄生电容变大的问题，综上所述皆有利于提高所述半导体结构的工作性能。
本实施例中，所述隔离层510的材料包括介电材料，所述介电材料能够对栅极结构和基底100起到隔绝作用，而且，介电材料的工艺兼容性高，从而减小所述隔离层510对工艺制程的影响。
本实施例中，所述隔离层510的材料包括氧化硅和氮化硅中的一种或多种，所述氧化硅和氮化硅有利于较好地隔绝栅极结构和基底100。
具体地，参考图11，在所述第二沟槽250中形成所述隔离层510的步骤包括：形成覆盖所述伪栅结构400的侧壁和顶部、所述沟道结构200侧壁、以及所述第一沟槽240露出的基底100顶部的隔离材料层500，所述隔离材料层500还填充于所述第二沟槽250中。
所述隔离材料层500用于形成隔离层510。
本实施例中，形成所述隔离材料层500的步骤中，采用原子层沉积工艺形成所述隔离材料层500。
采用原子层沉积工艺形成的所述隔离材料层500的厚度均匀性好，且具有良好的台阶覆盖（step coverage）能力，使得所述隔离材料层500能够在填充所述第二沟槽250的同时，很好地覆盖所述伪栅结构400的侧壁和顶部、所述沟道结构200侧壁。
相应的，所述隔离材料层500的材料包括介质材料，所述隔离材料层500的材料包括氧化硅和氮化硅中的一种或多种。
本实施例中，形成所述隔离材料层500的过程中，所述隔离材料层500还覆盖所述栅极侧墙410，从而在后续去除所述伪栅结构400侧壁的隔离材料层500的过程中，所述栅极侧墙410可以保护所述伪栅结构400的侧壁，从而保障后续栅极结构的形成质量。
本实施例中，相邻所述伪栅结构400的相对侧壁上的栅极侧墙410之间的距离d1，大于所述第一牺牲层300的厚度d2，因此，形成覆盖所述伪栅结构400的侧壁和顶部、所述沟道结构200侧壁、以及所述第一沟槽240露出的基底100顶部的隔离材料层500的过程中，相邻所述伪栅结构400侧壁的隔离材料层500之间具有间隙，有利于后续去除相邻所述伪栅结构400侧壁的隔离材料层500。
结合参考图12和图13，在所述第二沟槽250中形成所述隔离层510的步骤还包括：对所述隔离材料层500进行刻蚀，保留位于所述第二沟槽250中以及所述第一沟槽240露出的基底100顶部的剩余隔离材料层500作为隔离层510，且所述隔离层510露出所述沟道结构200的侧壁。
所述隔离层510露出所述沟道结构200的侧壁，为后续在所述第一沟槽240中形成源漏掺杂层做准备。
具体地，参考图12，对所述隔离材料层500进行刻蚀的步骤包括：对所述隔离材料层500进行第一刻蚀，去除位于相邻所述伪栅结构400之间，且靠近所述伪栅结构400顶部的部分高度的隔离材料层500，形成开口260。
所述开口260用于扩大去除相邻所述伪栅结构400之间的隔离材料层500的刻蚀工艺窗口，有利于后续去除高于所述沟道结构200底部的隔离材料层500。
本实施例中，对所述隔离材料层500进行第一刻蚀的步骤中，采用干法刻蚀工艺去除位于相邻所述伪栅结构400之间，且靠近所述伪栅结构400顶部的部分高度的隔离材料层500。
所述干法刻蚀工艺为各向异性的干法刻蚀工艺，因此通过选取干法刻蚀工艺，有利于在进行第一刻蚀的过程中，减小对所述开口260侧部的栅极侧墙410的损伤。
参考图13，对所述隔离材料层500进行刻蚀的步骤还包括：形成所述开口240后，对所述隔离材料层500进行第二刻蚀，去除高于所述沟道结构200底部的隔离材料层500。
进行第二刻蚀后，去除高于所述沟道结构200底部的剩余隔离材料层500，保留剩余所述隔离材料层500作为隔离层510。
本实施例中，对所述隔离材料层500进行第二刻蚀的步骤中，采用各向同性的刻蚀工艺去除高于所述沟道结构200底部的隔离材料层500。
所述第一沟槽240的深宽比较大，通过采用各向同性的刻蚀工艺有利于将高于所述沟道结构200底部的隔离材料层500去除干净。
本实施例中，所述各向同性的刻蚀工艺包括等离子体化学反应基团刻蚀工艺或气相刻蚀工艺。
具体地，等离子体化学反应基团刻蚀工艺可以为Certas刻蚀工艺或SiCoNi刻蚀工艺，气相刻蚀工艺也可以为Certas刻蚀工艺或SiCoNi刻蚀工艺。
所述Certas刻蚀工艺或SiCoNi刻蚀工艺具有较好的各向同性特性，有利于去除干净高于所述沟道结构200底部的隔离材料层500，且所述Certas刻蚀工艺或SiCoNi刻蚀工艺能够具有较好的刻蚀选择比。
需要说明的是，在进行第二刻蚀的过程中，通过控制刻蚀时间的方式，去除高于所述沟道结构200底部的隔离材料层500，直至露出所述沟道结构200底部的隔离材料层500顶面。
还需要说明的是，本实施例中，以进行所述第二刻蚀之后，高于所述沟道结构200底部的隔离材料层500被去除干净为例。在其他实施例中，在进行第二刻蚀后，所述第一沟槽的侧壁还可能留存有隔离材料层，此时，只需再加一道工序将高于所述沟道结构底部的隔离材料层去除干净。
参考图14，图14为基于图13的剖视图，形成所述隔离层510后，后续形成源漏掺杂层之前，还包括：沿垂直于所述伪栅结构400侧壁的方向，通过所述第一沟槽240，去除所述沟道结构200侧壁露出的部分所述第二牺牲层220，形成第三沟槽270。
所述第三沟槽270为后续形成内侧墙提供空间位置。
参考图15，图15为基于图14的剖视图，在所述第三沟槽270中形成内侧墙280。
所述内侧墙280起到隔离栅极结构和源漏掺杂层的作用，以减小栅极结构和源漏掺杂层之间的寄生电容。
所述内侧墙280的材料为绝缘材料。本实施例中，所述内侧墙280的材料包括氮化硅和碳氧化硅。
结合参考图16至图18，图16至图18为基于图15的剖视图，形成所述隔离层510后，在所述第一沟槽240中形成源漏掺杂层600。
具体地，形成所述内侧墙280后，在所述第一沟槽240中形成源漏掺杂层600。
所述源漏掺杂层600用于作为所形成晶体管的源区或漏区。
在所述第一沟槽240中，所述源漏掺杂层600以沟道层230作为外延生长基础进行外延生长，因此，本实施例中，形成所述源漏掺杂层600的步骤中，所述源漏掺杂层600与所述内侧墙280相接触。
所述源漏掺杂层600的掺杂类型与相对应的晶体管的沟道导电类型相同，具体地，当所述基底100用于形成NMOS晶体管时，所述源漏掺杂层600内的掺杂离子为N型离子，所述N型离子包括P离子、As离子或Sb离子；当所述基底100用于形成PMOS晶体管时，所述源漏掺杂层600内的掺杂离子为P型离子，所述P型离子包括B离子、Ga离子或In离子。
具体地，当所述基底100用于形成NMOS晶体管时，所述源漏掺杂层600的材料为掺杂有N型离子的Si或SiC，所述源漏掺杂层600为NMOS晶体管的沟道区提供拉应力作用，从而有利于提高NMOS晶体管的载流子迁移率；当所述基底用于形成PMOS晶体管时，所述源漏掺杂层600的材料为掺杂有P型离子的Si或SiGe，所述源漏掺杂层600为PMOS晶体管的沟道区提供压应力作用，从而有利于提高PMOS晶体管的载流子迁移率。
本实施例中，形成所述源漏掺杂层600的步骤中，在所述第一器件区100P中形成第一源漏掺杂层610，在所述第二器件区100N中形成第二源漏掺杂层620。
本实施例中，所述第一晶体管为PMOS晶体管，所述第一源漏掺杂层610中的P型离子为B离子，所述第一源漏掺杂层610的材料为掺杂有B离子的SiGe；所述第二晶体管为NMOS晶体管，所述第二源漏掺杂层620中的N型离子为P离子，所述第二源漏掺杂层620的材料为掺杂由P离子的Si。
具体地，参考图16，形成所述第一源漏掺杂层610和第二源漏掺杂层620的步骤包括：在所述第一器件区100P和第二器件区100N中，形成覆盖所述伪栅结构400的侧壁和顶部、以及第一沟槽240的侧壁和底部的保护层140。
所述保护层140用于保护所述第一沟槽240，能够减小后续形成的第一掩膜层对第二器件区100N中第一沟槽240的污染，从而减小对形成第二源漏掺杂层620的影响。
本实施例中，采用原子层沉积工艺形成所述保护层140，使得所述保护层140的厚度均匀性好，且原子层沉积工艺具有良好的台阶覆盖（step coverage）能力，使得所述保护层140能够很好地保形覆盖伪栅结构400的侧壁和顶部、以及第一沟槽240的侧壁和底部。
本实施例中，所述保护层的材料包括SiC、SiCO、SiCON、BN或BCN。
参考图17，形成所述第一源漏掺杂层610和第二源漏掺杂层620的步骤还包括：形成覆盖所述第二器件区100N中保护层140的第一掩膜层120，所述第一掩膜层120填充于所述第一沟槽240中，且所述第一掩膜层120露出所述第一器件区100P。
所述第一掩膜层120用于在形成所述第一源漏掺杂层610的过程中，遮盖所述第二器件区100N，保护所述第二器件区100N不受影响。
本实施例中，所述第一掩膜层120为叠层结构，所述第一掩膜层120包括平坦化层（未示出）以及位于所述平坦化层上的光刻胶层（未示出）。
本实施例中，所述平坦化层的材料包括旋涂碳（spin on carbon，SOC）材料。旋涂碳通过旋涂工艺所形成，工艺成本较低，同时，通过采用旋涂碳，有利于提高所述平坦化层的顶面平整度，从而为形成光刻胶层提供平坦面，进而提高光刻效果；此外，通过通过采用旋涂碳，无需采用化学机械研磨工艺进行平坦化处理，提高了工艺效率。
继续参考图17，形成所述第一掩膜层120后，去除位于所述第一器件区100P的保护层120；去除位于所述第一器件区100P的保护层120后，在所述第一器件区100P的第一沟槽240中形成第一源漏掺杂层610。
形成所述第一源漏掺杂层610后，去除所述第一掩膜层120和位于所述第二器件区100N中的保护层140，为形成第二源漏掺杂层620做准备。
参考图18，去除所述第一掩膜层120和位于所述第二器件区100N中的保护层140后，形成覆盖所述第二器件区100N的第二掩膜层130，所述第二掩膜层130覆盖所述第二源漏掺杂层620，且所述第二掩膜层130露出所述第二器件区100N。
所述第二掩膜层130用于在形成所述第二源漏掺杂层620的过程中，遮盖所述第一器件区100P，保护所述第一器件区100P不受影响。
形成所述第二掩膜层130的的步骤中，所述第二掩膜层130的材料包括SiN或SiNC，所SiN或SiNC能够与所述半导体结构的其他材料形成刻蚀选择比，使得在后续去除第二掩膜层130的过程中，减小对所述半导体结构的损伤。
继续参考图18，形成所述第二掩膜层130后，在所述第二器件区100N的第一沟槽240中形成第二源漏掺杂层620。
形成所述第二源漏掺杂层620后，去除所述第二掩膜层130，为形成栅极结构做准备。
参考图19，去除所述伪栅结构400，形成栅极开口（未示出）；通过所述栅极开口去除所述第二牺牲层220；去除所述第二牺牲层220后，在所述栅极开口中形成栅极结构700，所述栅极结构700包括沿所述栅极结构700延伸方向环绕所述沟道层230的栅介质层710、以及位于所述栅介质层710上的栅电极层720。
所述栅极结构700用于控制晶体管的沟道的开启或关断。
所述栅极结构700包覆所述沟道层230，则所述沟道层230的顶部、底部和侧壁均能够作为沟道，增大了沟道层230中用于作为沟道的面积，从而增大了所述半导体结构的工作电流。
所述栅介质层710用于隔离栅电极层720与沟道层230、以及栅电极层720与基底100。
所述栅介质层710的材料包括HfO2、ZrO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、SiO2和La2O3中的一种或多种。本实施例中，所述栅介质层710包括高k栅介质层，高k栅介质层的材料包括高k介质材料。其中，高k介质材料是指相对介电常数大于氧化硅相对介电常数的介质材料。具体地，所述高k栅介质层的材料包括HfO2、ZrO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO或Al2O3等。
需要说明的是，栅介质层710还可以包括栅氧化层，栅氧化层位于高k栅介质层和沟道层230之间。具体地，栅氧化层的材料可以为氧化硅。
本实施例中，所述栅极结构700为金属栅极结构，因此，所述栅电极层720的材料包括TiN、TaN、Ta、Ti、TiAl、W、AL、TiSiN和TiAlC中的一种或多种。
具体地，所述栅电极层720包括功函数层（未示出）、以及位于功函数层上的电极层（未示出）。其中，所述功函数层用于调节晶体管的阈值电压，所述电极层用于将金属栅极结构的电性引出。
在另一些实施例中，栅电极层也可以仅包括功函数层。
在其他实施例中，根据工艺需求，所述栅极结构也可以为多晶硅栅结构。
图20至图21是本发明半导体结构的形成方法另一实施例中各步骤对应的结构示意图。
本实施例与前述实施例的相同之处，在此不再赘述。本实施例与前述实施例的不同之处在于：所述隔离层512露出所述基底102顶面。
参考图20，形成所述隔离层512之后，形成所述源漏掺杂层之前，还包括：去除所述第一沟槽242底部的隔离层512，露出所述第一沟槽242底部的基底102顶面。
去除所述第一沟槽242底部的隔离层512，露出所述基底102顶面，为形成所述源漏掺杂层做准备，使得所述源漏掺杂层能够在所述基底102顶面生长，从而提高所述源漏掺杂层的生长速率和形成质量。
本实施例中，去除所述第一沟槽242底部的隔离层512的步骤中，采用干法刻蚀工艺去除所述第一沟槽242底部的隔离层512。
所述干法刻蚀工艺为各向异性的干法刻蚀工艺，因此通过选取干法刻蚀工艺，有利于减小对所述第一沟槽242底部所述基底102的损伤，同时，所述干法刻蚀更具刻蚀方向性，有利于提高剩余隔离层512的侧壁形貌质量和尺寸精度。
需要说明的是，在去除相邻所述伪栅结构402之间高于所述沟道结构202底部的隔离材料层之后，如果所述第一沟槽242侧壁还留存部分所述隔离材料层未去除干净，可以在去除所述第一沟槽242底部的隔离层512的工序中，进一步去除相邻所述伪栅结构402之间高于所述沟道结构202底部的隔离材料层，将高于所述沟道结构202底部的隔离材料层去除干净。
参考图21，在所述第一沟槽242中形成源漏掺杂层602的过程中，所述源漏掺杂层602与所述基底102顶面相接触。
在相邻所述源漏掺杂层602通过所述隔离层512进行有效隔离的同时，所述源漏掺杂层602与基底102相接触，有利于增加所述源漏掺杂层602的生长速率，并提升所述源漏掺杂层602的生长质量，减少生长过程中产生的缺陷。
对本实施例所述形成方法的具体描述，可结合参考前述实施例中的相应描述，在此不再赘述。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (28)

  1.       一种半导体结构，其特征在于，包括：
    基底，包括沟道区，所述基底表面的法线方向为纵向；
    隔离层，位于所述沟道区的基底上；
    沟道层结构，位于所述沟道区且悬置于所述隔离层上方，在所述纵向上，所述沟道层结构包括一个或多个间隔的沟道层；
    栅极结构，位于所述基底上且横跨所述沟道层结构，所述栅极结构包括沿所述栅极结构延伸方向环绕所述沟道层的栅介质层、以及位于所述栅介质层上的栅电极层，在所述沟道区中，所述栅极结构位于所述隔离层上；
    源漏掺杂层，位于所述栅极结构两侧的基底上，在所述沟道层结构的延伸方向上，所述源漏掺杂层与所述沟道层结构的端部、以及所述隔离层的端部相接触。
  2.       如权利要求1所述的半导体结构，其特征在于，所述半导体结构还包括：内侧墙，在所述纵向上，所述内侧墙位于相邻所述沟道层之间、以及底部的沟道层与隔离层之间，在所述沟道层结构的延伸方向上，所述内侧墙位于所述栅极结构和源漏掺杂层之间。
  3.       如权利要求1所述的半导体结构，其特征在于，所述半导体结构还包括：栅极侧墙，覆盖所述栅极结构的侧壁；
    相邻所述栅极结构的相对侧壁上的栅极侧墙之间的距离，大于所述隔离层的厚度。
  4.       如权利要求1所述的半导体结构，其特征在于，所述隔离层的材料包括介电材料。
  5.       如权利要求1所述的半导体结构，其特征在于，所述隔离层的材料包括氧化硅和氮化硅中的一种或多种。
  6.       如权利要求1所述的半导体结构，其特征在于，所述隔离层的厚度为5nm至15nm。
  7.       如权利要求1所述的半导体结构，其特征在于，所述沟道层的材料包括硅、锗、锗化硅或Ⅲ-Ⅴ族半导体材料。
  8.       如权利要求1所述的半导体结构，其特征在于，所述栅介质层的材料包括HfO2、ZrO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、SiO2和La2O3中的一种或多种；所述栅电极层的材料包括TiN、TaN、Ta、Ti、TiAl、W、AL、TiSiN和TiAlC中的一种或多种。
  9.       一种半导体结构的形成方法，其特征在于，包括：
    提供基底，所述基底上形成有第一牺牲层，所述第一牺牲层上形成有沟道结构，所述沟道结构包括一个或多个堆叠的沟道叠层，所述沟道叠层包括第二牺牲层和位于所述第二牺牲层上的沟道层，所述基底上还形成有横跨所述沟道结构的伪栅结构，所述伪栅结构覆盖所述沟道结构的部分侧壁和部分顶部，其中，所述第一牺牲层的耐刻蚀度小于第二牺牲层的耐刻蚀度；
    去除所述伪栅结构两侧的沟道结构和第一牺牲层，形成贯穿所述沟道结构和第一牺牲层的第一沟槽；
    通过所述第一沟槽去除所述沟道结构底部的第一牺牲层，在所述沟道结构底部形成与所述第一沟槽相连通的第二沟槽；
    在所述第二沟槽中形成隔离层；
    形成所述隔离层后，在所述第一沟槽中形成源漏掺杂层。
  10.    如权利要求9所述的半导体结构的形成方法，其特征在于，在所述第二沟槽中形成所述隔离层的步骤包括：形成覆盖所述伪栅结构的侧壁和顶部、所述沟道结构侧壁、以及所述第一沟槽露出的基底顶部的隔离材料层，所述隔离材料层还填充于所述第二沟槽中；
    对所述隔离材料层进行刻蚀，保留位于所述第二沟槽中以及所述第一沟槽露出的基底顶部的剩余隔离材料层作为隔离层，且所述隔离层露出所述沟道结构的侧壁。
  11.    如权利要求10所述的半导体结构的形成方法，其特征在于，对所述隔离材料层进行刻蚀的步骤包括：对所述隔离材料层进行第一刻蚀，去除位于相邻所述伪栅结构之间，且靠近所述伪栅结构顶部的部分高度的隔离材料层，形成开口；
    形成所述开口后，对所述隔离材料层进行第二刻蚀，去除高于所述沟道结构底部的隔离材料层。
  12.    如权利要求10所述的半导体结构的形成方法，其特征在于，形成所述隔离层之后，形成所述源漏掺杂层之前，还包括：去除所述第一沟槽底部的隔离层，露出所述基底顶面；
    在所述第一沟槽中形成源漏掺杂层的过程中，所述源漏掺杂层与所述基底顶面相接触。
  13.    如权利要求10所述的半导体结构的形成方法，其特征在于，所述提供基底的步骤中，所述基底上还形成有覆盖所述伪栅结构的顶部和侧壁的栅极侧墙；
    形成所述隔离材料层的过程中，所述隔离材料层还覆盖所述栅极侧墙。
  14.    如权利要求13所述的半导体结构的形成方法，其特征在于，所述提供基底的步骤中，相邻所述伪栅结构的相对侧壁上的栅极侧墙之间的距离，大于所述第一牺牲材料层的厚度；
    形成覆盖所述伪栅结构的侧壁和顶部、所述沟道结构侧壁、以及所述第一沟槽露出的基底顶部的隔离材料层的过程中，相邻所述伪栅结构侧壁的隔离材料层之间具有间隙。
  15.    如权利要求9所述的半导体结构的形成方法，其特征在于，形成所述隔离层后，形成所述源漏掺杂层之前，还包括：沿垂直于所述伪栅结构侧壁的方向，通过所述第一沟槽，去除所述沟道结构侧壁露出的部分所述第二牺牲层，形成第三沟槽；
    在所述第三沟槽中形成内侧墙；
    形成所述源漏掺杂层的步骤中，所述源漏掺杂层与所述内侧墙相接触。
  16.    如权利要求9所述的半导体结构的形成方法，其特征在于，所述提供基底的步骤中，所述基底包括用于形成第一晶体管的第一器件区和用于形成第二晶体管的第二器件区；
    形成所述源漏掺杂层的步骤中，在所述第一器件区中形成第一源漏掺杂层，在所述第二器件区中形成第二源漏掺杂层；
    形成所述第一源漏掺杂层和第二源漏掺杂层的步骤包括：在所述第一器件区和第二器件区中，形成覆盖所述伪栅结构的侧壁和顶部、以及第一沟槽的侧壁和底部的保护层；
    形成覆盖所述第二器件区中保护层的第一掩膜层，所述第一掩膜层填充于所述第一沟槽中，且所述第一掩膜层露出所述第一器件区；
    形成所述第一掩膜层后，去除位于所述第一器件区的保护层；
    去除位于所述第一器件区的保护层后，在所述第一器件区的第一沟槽中形成第一源漏掺杂层；
    形成所述第一源漏掺杂层后，去除所述第一掩膜层和位于所述第二器件区中的保护层；
    去除所述第一掩膜层和位于所述第二器件区中的保护层后，形成覆盖所述第一器件区的第二掩膜层，所述第二掩膜层覆盖所述第一源漏掺杂层，且所述第二掩膜层露出所述第二器件区；
    形成所述第二掩膜层后，在所述第二器件区的第一沟槽中形成第二源漏掺杂层；
    形成所述第二源漏掺杂层后，去除所述第二掩膜层。
  17.    如权利要求9所述的半导体结构的形成方法，其特征在于，去除所述伪栅结构两侧的沟道结构和第一牺牲层的步骤中，采用干法刻蚀工艺去除所述伪栅结构两侧的沟道结构和第一牺牲层。
  18.    如权利要求9所述的半导体结构的形成方法，其特征在于，通过所述第一沟槽去除所述第一牺牲层的步骤中，采用各向同性的刻蚀工艺去除所述第一牺牲层。
  19.    如权利要求10所述的半导体结构的形成方法，其特征在于，形成所述隔离材料层的步骤中，采用原子层沉积工艺形成所述隔离材料层。
  20.    如权利要求11所述的半导体结构的形成方法，其特征在于，对所述隔离材料层进行第一刻蚀的步骤中，采用干法刻蚀工艺去除位于相邻所述伪栅结构之间，且靠近所述伪栅结构顶部的部分高度的隔离材料层。
  21.    如权利要求11所述的半导体结构的形成方法，其特征在于，对所述隔离材料层进行第二刻蚀的步骤中，采用各向同性的刻蚀工艺去除高于所述沟道结构底部的隔离材料层。
  22.    如权利要求12所述的半导体结构的形成方法，其特征在于，去除所述第一沟槽底部的隔离层的步骤中，采用干法刻蚀工艺去除所述第一沟槽底部的隔离层。
  23.    如权利要求9所述的半导体结构的形成方法，其特征在于，所述第一牺牲层和第二牺牲层的刻蚀选择比大于10。
  24.    如权利要求9所述的半导体结构的形成方法，其特征在于，所述提供基底的步骤中，所述第一牺牲层的材料包括半导体材料。
  25.    如权利要求9所述的半导体结构的形成方法，其特征在于，所述第一牺牲层的材料包括Si1-yGey，所述第二牺牲层的材料包括Si1-xGex，其中，x＜y。
  26.    如权利要求25所述的半导体结构的形成方法，其特征在于，在所述第一牺牲层的材料Si1-yGey中，y≥0.4；在所述第二牺牲层的材料Si1-xGex中，0.1≤x≤0.5。
  27.    如权利要求9所述的半导体结构的形成方法，其特征在于，所述形成隔离层的步骤中，所述隔离层的材料包括介电材料。
  28.    如权利要求16所述的半导体结构的形成方法，其特征在于，形成所述保护层的步骤中，所述保护层的材料包括SiC、SiCO、SiCON、BN或BCN；形成所述第一掩膜层的的步骤中，所述第一掩膜层的材料包括SOC；形成所述第二掩膜层的的步骤中，所述第二掩膜层的材料包括SiN或SiNC。
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