CN104347707A - 一种mosfet结构及其制造方法 - Google Patents

一种mosfet结构及其制造方法 Download PDF

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CN104347707A
CN104347707A CN201310339819.6A CN201310339819A CN104347707A CN 104347707 A CN104347707 A CN 104347707A CN 201310339819 A CN201310339819 A CN 201310339819A CN 104347707 A CN104347707 A CN 104347707A
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尹海洲
张珂珂
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Institute of Microelectronics of CAS
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Abstract

本发明提供一种MOSFET制造方法，包括：a.提供衬底（100）；b.在衬底上形成伪栅堆叠及其侧墙（104）、源/漏区和层间介质层（105）；c.去除所述伪栅堆叠以形成伪栅空位；d.在伪栅空位下方的衬底中形成第一掺杂阱(200)；e.在靠近漏区的伪栅空位下方的衬底中形成第二掺杂阱(300)；f.对所述器件进行退火，以激活掺杂；g.在所述开口中沉积栅极介质层（201）、功函数调节层（202）和栅极金属层（203）。本发明的方法制造的MOSFET能够有效地抑制了短沟道效应的不良影响，提高了器件性能。

Description

一种MOSFET结构及其制造方法
技术领域
本发明涉及一种MOSFET结构及其制造方法。更具体而言，涉及一种用于在栅堆叠下方的半导体衬底中形成具有陡峭的倒掺杂阱的MOSFET结构及其制造方法。
技术背景
随着半导体行业的发展，具有更高性能和更强功能的集成电路要求更大的元件密度，而且各个部件、元件之间或各个元件自身的尺寸、大小和空间也需要进一步缩小。相应地，为了提高MOSFET(金属氧化物半导体场效应晶体管)器件的性能，需要进一步减少MOSFET器件的栅长。然而随着栅长持续减小，减少到接近源极和漏极的耗尽层的宽度，例如小于40nm时，将会产生较严重的短通道效应(short channel effect或简写为SCE)，从而不利地降低器件的性能，给大规模集成电路的生产造成困难。如何降低短通道效应以及有效地控制短通道效应，已经成为集成电路大规模生产中的一个很关键的问题。
现有方案一般是基于在沟道中形成陡峭的倒掺杂阱以减小栅极下耗尽层的厚度，进而减少短通道效应。然而随着沟道尺寸的进一步减小，漏端感应势垒降低效应（Drain Induction Barrier Lower）、载流子迁移率随着沟道厚度的减小而降低等因素对器件特性的影响越来越严重。
因此，为了平衡沟道宽度对载流子迁移率和DIBL效应的影响，优化器件性能，本发明提供了一种MOSFET结构及其制造方法，其沟道区下方靠近源端部分的倒掺杂阱距离沟道表面的深度是靠近漏端部分的倒掺杂阱距离沟道表面的深度的1至3倍，且其深掺杂部分的长度是浅掺杂部分的长度的1至3倍。也就是说，在靠近源端的地方，主要考虑沟道宽度对迁移率的影响，掺杂深度较大；而在靠近漏端的地方，由于沟道宽度对载流子迁移率的影响不大，因此为了降低DIBL的影响，掺杂深度较小。与现有技术相比，本发明有效地抑制了短沟道效应的不良影响，提高了器件性能。
发明内容
本发明提供了一种非对称MOSFET结构及其制作方法，有效抑制了器件的短沟道效应，提高了器件性能。具体地，本发明提供的制造方法包括以下步骤：
a.提供衬底；
b.在衬底上形成伪栅堆叠及其侧墙、源/漏区和层间介质层；
c.去除所述伪栅堆叠以形成伪栅空位；
d.在伪栅空位下方的衬底中形成第一掺杂阱；
e.在靠近漏区的伪栅空位下方的衬底中形成第二掺杂阱；
f.对所述器件进行退火，以激活掺杂；
g.在所述开口中沉积栅极介质层、功函数调节层和栅极金属层。
其中，所述第一掺杂阱的形成方式是：对所述伪栅空位下方的衬底进行离子注入，所述离子注入的方向与衬底垂直。
其中，所述第一掺杂阱位于伪栅空位下方35～45nm处的衬底中。
其中，所述第二掺杂阱的形成方法是：在靠近源端的伪栅空位中形成掩膜，对所述伪栅空位下方未被掩膜覆盖的衬底进行离子注入，所述离子注入的方向与衬底垂直。
其中，所述第二掺杂阱的形成方法是：以侧墙为掩膜，对所述伪栅空位下方的衬底进行入射角为α的离子注入，其中，所述离子注入区域位于侧墙下方的部分不超过侧墙的边界。
其中，所述侧墙的高度不小于L/tanα，其中L为伪第一掺杂阱与第二掺杂阱之间的长度差。
其中，所述第二掺杂阱位于靠近漏区的伪栅空位下方15～25nm处的衬底中，所述第二掺杂阱的长度为第一掺杂阱长度的1/4～1/2。
其中，所述离子注入的类型与衬底相同，浓度5e17cm-3～1e19cm-3。
相应的，本发明提供了一种MOSFET结构，包括：衬底、侧墙、源区和漏区、栅极介质层、功函数调节层、栅极金属层、第一掺杂阱和第二掺杂阱，其中，所述第一掺杂阱和第二掺杂阱的掺杂类型与衬底相同。
其中，所述第一掺杂阱位于栅极下方35～45nm处的衬底中，所述第二掺杂阱位于靠近漏区的栅极下方15～25nm处的衬底中。
其中，所述侧墙的高度不小于L/tanα，其中L为伪第一掺杂阱与第二掺杂阱之间的长度差。
其中，所述第二掺杂阱的长度为第一掺杂阱长度的1/4～1/2。
根据本发明提供的MOSFET结构及其制造方法，其沟道区下方靠近源端部分的倒掺杂阱距离沟道表面的深度是靠近漏端部分的倒掺杂阱距离沟道表面的深度的1至3倍，且其深掺杂部分的长度是浅掺杂部分的长度的1至3倍。也就是说，在靠近源端的地方，主要考虑沟道宽度对迁移率的影响，掺杂深度较大；而在靠近漏端的地方，由于沟道宽度对载流子迁移率的影响不大，因此为了降低DIBL的影响，掺杂深度较小。与现有技术相比，本发明有效地抑制了短沟道效应的不良影响，提高了器件性能。
附图说明
图1至图7示意性地示出了形成根据本发明的制造方法各阶段半导体结构的剖面图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明的实施例作详细描述。
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
本发明提供了一种非对称MOSFET结构，包括：包括：衬底100、侧墙104、源区和漏区、栅极介质层201、功函数调节层202、栅极金属层203、第一掺杂阱200和第二掺杂阱300，其中，所述第一掺杂阱200和第二掺杂阱300的掺杂类型与衬底相同。
栅结构包括栅极介质层201、功函数调节层202、栅极金属层203、和一对位于该栅极叠层两侧的绝缘介质侧墙104。栅介质层201优选材料为氮氧化硅，也可为氧化硅或高K材料。其等效氧化厚度为0.5nm～5nm。栅极金属层203可以只为金属栅极，也可以为金属/多晶硅复合栅极，其中多晶硅上表面上具有硅化物。
半导体沟道区位于衬底100的表面，其优选材料为单晶硅或单晶锗合金薄膜，其厚度为5～20nm。该区域是极轻掺杂甚至未掺杂的。在掺杂的情况下，其掺杂类型与源漏区掺杂相反。
源区和漏区分别位于栅极叠层两侧，衬底100内。源区与漏区相对称，其掺杂类型与衬底相反。
第一掺杂阱200位于栅极下方35～45nm处的衬底中，第二掺杂阱300位于靠近漏区的栅极下方15～25nm处的衬底中。第二掺杂阱300的长度为第一掺杂阱200长度的1/4～1/2。
侧墙104的高度不小于L/tanα，其中L为伪第一掺杂阱200与第二掺杂阱300之间的长度差。
下面结合附图对本发明的制作方法进行详细说明，包括以下步骤。需要说明的是，本发明各个实施例的附图仅是为了示意的目的，因此没有必要按比例绘制。
首先提供衬底，并在所述衬底上形成栅极介质层103。所述栅极介质层103可以是热氧化层，包括氧化硅、氮氧化硅；也可为高K介质，例如HfAlON、HfSiAlON、HfTaAlON、HfTiAlON、HfON、HfSiON、HfTaON、HfTiON、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合，栅极介质层301的厚度可以为1nm-10nm，例如3nm、5nm或8nm。可以采用热氧化、化学气相沉积（CVD）或原子层沉积（ALD）等工艺来形成栅极介质层103。
接下来，在所述栅极介质层上形成伪栅结构102。所述伪栅结构102可以是单层的，也可以是多层的。伪栅结构102可以包括聚合物材料、非晶硅、多晶硅或TiN，厚度可以为10nm～200nm。本是实例中，伪栅结构包括多晶硅和二氧化，具体的，采用化学汽相淀积的方法在栅极空位中填充多晶硅，接着在多晶硅上方形成一层二氧化硅介质层，形成方法可以是外延生长、氧化、CVD等。接着采用常规CMOS工艺光刻和刻蚀所淀积的伪栅叠层形成栅电极图形，然后以栅电极图形为掩膜腐蚀掉栅极介质层103的裸露部分。需说明地是，以下若无特别说明，本发明实施例中各种介质材料的淀积均可采用上述所列举的形成栅介质层相同或类似的方法，故不再赘述。
接下来，对伪栅结构两侧的衬底100进行浅掺杂，以形成轻掺杂源漏区，还可以进行Halo注入，以形成Halo注入区。其中浅掺杂的杂质类型与器件类型一致，Halo注入的杂质类型与器件类型相反。
可选地，在栅极堆叠的侧壁上形成侧墙104，用于将栅极隔开。具体的，用LPCVD淀积40nm～80nm厚的牺牲侧墙介质层氮化硅，接着用会客技术再栅电极两侧形成宽度为35nm～75nm的氮化硅侧墙104。侧墙104还可以由氧化硅、氮氧化硅、碳化硅及其组合，和/或其他合适的材料形成。侧墙104可以具有多层结构。侧墙104还可以通过包括沉积刻蚀工艺形成，其厚度范围可以是10nm-100nm，如30nm、50nm或80nm。
接下来，在所述半导体结构上淀积一层厚度为10nm～35nm厚的二氧化硅介质层，形成层间介质层105，并以该介质层为缓冲层，离子注入源漏区。对P型晶体而言，掺杂剂为硼或弗化硼或铟或镓等。对N型晶体而言，掺杂剂为磷或砷或锑等。掺杂浓度为5e1019cm-3～1e1020cm-3。完成掺杂之后的半导体结构如图1所示。
接下来，去除所述伪栅结构，形成伪栅空位，如图2所示。去除伪栅结构可以采用湿刻和/或干刻除去。在一个实施例中，采用等离子体刻蚀。
接下来，如图3所示，在伪栅空位下方的衬底中形成第一掺杂阱200。具体的，对所述半导体结构进行垂直的离子注入，在伪栅空位下方35～45nm处的衬底中形成具有一定浓度分布的掺杂区域，所述掺杂区域的类型与衬底相同，为了很好地抑制短沟道效应，在衬底中形成倒掺杂阱200，所述离子注入形成的掺杂浓度最高值为5e17cm-3～1e19cm-3。
接下来，在靠近漏区的伪栅空位下方的衬底中形成第二掺杂阱300，所述第二掺杂阱位于靠近漏区的伪栅空位下方15～25nm处的衬底中，所述第二掺杂阱的长度为第一掺杂阱长度的1/4～1/2。
具体的，如图4所示，形成第二掺杂阱300的方法可以是：在靠近源端的伪栅空位中形成掩膜106，对所述伪栅空位下方未被掩膜覆盖的衬底进行离子注入。所述掩膜106可以是光刻胶，具体的，在所述伪栅空位中填充光刻胶，通过掩膜板进行曝光、显影、去胶的工艺过程去除靠近漏端一侧的光刻胶，暴露出衬底100，去除的光刻胶长度等于所需第二掺杂阱的长度。其中，所述离子注入的方向与衬底垂直，通过控制离子注入的剂量和能量，则可在未被光刻胶覆盖的半导体衬底100下方形成第二掺杂阱300，如图5所示。之后去除掩膜106，露出衬底100。
可选的，如图6所示，形成第二掺杂阱300的方法还可以是：以侧墙为掩膜，对所述伪栅空位下方的衬底进行入射角为α的离子注入，其中，所述离子注入区域位于侧墙下方的部分不超过侧墙的边界。也就是说，倾斜注入衬底中的掺杂离子沿沿与沟道平行的方向进入衬底中的最远距离不超过侧墙104与层间介质层相邻的边界，避免第二掺杂阱300与漏区相连而对器件产生的一些不良影响。同时，根据靠近漏端一侧的离子注入范围可确定离子注入的倾斜角度α。需要注意的是，为了确保第二掺杂阱300的长度在我们需要的范围之内，根据数学关系，在此处作为掩膜的侧墙高度必须不小于L/tanα，其中L为伪第一掺杂阱与第二掺杂阱之间的长度差。
第二掺杂阱300形成之后，在栅极空位中依次形成栅极介质层201、功函数调节层202和栅极金属层203。栅极金属层203可以只为金属栅极，也可以为金属/多晶硅复合栅极，其中多晶硅上表面上具有硅化物。具体的如图7所示，优选的，在栅极介质层201上先沉积功函数金属层，之后再在功函数金属层之上形成金属导体层。功函数金属层可以采用TiN、TaN等材料制成，其厚度范围为3nm～15nm。金属导体层可以为一层或者多层结构。其材料可以为TaN、TaC、TiN、TaAlN、TiAlN、MoAlN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax中的一种或其组合。其厚度范围例如可以为10nm-40nm，如20nm或30nm。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。

Claims (14)

1.一种MOSFET制造方法，包括：
a.提供衬底（100）；
b.在衬底上形成伪栅堆叠及其侧墙（104）、源/漏区和层间介质层（105）；
c.去除所述伪栅堆叠以形成伪栅空位；
d.在伪栅空位下方的衬底中形成第一掺杂阱(200)；
e.在靠近漏区的伪栅空位下方的衬底中形成第二掺杂阱(300)；
f.对所述器件进行退火，以激活掺杂；
g.在所述开口中沉积栅极介质层（201）、功函数调节层（202）和栅极金属层（203）。
2.根据权利要求1所述的制造方法，其特征在于，所述第一掺杂阱(200)的形成方式是：对所述伪栅空位下方的衬底（100）进行离子注入，所述离子注入的方向与衬底（100）垂直。
3.根据权利要求1和2所述的制造方法，其特征在于，所述第一掺杂阱（200）位于伪栅空位下方35～45nm处的衬底中。
4.根据权利要求1所述的制造方法，其特征在于，所述第二掺杂阱（300）的形成方法是：在靠近源端的伪栅空位中形成掩膜（106），对所述伪栅空位下方未被掩膜（106）覆盖的衬底（100）进行离子注入，所述离子注入的方向与衬底（100）垂直。
5.根据权利要求1所述的制造方法，其特征在于，所述第二掺杂阱（300）的形成方法是：以侧墙（104）为掩膜，对所述伪栅空位下方的衬底（100）进行入射角为α的离子注入，其中，所述离子注入区域位于侧墙（104）下方的部分不超过侧墙（104）的边界。
6.根据权利要求1和5所述的制造方法，其特征在于,所述侧墙（104）的高度不小于L/tanα，其中L为伪第一掺杂阱(200)与第二掺杂阱（300）之间的长度差。
7.根据权利要求1所述的制造方法，其特征在于，所述第二掺杂阱（300）位于靠近漏区的伪栅空位下方15～25nm处的衬底中。
8.根据权利要求1、3和4所述的制造方法，其特征在于，所述第二掺杂阱（300）的长度为第一掺杂阱（200）长度的1/4～1/2。
9.根据权利要求1、2、3和4所述的制造方法，其特征在于，所述离子注入的类型与衬底相同，浓度为5e17cm-3～1e19cm-3。
10.一种MOSFET结构，包括：衬底（100）、侧墙（104）、源区和漏区、栅极介质层（201）、功函数调节层（202）、栅极金属层（203）、第一掺杂阱（200）和第二掺杂阱（300），其中，所述第一掺杂阱（200）和第二掺杂阱（300）的掺杂类型与衬底（100）相同。
11.根据权利要求10所述的制造方法，其特征在于，所述第一掺杂阱（200）位于栅极下方35～45nm处的衬底中。
12.根据权利要求10所述的制造方法，其特征在于，所述第二掺杂阱（300）位于靠近漏区的栅极下方15～25nm处的衬底中。
13.根据权利要求10所述的制造方法，其特征在于,所述侧墙（104）的高度不小于L/tanα，其中L为伪第一掺杂阱(200)与第二掺杂阱（300）之间的长度差。
14.根据权利要求10和12所述的制造方法，其特征在于，所述第二掺杂阱（300）的长度为第一掺杂阱（200）长度的1/4～1/2。
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