WO2015196639A1 - 一种FinFET制造方法 - Google Patents
一种FinFET制造方法 Download PDFInfo
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- WO2015196639A1 WO2015196639A1 PCT/CN2014/088594 CN2014088594W WO2015196639A1 WO 2015196639 A1 WO2015196639 A1 WO 2015196639A1 CN 2014088594 W CN2014088594 W CN 2014088594W WO 2015196639 A1 WO2015196639 A1 WO 2015196639A1
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- forming
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000010410 layer Substances 0.000 claims abstract description 88
- 238000009792 diffusion process Methods 0.000 claims abstract description 45
- 238000002955 isolation Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 238000011049 filling Methods 0.000 claims abstract description 5
- 239000012535 impurity Substances 0.000 claims description 58
- 230000004888 barrier function Effects 0.000 claims description 38
- 238000005468 ion implantation Methods 0.000 claims description 10
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 54
- 238000009826 distribution Methods 0.000 abstract description 9
- 230000008569 process Effects 0.000 description 30
- 239000004065 semiconductor Substances 0.000 description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 230000000903 blocking effect Effects 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000002245 particle Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
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- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004143 HfON Inorganic materials 0.000 description 1
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 1
- 241000849798 Nita Species 0.000 description 1
- 235000003976 Ruta Nutrition 0.000 description 1
- 240000005746 Ruta graveolens Species 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910004491 TaAlN Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
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- 238000011065 in-situ storage Methods 0.000 description 1
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- 239000002356 single layer Substances 0.000 description 1
- 238000001894 space-charge-limited current method Methods 0.000 description 1
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- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
Definitions
- the present invention relates to a method of fabricating a semiconductor device, and in particular to a method of fabricating a FinFET.
- the channel punch-through effect is a phenomenon in which the source junction of the field effect transistor is connected to the depletion region of the drain junction.
- the potential/drain barrier is significantly reduced, and a large number of carriers are injected from the source to the channel, and drifts through the space-charge region between the source and the drain to form a large current;
- the magnitude of this current will be limited by the space charge, which is the so-called space charge limited current.
- This space charge limiting current is in parallel with the gate voltage controlled channel current, so channel passthrough will greatly increase the total current through the device; and in the case of channel punchthrough, even if the gate voltage is below the threshold voltage, the source - There will also be current flow through the drain.
- This effect is an effect that may occur in small-sized field effect transistors, and as the channel width is further reduced, its influence on device characteristics is also becoming more and more significant.
- a through-pass barrier (PTSL) is formed to suppress the channel punch-through effect.
- PTSL through-pass barrier
- the PTSL formed by this method is concentrated and does not introduce defects into the channel, which significantly improves device performance.
- the invention provides a FinFET manufacturing method, which effectively optimizes the PTSL distribution, so that it is well concentrated in the place where the punch-through current is generated, suppresses its diffusion to the channel, does not affect other properties of the device, and does not increase the process. the complexity. Specifically, the method includes:
- a FinFET manufacturing method comprising:
- the through barrier layer and the diffusion barrier layer are formed by lateral scattering of impurity particles from the isolation layer into the fins during ion implantation.
- the impurity forming the through-barrier layer is boron; the impurity forming the diffusion barrier region is carbon; and the implantation dose of the diffusion barrier region is 1.5e15 cm -2 - 7.5e15 cm -2 .
- the impurity forming the punch-through barrier layer is phosphorus; the impurity forming the diffusion barrier region is ruthenium; and the implantation dose of the diffusion barrier region is 3e14 cm -2 - 1.5e15 cm -2 .
- the method provided by the present invention that is, in the process of forming PTSL by side scatter, when implanting PTSL impurities, simultaneously injecting corresponding diffusion to prevent impurities, for N-type devices, impurities forming PTSL are generally B, and corresponding diffusion
- the blocking impurity is C; for the P-type device, the impurity forming PTSL is generally P, and the corresponding diffusion blocking impurity is Ge.
- Diffusion blocking impurities can effectively suppress Diffusion of impurities to avoid redistribution of PTSL in subsequent processes and optimize device performance.
- the PTSL can be effectively distributed in the region where the punch-through current occurs under the existing process conditions without introducing impurity distribution in the channel, effectively optimizing the PTSL process and improving device performance.
- FIG. 1 to 4 are schematic cross-sectional views showing a semiconductor structure in various stages of a method of fabricating a semiconductor fin according to the present invention; wherein FIG. 1 is a cross-sectional view showing a semiconductor structure after a fin forming step;
- Figure 2 is a cross-sectional view showing the isolation layer formed on the substrates on both sides of the fin;
- FIG. 3 is a schematic view showing a step of forming a through-barrier layer and a diffusion barrier layer in fins on both sides of the upper half of the isolation layer;
- FIG. 4 shows a schematic view of the through-barrier layer and the diffusion barrier layer formed by side-scattering of impurity particles from the isolation layer into the fins by ion implantation.
- Figure 5 is a schematic illustration of a three-dimensional isometric view of a semiconductor structure at various stages of a method of fabricating a semiconductor fin in accordance with the present invention.
- the present invention provides a FinFET manufacturing method in which PTSL is effectively distributed in a region where a punch-through current occurs without introducing an impurity distribution in the channel.
- the method includes:
- a substrate 100 is provided, and fins 200 are formed on the substrate;
- the through-barrier layer 310 and the diffusion barrier layer 320 are formed by lateral scattering of the impurity particles from the isolation layer 300 into the fins 200 during ion implantation.
- the impurity forming the through-barrier layer 310 is boron; the impurity forming the diffusion barrier region 320 is carbon; and the implantation dose of the diffusion barrier region 320 is 1.5e15 cm -2 -7.5e15 cm -2 .
- the impurity forming the through-barrier layer 310 is phosphorus; the impurity forming the diffusion barrier region 320 is germanium; and the diffusion barrier region 203 is implanted at a dose of 3e14 cm -2 - 1.5e15 cm -2 .
- the method provided by the present invention that is, in the process of forming PTSL by side scatter, when implanting PTSL impurities, simultaneously injecting corresponding diffusion to prevent impurities, for the N-type period, the impurity forming PTSL is generally B, and the corresponding diffusion
- the blocking impurity is C; for the P-type period, the impurity forming PTSL is generally P, and the corresponding diffusion blocking impurity is Ge.
- Diffusion barrier impurities can effectively inhibit the diffusion of impurities, avoid redistribution of PTSL in subsequent processes, and optimize device performance.
- the PTSL can be effectively distributed in the region where the punch-through current occurs under the existing process conditions without introducing impurity distribution in the channel, effectively optimizing the PTSL process and improving device performance.
- the semiconductor material of the substrate and the fins may be selected from a Group IV semiconductor such as Si or Ge, or a III-V semiconductor such as GaAs, InP, GaN, SiC, or a laminate of the above semiconductor materials.
- the present invention contemplates fabrication of a semiconductor fin 200 over a substrate 100.
- substrate 100 and fins 200 are comprised of silicon.
- the fin 200 is formed by epitaxially growing a semiconductor layer on the surface of the substrate 100 and etching the semiconductor layer.
- the epitaxial growth method may be molecular beam epitaxy MBE or other methods, and the etching method may be dry etching or Dry/wet etching.
- the fin 200 has a height of 100-150 nm.
- an isolation layer is formed on the semiconductor structure to form an isolation layer structure 300, as shown in FIG.
- a silicon nitride and buffered silicon dioxide pattern is first formed on the semiconductor fin 200 as a mask for trench etching.
- a trench having a certain depth and a side wall angle is etched on the substrate 100.
- a thin layer of silicon dioxide is then grown to round the top corners of the trench and remove damage introduced on the silicon surface during the etching process.
- the trench is filled after oxidation, and the filling medium may be silicon dioxide.
- the surface of the semiconductor substrate is then planarized using a CMP process, with silicon nitride acting as a barrier to CMP.
- the surface of the semiconductor structure is etched using silicon nitride as a mask, and the etch depth is greater than the actual desired fin height in order to avoid vertical diffusion in the fin 200 during diffusion in a subsequent process.
- an isolation layer structure 300 is formed, the top of which is 20-60 nm from the top of the fin 200.
- the exposed silicon nitride is removed using hot phosphoric acid to expose the fins 200.
- a mask layer 201 is formed over the fins 200 as a mask for ion implantation in the next step, and the protective fins 200 are not incident by impurities.
- the mask layer 201 may be silicon oxide or silicon nitride.
- silicon nitride is used, and the thickness thereof is 30-50 nm.
- the mask layer 201 is formed, ion implantation is performed on the semiconductor structure, and a via barrier layer 310 is formed in the isolation layer 300. Specifically, the punch-through barrier layer 310 and the diffusion barrier layer 320 are simultaneously formed by lateral scattering of the impurity particles from the isolation layer 300 into the fins 200 during ion implantation.
- the mask layer 201 is then removed, and the device structure is as shown in FIG.
- the present invention injects a diffusion barrier layer while implanting a through-barrier layer.
- the impurity forming PTSL is generally B, and the corresponding diffusion blocking impurity is C;
- the impurity forming PTSL is generally P, and the corresponding diffusion blocking impurity is Ge.
- Diffusion barrier impurities can effectively inhibit the diffusion of impurities, avoid redistribution of PTSL in subsequent processes, and optimize device performance. And since carbon and germanium are tetravalent elements themselves, they do not introduce unwanted carriers, and have no influence on device characteristics, so that optimization is optimized. PTSL distribution without affecting process complexity.
- the dummy gate stack may be a single layer or a plurality of layers.
- the dummy gate stack may comprise a polymer material, amorphous silicon, polysilicon or TiN and may have a thickness of 10-100 nm.
- the pseudo gate stack can be formed by processes such as thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like.
- the source/drain region formation method may be ion implantation and then annealing activated ions, in situ doped epitaxy, and/or a combination of both.
- sidewalls are formed on the sidewalls of the gate stack for spacing the gates apart.
- the sidewall spacers can be formed from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
- the side walls can have a multi-layered structure.
- the sidewall spacers may be formed by a deposition etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm, or 80 nm.
- the interlayer dielectric layer 400 is deposited and planarized in parallel to expose the dummy gate stack.
- the interlayer dielectric layer 400 may be formed by CVD, high density plasma CVD, spin coating, or other suitable methods.
- the material of the interlayer dielectric layer 400 may be SiO 2 , carbon doped SiO 2 , BPSG, PSG, UGS, silicon oxynitride, low k material, or a combination thereof.
- the thickness of the interlayer dielectric layer 400 may range from 40 nm to 150 nm, such as 80 nm, 100 nm, or 120 nm.
- a planarization process is performed to expose the dummy gate stack and is flush with the interlayer dielectric layer 400 (the term "flush" in the present invention means that the height difference between the two is allowed in the process error. Within the scope).
- the dummy gate stack is removed to expose the channel portion.
- the dummy gate structure can be removed by wet etching and/or dry etching. In one embodiment, plasma etching is employed.
- the gate dielectric layer may be a thermal oxide layer, including silicon oxide or silicon oxynitride; or a high-k dielectric such as HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, Al 2 O 3
- a high-k dielectric such as HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, Al 2 O 3
- La 2 O 3 , ZrO 2 , LaAlO, and the gate dielectric layer may have a thickness of 1 nm to 10 nm, for example, 3 nm, 5 nm, or 8 nm.
- the work function adjusting layer may be made of a material such as TiN or TaN, and has a thickness ranging from 3 nm to 15 nm.
- the gate metal layer may have a one-layer or multi-layer structure.
- the material may be one of TaN, TaC, TiN, TaAlN, TiAlN, MoAlN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x or a combination thereof.
- the thickness may range, for example, from 10 nm to 40 nm, such as 20 nm or 30 nm.
- the method provided by the present invention that is, in the process of forming PTSL by side scatter, when implanting PTSL impurities, simultaneously injecting corresponding diffusion to prevent impurities, for N-type devices, impurities forming PTSL are generally B, and corresponding diffusion
- the blocking impurity is C; for the P-type device, the impurity forming PTSL is generally P, and the corresponding diffusion blocking impurity is Ge.
- Diffusion barrier impurities can effectively inhibit the diffusion of impurities, avoid redistribution of PTSL in subsequent processes, and optimize device performance.
- the PTSL can be effectively distributed in the region where the punch-through current occurs under the existing process conditions without introducing impurity distribution in the channel, effectively optimizing the PTSL process and improving device performance.
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Abstract
一种FinFET制造方法,包括:a.提供衬底(100),并在所述衬底上形成鳍片(200);b.所述鳍片(200)两侧的衬底上形成隔离层(300);c.在所述隔离层(300)上半部分两侧的鳍片中形成穿通阻挡层(310)和扩散阻挡层(320);d.在所述鳍片两端分别形成源漏区,在所述鳍片中部形成栅极结构(500),并在所述隔离层(300)上方填充层间介质层(400)。本方法有效的优化了PTSL分布,提高了器件性能。
Description
本申请要求了2014年6月26日提交的、申请号为201410295576.5、发明名称为“一种FinFET制造方法”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
本发明涉及一种半导体器件制造方法,具体地,涉及一种FinFET制造方法。
随着半导体器件的尺寸按比例缩小,出现了阈值电压随沟道长度减小而下降的问题,也即,在半导体器件中产生了短沟道效应。为了应对来自半导体涉及和制造方面的挑战,导致了鳍片场效应晶体管,即FinFET的发展。
沟道穿通效应(Channel punch-through effect)是场效应晶体管的源结与漏结的耗尽区相连通的一种现象。当沟道穿通,就使源/漏间的势垒显著降低,则从源往沟道即注入大量载流子,并漂移通过源-漏间的空间电荷区、形成一股很大的电流;此电流的大小将受到空间电荷的限制,是所谓空间电荷限制电流。这种空间电荷限制电流是与栅压控制的沟道电流相并联的,因此沟道穿通将使得通过器件的总电流大大增加;并且在沟道穿通情况下,即使栅电压低于阈值电压,源-漏间也会有电流通过。这种效应是在小尺寸场效应晶体管中有可能发生的一种效应,且随着沟道宽度的进一步减小,其对器件特性的影响也越来越显著。
在FinFET中,通常采用对沟道下方的鳍片部分进行重掺杂,即形成穿通阻挡层(PTSL),来抑制沟道穿通效应。形成PTSL的方法一般有两种,比较常用的是通过直接离子注入的方法在沟道底部形成重掺杂区域。这种方法形成的PTSL分布范围较大,往往会在沟道中引入杂质,同时离子注入的过程本身也会在沟道中形成缺陷,影响器件性能。另一种方法是通过侧向散射
的方法形成PTSL,也就是不向沟道中直接进行离子注入,而是将杂质注入鳍片两侧的的STI中。因为鳍片本身很薄,由于载流子本身的散射作用,杂质会从STI中扩散至鳍片中,形成PTSL分布。这种方法形成的PTSL分布集中,且不会在沟道中引入缺陷,显著提高了器件性能。
然而,在PTSL形成之后,由于后续工艺中存在数次退火,PTSL中的杂质会在高温下形成再分布,向沟道中扩散,从而在沟道中引入杂质,影响器件的阈值电压和亚阈值特性。因此,需要对上述工艺进行优化,解决这一问题。
发明内容
本发明提供了一种FinFET制造方法,有效的优化了PTSL分布,使其很好的集中在穿通电流产生的地方,抑制了其向沟道的扩散,同时不影响器件的其他性能,不增加工艺复杂度。具体的,该方法包括:
一种FinFET制造方法,包括:
a.提供衬底,并在在所述衬底上形成鳍片;
b.所述鳍片两侧的衬底上形成隔离层;
c.在所述隔离层上半部分两侧的鳍片中形成穿通阻挡层和扩散阻挡层;
d.在所述鳍片两端分别形成源漏区,在所述鳍片中部形成栅极结构,并在所述隔离层上方填充层间介质层。
其中,所述穿通阻挡层和扩散阻挡层通过离子注入时杂质粒子从隔离层到鳍片中的侧向散射形成。
其中,对于N型器件,形成所述穿通阻挡层的杂质为硼;形成所述扩散阻挡区的杂质为碳;所述扩散阻挡区的注入剂量为1.5e15cm-2-7.5e15cm-2。对于P型器件,形成所述穿通阻挡层的杂质为磷;形成所述扩散阻挡区的杂质为锗;所述扩散阻挡区的注入剂量为3e14cm-2-1.5e15cm-2。
本发明提供的方法,即在侧向散射形成PTSL的工艺中,在注入PTSL杂质的时候,同时注入相应的扩散阻止杂质,对于N型器件而言,形成PTSL的杂质一般为B,相应的扩散阻挡杂质即为C;对于P型器件而言,形成PTSL的杂质一般为P,相应的扩散阻挡杂质即为Ge。扩散阻挡杂质能够有效地抑
制杂质的扩散,避免PTSL在后续工艺中的再分布,优化器件性能。采用这种方法,能够有效地在现有工艺条件下,使PTSL有效的分布在穿通电流发生的区域,而不会在沟道中引入杂质分布,有效的优化了PTSL工艺,提高了器件性能。
图1-图4示意性地示出形成根据本发明的制造半导体鳍片的方法各阶段半导体结构的剖面图;其中图1示出形成鳍片步骤后的半导体结构的剖面图;
图2示出在鳍片两侧的衬底上形成隔离层后的剖面图;
图3示出在所述隔离层上半部分两侧的鳍片中形成穿通阻挡层和扩散阻挡层的步骤的示意图;
图4示出所述穿通阻挡层和扩散阻挡层为通过离子注入时杂质粒子从隔离层到鳍片中的侧向散射形成的示意图。
图5示意性地示出形成根据本发明的制造半导体鳍片的方法各阶段半导体结构的三维等角图。
针对上述问题,本发明提供了一种FinFET制造方法,使PTSL有效的分布在穿通电流发生的区域,而不会在沟道中引入杂质分布。具体的,该方法包括:
a.提供衬底100,并在在所述衬底上形成鳍片200;
b.所述鳍片200两侧的衬底上形成隔离层300;
c.在所述隔离层300上半部分两侧的鳍片中形成穿通阻挡层310和扩散阻挡层320;
d.在所述鳍片两端分别形成源漏区,在所述鳍片中部形成栅极结构,并在所述隔离层300上方填充层间介质层500。其中,所述穿通阻挡层310和扩散阻挡层320通过离子注入时杂质粒子从隔离层300到鳍片200中的侧向散射形成。
其中,对于N型器件,形成所述穿通阻挡层310的杂质为硼;形成所述扩散阻挡区320的杂质为碳;所述扩散阻挡区320的注入剂量为1.5e15cm-2-7.5e15cm-2。对于P型器件,形成所述穿通阻挡层310的杂质为磷;形成所述扩散阻挡区320的杂质为锗;所述扩散阻挡区203的注入剂量为3e14cm-2-1.5e15cm-2。
本发明提供的方法,即在侧向散射形成PTSL的工艺中,在注入PTSL杂质的时候,同时注入相应的扩散阻止杂质,对于N型期间而言,形成PTSL的杂质一般为B,相应的扩散阻挡杂质即为C;对于P型期间而言,形成PTSL的杂质一般为P,相应的扩散阻挡杂质即为Ge。扩散阻挡杂质能够有效地抑制杂质的扩散,避免PTSL在后续工艺中的再分布,优化器件性能。采用这种方法,能够有效地在现有工艺条件下,使PTSL有效的分布在穿通电流发生的区域,而不会在沟道中引入杂质分布,有效的优化了PTSL工艺,提高了器件性能。
以下将参照附图更详细地描述本实发明。在各个附图中,相同的元件采用类似的附图标记来表示。为了清楚起见,附图中的各个部分没有按比例绘制。
应当理解,在描述器件的结构时,当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时,可以指直接位于另一层、另一个区域上面,或者在其与另一层、另一个区域之间还包含其它的层或区域。并且,如果将器件翻转,该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。
如果为了描述直接位于另一层、另一个区域上面的情形,本文将采用“直接在……上面”或“在……上面并与之邻接”的表述方式。
在下文中描述了本发明的许多特定的细节,例如器件的结构、材料、尺寸、处理工艺和技术,以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样,可以不按照这些特定的细节来实现本发明。例如,衬底和鳍片的半导体材料可以选自IV族半导体,如Si或Ge,或III-V族半导体,如GaAs、InP、GaN、SiC,或上述半导体材料的叠层。
参见图1,本发明意图制作位于衬底100上方的半导体鳍片200。仅
仅作为示例,衬底100和鳍片200都由硅组成。通过在衬底100表面外延生长半导体层并刻蚀该半导体层而形成鳍片200,所述外延生长方法可以是分子束外延法MBE或其他方法,所述刻蚀方法可以是干法刻蚀或干法/湿法刻蚀。鳍片200高度为100-150nm。
鳍片200形成之后,对所述半导体结构进行隔离层,以形成隔离层结构300,如图3所示。优选地,首先在半导体鳍片200上成氮化硅和缓冲二氧化硅图形,作为沟槽腐蚀的掩膜。接下来在衬底100上腐蚀出具有一定深度和侧墙角度的沟槽。然后生长一薄层二氧化硅,以圆滑沟槽的顶角和去掉刻蚀过程中在硅表面引入的损伤。氧化之后进行沟槽填充,填充介质可以是二氧化硅。接下来使用CMP工艺对半导体衬底表面进行平坦化,氮化硅作为CMP的阻挡层。之后,以氮化硅为掩膜,对半导体结构表面进行刻蚀,为了避免后续工艺中扩散时在鳍片200中引入纵向扩散,所述刻蚀深度大于实际所需鳍片高度。刻蚀完成之后,形成隔离层结构300,其顶部距离鳍片200顶部20-60nm。最后使用热的磷酸取出暴露出的氮化硅,暴露出鳍片200。
接下来,如图3所示,在所述鳍片200上方形成掩膜层201,作为下一步中离子注入的掩膜,保护鳍片200不被杂质射入。该掩膜层201可以是氧化硅或氮化硅,优选的,在本实施例中采用氮化硅,其厚度为30-50nm。
掩膜层201形成之后,对所述半导体结构进行离子注入,在隔离层300中形成穿通阻挡层310。具体的,所述穿通阻挡层310和扩散阻挡层320通过离子注入时杂质粒子从隔离层300到鳍片200中的侧向散射同时形成。之后去除掩膜层201,器件结构如图4所示。
在现有技术中,通过侧向散射形成PTSL之后,由于后续工艺中的数次高温退火,PTSL会继续扩散再分布,扩散进入沟道中,在沟道中引入杂质,影响器件的阈值电压和其他性能。为了抑制这一缺点,本发明在注入穿通阻挡层的同时注入扩散阻挡层。对于N型器件而言,形成PTSL的杂质一般为B,相应的扩散阻挡杂质即为C;对于P型器件而言,形成PTSL的杂质一般为P,相应的扩散阻挡杂质即为Ge。扩散阻挡杂质能够有效地抑制杂质的扩散,避免PTSL在后续工艺中的再分布,优化器件性能。且由于碳和锗本身为四价元素,不会引入不需要的载流子,对器件特性不产生影响,从而优化的优化了
PTSL分布而不影响工艺复杂度。
接下来,在沟道上方形成伪栅叠层,并形成源漏区。所述伪栅叠层可以是单层的,也可以是多层的。伪栅叠层可以包括聚合物材料、非晶硅、多晶硅或TiN,厚度可以为10-100nm。可以采用热氧化、化学气相沉积(CVD)、原子层沉积(ALD)等工艺来形成伪栅叠层。所述源漏区形成方法可以是离子注入然后退火激活离子、原位掺杂外延和/或二者的组合。
可选地,在栅极堆叠的侧壁上形成侧墙,用于将栅极隔开。侧墙可以由氮化硅、氧化硅、氮氧化硅、碳化硅及其组合,和/或其他合适的材料形成。侧墙可以具有多层结构。侧墙可以通过包括沉积刻蚀工艺形成,其厚度范围可以是10nm-100nm,如30nm、50nm或80nm。
接下来,淀积层间介质层400,并并行平坦化,露出伪栅叠层。具体的,层间介质层400可以通过CVD、高密度等离子体CVD、旋涂或其他合适的方法形成。层间介质层400的材料可以采用包括SiO2、碳掺杂SiO2、BPSG、PSG、UGS、氮氧化硅、低k材料或其组合。层间介质层400的厚度范围可以是40nm-150nm,如80nm、100nm或120nm。接下来,执行平坦化处理,使伪栅叠层暴露出来,并与层间介质层400齐平(本发明中的术语“齐平”指的是两者之间的高度差在工艺误差允许的范围内)。
接下来,去除伪栅叠层,露出沟道部分。具体的,伪栅结构可以采用湿刻和/或干刻除去。在一个实施例中,采用等离子体刻蚀。
接下来,在伪栅空位中形成栅极结构500,栅极结构500包括栅介质层、功函数调节层和栅极金属层,如图5所示。具体的,所述栅介质层可以是热氧化层,包括氧化硅、氮氧化硅;也可为高K介质,例如HfAlON、HfSiAlON、HfTaAlON、HfTiAlON、HfON、HfSiON、HfTaON、HfTiON、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合,栅介质层的厚度可以为1nm-10nm,例如3nm、5nm或8nm。所述功函数调节层可以采用TiN、TaN等材料制成,其厚度范围为3nm-15nm。所述栅极金属层可以为一层或者多层结构。其材料可以为TaN、TaC、TiN、TaAlN、TiAlN、MoAlN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax中的一种或其组合。其厚度范围例如可以为10nm-40nm,如20nm或30nm。
本实施例中所述的方法采用的是后栅工艺,然而本领域中的技术人员可以很清楚的知道,该发明同样可以用于先栅工艺,在此不再赘述。
本发明提供的方法,即在侧向散射形成PTSL的工艺中,在注入PTSL杂质的时候,同时注入相应的扩散阻止杂质,对于N型器件而言,形成PTSL的杂质一般为B,相应的扩散阻挡杂质即为C;对于P型器件而言,形成PTSL的杂质一般为P,相应的扩散阻挡杂质即为Ge。扩散阻挡杂质能够有效地抑制杂质的扩散,避免PTSL在后续工艺中的再分布,优化器件性能。采用这种方法,能够有效地在现有工艺条件下,使PTSL有效的分布在穿通电流发生的区域,而不会在沟道中引入杂质分布,有效的优化了PTSL工艺,提高了器件性能。
虽然关于示例实施例及其优点已经详细说明,应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下,可以对这些实施例进行各种变化、替换和修改。对于其他例子,本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时,工艺步骤的次序可以变化。
此外,本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容,作为本领域的普通技术人员将容易地理解,对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤,其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果,依照本发明可以对它们进行应用。因此,本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。
Claims (8)
- 一种FinFET制造方法,包括:a.提供衬底(100),并在在所述衬底上形成鳍片(200);b.所述鳍片(200)两侧的衬底上形成隔离层(300);c.在所述隔离层(300)上半部分两侧的鳍片中形成穿通阻挡层(310)和扩散阻挡层(320);d.在所述鳍片两端分别形成源漏区,在所述鳍片中部形成栅极结构,并在所述隔离层(300)上方填充层间介质层(500)。
- 根据权利要求1所述的制造方法,其特征在于,所述穿通阻挡层(310)和扩散阻挡层(320)通过离子注入时杂质粒子从隔离层(300)到鳍片(200)中的侧向散射形成。
- 根据权利要求2所述的制造方法,其特征在于,对于N型器件,形成所述穿通阻挡层(310)的杂质为硼。
- 根据权利要求3所述的制造方法,其特征在于,形成所述扩散阻挡区(320)的杂质为碳。
- 根据权利要求4所述的制造方法,其特征在于,所述扩散阻挡区(320)的注入剂量为1.5e15cm-2-7.5e15cm-2。
- 根据权利要求2所述的制造方法,其特征在于,对于P型器件,形成所述穿通阻挡层(310)的杂质为磷。
- 根据权利要求6所述的制造方法,其特征在于,形成所述扩散阻挡区(320)的杂质为锗。
- 根据权利要求7所述的制造方法,其特征在于,所述扩散阻挡区(203)的注入剂量为3e14cm-2-1.5e15cm-2。
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