CN103855011A - FinFET及其制造方法 - Google Patents

FinFET及其制造方法 Download PDF

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CN103855011A
CN103855011A CN201210506189.2A CN201210506189A CN103855011A CN 103855011 A CN103855011 A CN 103855011A CN 201210506189 A CN201210506189 A CN 201210506189A CN 103855011 A CN103855011 A CN 103855011A
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finfet
semiconductor fin
break
doping
trapping layer
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CN103855011B (zh
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朱慧珑
许淼
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201210506189.2A priority Critical patent/CN103855011B/zh
Priority to PCT/CN2012/086155 priority patent/WO2014082340A1/zh
Priority to US14/647,736 priority patent/US10263111B2/en
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Abstract

公开了一种FinFET及其制造方法。制造FinFET的方法包括：图案化半导体衬底以形成脊状物；进行离子注入，使得在脊状物中形成掺杂穿通阻止层，并且半导体衬底位于掺杂穿通阻止层上方的部分形成半导体鳍片；形成与半导体鳍片相交的栅堆叠，该栅堆叠包括栅极电介质和栅极导体，并且栅电介质将栅极导体和半导体鳍片隔开；形成围绕栅极导体的栅极侧墙；以及在半导体鳍片位于栅堆叠两侧的部分中形成源区和漏区。掺杂穿通阻止层将半导体鳍片和半导体衬底隔开，从而可以断开源区和漏区之间经由半导体衬底的漏电流路径。

Description

FinFET及其制造方法
技术领域
本发明涉及半导体技术，更具体地，涉及FinFET及其制作方法。
背景技术
随着半导体器件的尺寸越来越小，短沟道效应愈加明显。为了抑制短沟道效应，提出了在SOI晶片或块状半导体衬底上形成的FinFET。FinFET包括在半导体材料的鳍片(fin)的中间形成的沟道区，以及在鳍片两端形成的源/漏区。栅电极在沟道区的两个侧面包围沟道区(即双栅结构)，从而在沟道各侧上形成反型层。由于整个沟道区都能受到栅极的控制，因此能够起到抑制短沟道效应的作用。
在批量生产中，与使用SOI晶片相比，使用块状的半导体衬底制造的FinFET成本效率更高，从而广泛采用。然而，在使用半导体衬底的FinFET中难以控制半导体鳍片的高度，并且在源区和漏区之间可能形成经由半导体衬底的导电路径，从而产生漏电流的问题。
为了减小源区和漏区之间的漏电流，可以在半导体鳍片下方形成掺杂穿通阻止层(punch-through-stopper layer)。例如，通过对半导体衬底进行离子注入形成掺杂区，以提供掺杂穿通阻止层，然后将半导体衬底位于穿通阻止层上方的部分图案化为半导体鳍片。
然而，掺杂区的浓度分布导致其难以形成明显的边界。利用掺杂区提供的掺杂穿通阻止层的深度位置及其厚度难以清晰地限定。进一步地，位于掺杂穿通阻止层上方的半导体鳍片的厚度也难以清晰地限定。半导体鳍片与掺杂穿通阻止层之间的过渡区域可能成为潜在的漏电流路径，并且导致FinFET的阈值电压不期望地发生随机变化。
发明内容
本发明的目的是在基于半导体衬底的FinFET中减小源区和漏区之间的漏电流，并且减小阈值电压的随机变化。
根据本发明的一方面，提供一种制造FinFET的方法，包括：图案化半导体衬底以形成脊状物；进行离子注入，使得在脊状物中形成掺杂穿通阻止层，并且半导体衬底位于掺杂穿通阻止层上方的部分形成半导体鳍片；形成与半导体鳍片相交的栅堆叠，该栅堆叠包括栅极电介质和栅极导体，并且栅电介质将栅极导体和半导体鳍片隔开；形成围绕栅极导体的栅极侧墙；以及在半导体鳍片位于栅堆叠两侧的部分中形成源区和漏区。
根据本发明的另一方面，提供一种FinFET，包括：半导体衬底；位于半导体衬底上的掺杂穿通阻止层；位于掺杂穿通阻止层上的半导体鳍片；与半导体鳍片相交的栅堆叠，该栅堆叠包括栅极电介质和栅极导体，并且栅电介质将栅极导体和半导体鳍片隔开；以及位于半导体鳍片两端的源区和漏区，其中掺杂穿通阻止层和半导体鳍片均由半导体衬底形成。
在本发明的FinFET中，采用掺杂穿通阻止层将半导体鳍片和半导体衬底隔开，从而可以断开源区和漏区之间经由半导体衬底的漏电流路径。由于在形成脊状物之后进行离子注入，在脊状物的深度方向上形成陡峭的掺杂分布，可以更清晰地限定掺杂穿通阻止层的上边界和下边界，以及更清楚地限定位于掺杂穿通阻止层上方的半导体鳍片的高度。本发明的FinFET可以减小漏电流和减小阈值电压的随机变化。在一个优选的实施例中，在应力作用层中形成的源区和漏区可以向半导体鳍片中的沟道区施加合适的应力以提供载流子的迁移率。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1-6是示出了根据本发明的第一实施例的制造半导体器件的方法的各个阶段的半导体结构的示意图，其中在图4中还示出掺杂穿通阻止层中的掺杂分布。
图7-9示出了根据本发明的一个优选实施例的制造半导体器件的方法的一部分阶段的半导体结构的示意图。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。
为了简明起见，可以在一幅图中描述经过数个步骤后获得的半导体结构。
应当理解，在描述器件的结构时，当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时，可以指直接位于另一层、另一个区域上面，或者在其与另一层、另一个区域之间还包含其它的层或区域。并且，如果将器件翻转，该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。
如果为了描述直接位于另一层、另一个区域上面的情形，本文将采用“直接在......上面”或“在......上面并与之邻接”的表述方式。
在本申请中，术语“半导体结构”指在制造半导体器件的各个步骤中形成的整个半导体结构的统称，包括已经形成的所有层或区域。在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。
除非在下文中特别指出，FinFET的各个部分可以由本领域的技术人员公知的材料构成。半导体材料例如包括III-V族半导体，如GaAs、InP、GaN、SiC，以及IV族半导体，如Si、Ge。栅极导体可以由能够导电的各种材料形成，例如金属层、掺杂多晶硅层、或包括金属层和掺杂多晶硅层的叠层栅极导体或者是其他导电材料，例如为TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax，MoNx、TiSiN、TiCN、TaAlC、TiAlN、TaN、PtSix、Ni3Si、Pt、Ru、Ir、Mo、HfRu、RuOx和所述各种导电材料的组合。栅极电介质可以由SiO2或介电常数大于SiO2的材料构成，例如包括氧化物、氮化物、氧氮化物、硅酸盐、铝酸盐、钛酸盐，其中，氧化物例如包括SiO2、HfO2、ZrO2、Al2O3、TiO2、La2O3，氮化物例如包括Si3N4，硅酸盐例如包括HfSiOx，铝酸盐例如包括LaAlO3，钛酸盐例如包括SrTiO3，氧氮化物例如包括SiON。并且，栅极电介质不仅可以由本领域的技术人员公知的材料形成，也可以采用将来开发的用于栅极电介质的材料。
本发明可以各种形式呈现，以下将描述其中一些示例。
参照图1-6描述根据本发明的第一实施例的制造半导体器件的方法的示例流程，其中，在图5a-6a中示出了半导体结构的俯视图及截面图的截取位置，在图1-4、5b-6b中示出在半导体鳍片的宽度方向上沿线A-A截取的半导体结构的截面图，在图5c-6c中示出在半导体鳍片的长度方向上沿线B-B截取的半导体结构的截面图。
如图1所示，通过旋涂在半导体衬底101上形成光致抗蚀剂层PR1，并通过其中包括曝光和显影的光刻工艺将光致抗蚀剂层PR1形成用于限定半导体鳍片的形状(例如，条带)的图案。
采用光致抗蚀剂层PR1作为掩模，通过干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过使用蚀刻剂溶液的湿法蚀刻，去除半导体衬底101的暴露部分。通过控制蚀刻的时间，可以控制半导体衬底101中的蚀刻深度，从而在半导体衬底101中形成开口，并且在开口之间限定脊状物。
然后，通过在溶剂中溶解或灰化去除光致抗蚀剂层PR1。例如通过高密度等离子体沉积(HDP)工艺，在半导体结构的表面上形成第一绝缘层102(例如，氧化硅)，以填充半导体衬底101中的开口。通过控制工艺淀积参数，使得第一绝缘层102在脊状物的顶部上的部分厚度远远小于位于脊状物之间的开口内的部分厚度，优选为脊状物的顶部上的部分厚度小于位于脊状物之间的开口内的部分厚度的三分之一，优选小于四分之一，且优选为第一绝缘层102在脊状物的顶部上的部分的厚度小于脊状物之间间距(即开口宽度)的一半。在本发明的一个实施例中，其中第一绝缘层102在开口内的部分的厚度大于80nm，第一绝缘层102位于脊状物顶部的部分的厚度小于20nm。
通过选择性的蚀刻工艺(例如，反应离子蚀刻)，回蚀刻第一绝缘层102，如图2所示。该蚀刻不仅去除第一绝缘层102位于脊状物的顶部上的部分，而且减小第一绝缘层102位于开口内的部分的厚度。第一绝缘层102限定开口的深度。控制蚀刻的时间，使得开口的深度应当大致等于将要形成的半导体鳍片的高度。
然后，在未使用掩模的情形下进行离子注入，如图3所示。在半导体衬底101中形成的掺杂区将提供掺杂穿通阻止层。如图中的实心箭头所示，离子注入可以垂直于半导体结构的表面。控制离子注入的参数，使得掺杂区位于半导体衬底101的脊状物中的预定深度并且具有期望的掺杂浓度。应当注意，由于脊状物的形状因子，在离子注入中，一部分掺杂剂(离子或元素)可能从脊状物散射到第一绝缘层102中，从而有利于在深度方向上形成陡峭的掺杂分布。第一绝缘层102阻挡掺杂剂进一步进入半导体衬底101位于开口中的部分中。并且，已经进入第一绝缘层102的掺杂剂可以向脊状物扩散，在半导体鳍片的宽度方向上也形成掺杂分布。
在离子注入中，针对不同类型的FinFET可以采用不同的掺杂剂。在N型FinFET中可以使用P型掺杂剂，例如B、In，在P型FinFET中可以使用N型掺杂剂，例如P、As。将要形成的掺杂穿通阻止层的掺杂类型与源区和漏区的掺杂类型相反，从而可以断开源区和漏区之间的漏电流路径。在离子注入之后，在半导体衬底101的脊状物中形成的掺杂区提供掺杂穿通阻止层103，如图4(a)所示。该脊状物位于掺杂穿通阻止层103之上的部分形成半导体鳍片104。并且，半导体鳍片104与半导体衬底101之间由穿通阻止层103隔开。
在图4(b)中，曲线a说明根据本发明的方法在形成脊状物之后进行离子注入之后在深度方向(即图4(a)所示的Y方向)上的掺杂浓度分布，曲线b说明根据现有技术的方法在大面积的平整半导体衬底(即形成脊状物之前的半导体衬底)中进行离子注入之后在深度方向的掺杂浓度分布。在一个示例中，示出了在形成脊状物之后注入In的模拟掺杂浓度分布曲线a，选择的深度约为0.2μm。与现有技术相比，根据本发明的方法在形成脊状物之后进行的离子注入获得的掺杂穿通阻止层在深度方向上具有陡峭的掺杂浓度分布。
在图4(c)中，曲线说明根据本发明的方法在形成脊状物之后进行离子注入之后在半导体鳍片的宽度方向(即图4(a)中的X方向)上的掺杂浓度分布。在一个示例中，示出了在形成脊状物之后注入In的模拟掺杂浓度分布曲线a，选择的深度约为0.2μm。与现有技术相比，根据本发明的方法在形成脊状物之后进行的离子注入获得的掺杂区在宽度方向上具有陡峭的掺杂浓度分布。由于进入第一绝缘层102的掺杂剂可以向脊状物扩散，在宽度方向上也形成掺杂分布。根据本发明的方法在形成脊状物之后进行的离子注入获得的掺杂穿通阻止层中间部分的掺杂浓度大于两端部分的掺杂浓度。
然后，通过已知的沉积工艺，如电子束蒸发(EBM)、化学气相沉积(CVD)、原子层沉积(ALD)、溅射等，在半导体结构的表面上形成栅极电介质105(例如，氧化硅或氮化硅)。在一个示例中，该栅极电介质105为约0.8-1.5nm厚的氧化硅层。栅极电介质105覆盖半导体鳍片104的顶部表面和侧面。
通过上述已知的沉积工艺，在半导体结构的表面上形成导体层(例如，掺杂多晶硅)。如果需要，可以对导体层进行化学机械抛光(CMP)，以获得平整的表面。
采用光致抗蚀剂掩模，将该导体层图案化为与半导体鳍片相交的栅极导体106，并且进一步去除栅极电介质105的暴露部分，如图5a、5b和5c所示。栅极导体106和栅极电介质105一起形成栅堆叠。在图5a、5b和5c所示的示例中，栅极导体106的形状为条带，并且沿着与半导体鳍片的长度垂直的方向延伸。
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成氮化物层。在一个示例中，该氮化物层为厚度约5-20nm的氮化硅层。通过各向异性的蚀刻工艺(例如，反应离子蚀刻)，去除氮化物层的横向延伸的部分，使得氮化物层位于栅极导体106的侧面上的垂直部分保留，从而形成栅极侧墙107，如图6a、6b和6c所示。通常，由于形状因子，半导体鳍片104侧面上的氮化物层厚度比栅极导体106的侧面上的氮化物层厚度小，从而在该蚀刻步骤中可以完全去除半导体鳍片104侧面上的氮化物层。否则，半导体鳍片104侧面上的氮化物层厚度太大可能妨碍形成栅极侧墙。可以采用附加的掩模进一步去除半导体鳍片104侧面上的氮化物层。
该蚀刻暴露半导体鳍片104位于栅极导体106两侧的部分的顶部表面和侧面。然后，可以按照常规的工艺在半导体鳍片104的暴露部分中形成源区和漏区。
参照图7-9描述根据本发明的优选实施例的制造半导体器件的方法的一部分阶段的示例流程，其中，在图7a-9a中示出了半导体结构的俯视图及截面图的截取位置，在图7b-9b中示出在半导体鳍片的宽度方向上沿线A-A截取的半导体结构的截面图，在图7c-9c中示出在半导体鳍片的长度方向上沿线B-B截取的半导体结构的截面图。
根据该优选实施例，在图6所示的步骤之后进一步执行图7至9所示的步骤以形成应力作用层，并且在应力作用层中形成源区和漏区。
通过上述已知的蚀刻工艺(例如，反应离子蚀刻)，相对于栅极侧墙107选择性地去除半导体鳍片104位于栅极导体106两侧的部分，如图7a、7b和7c所示。该蚀刻可以在掺杂穿通阻止层107的顶部表面停止，或者进一步去除掺杂穿通阻止层107的一部分(如图7c所示)。该蚀刻还可能去除栅极导体106的一部分。由于栅极导体106的厚度可以比半导体鳍片104的高度大很多，因此，该蚀刻仅仅减小了栅极导体106的厚度，而没有完全去除栅极导体106(如图7c所示)。
然后，通过上述已知的沉积工艺，在掺杂穿通阻止层107上外延生长应力作用层108，如图8a、8b和8c所示。应力作用层108还形成在栅极导体106上。该应力作用层108的厚度应当足够大，使得应力作用层108的顶部表面高于或等于半导体鳍片104的顶部表面，以最大化在半导体鳍片104施加的应力。
针对不同类型的FinFET可以形成不同的应力作用层108。通过应力作用层向FinFET的沟道区施加合适的应力，可以提高载流子的迁移率，从而减小导通电阻并提高器件的开关速度。为此，采用与半导体鳍片104的材料不同的半导体材料形成源区和漏区，可以产生期望的应力。对于N型FinFET，应力作用层108例如是在Si衬底上形成的C的含量约为原子百分比0.2-2％的Si∶C层，沿着沟道区的纵向方向对沟道区施加拉应力。对于P型FinFET，应力作用层108例如是在Si衬底上形成的Ge的含量约为原子百分比15-75％的SiGe层，沿着沟道区的纵向方向对沟道区施加压应力。
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成第二绝缘层109(例如，氧化硅)。对半导体结构进行化学机械抛光，以获得平整的表面，如图9a、9b和9c所示。该化学机械抛光去除了第二绝缘层109位于栅极导体110上方的一部分，从而暴露出栅极导体110上方的应力作用层112和栅极侧墙111。进一步地，该化学机械抛光可以去除栅极导体110上方的应力作用层112以及栅极侧墙111的一部分，从而暴露栅极导体106。
根据上述的各个实施例，在形成源区和漏区之后，可以在所得到的半导体结构上形成层间绝缘层、位于层间绝缘层中的通孔、位于层间绝缘层上表面的布线或电极，从而完成FinFET的其他部分。
在以上的描述中，对于各层的构图、蚀刻等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本发明的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本发明的范围。本发明的范围由所附权利要求及其等价物限定。不脱离本发明的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本发明的范围之内。

Claims (15)

1.一种制造FinFET的方法，包括：
图案化半导体衬底以形成脊状物；
进行离子注入，使得在脊状物中形成掺杂穿通阻止层，并且半导体衬底位于掺杂穿通阻止层上方的部分形成半导体鳍片；
形成与半导体鳍片相交的栅堆叠，该栅堆叠包括栅极电介质和栅极导体，并且栅电介质将栅极导体和半导体鳍片隔开；
形成围绕栅极导体的栅极侧墙；以及
在半导体鳍片位于栅堆叠两侧的部分中形成源区和漏区。
2.根据权利要求1所述的方法，其中脊状物由半导体衬底中的开口限定，并且在图案化半导体衬底的步骤和进行离子注入的步骤之间还包括：
形成绝缘层，该绝缘层填充开口并且覆盖脊状物的顶部；以及
回刻绝缘层，去除绝缘层位于脊状物的顶部的部分并保留绝缘层在开口内的一部分，从而用作隔离层。
3.根据权利要求2所述的方法，其中形成绝缘层的步骤包括：
通过高密度等离子体淀积方法形成绝缘层，该绝缘层在开口内的部分的厚度远远大于位于脊状物的顶部的部分的厚度。
4.根据权利要求3所述的方法，其中刚刚形成的绝缘层位于脊状物的顶部的部分的厚度小于绝缘层在开口内的部分的厚度的三分之一。
5.根据权利要求1所述的方法，其中所述FinFET是N型的，并且在对穿通阻止层掺杂的步骤中使用P型掺杂剂。
6.根据权利要求1所述的方法，其中所述FinFET是P型的，并且在对穿通阻止层掺杂的步骤中使用N型掺杂剂。
7.根据权利要求1所述的方法，其中形成源区和漏区的步骤包括：
采用栅极侧墙和栅极导体作为硬掩模，通过蚀刻去除半导体鳍片的暴露部分至掺杂穿通阻止层露出，使得在栅极导体两侧形成到达掺杂穿通阻止层的开口；
在开口内形成应力作用层，该应力作用层由与半导体鳍片不同的材料组成；以及
在应力作用层中形成源区和漏区。
8.一种FinFET，包括：
半导体衬底；
位于半导体衬底上的掺杂穿通阻止层；
位于掺杂穿通阻止层上的半导体鳍片；
与半导体鳍片相交的栅堆叠，该栅堆叠包括栅极电介质和栅极导体，并且栅电介质将栅极导体和半导体鳍片隔开；以及
位于半导体鳍片两端的源区和漏区，
其中掺杂穿通阻止层和半导体鳍片均由半导体衬底形成。
9.根据权利要求8所述的FinFET，其中所述FinFET是N型的，并且所述掺杂穿通阻止层是P型的。
10.根据权利要求8所述的FinFET，其中所述FinFET是P型的，并且所述掺杂穿通阻止层是N型的。
11.根据权利要求8所述的FinFET，还包括将栅极导体和半导体衬底隔开的绝缘层。
12.根据权利要求8所述的FinFET，其中源区和漏区由与半导体鳍片不同的材料组成。
13.根据权利要求12所述的FinFET，其中所述FinFET是N型的，并且所述半导体鳍片由Si组成，所述源区和漏区由C的含量约为原子百分比0.2-2％的Si∶C组成。
14.根据权利要求12所述的FinFET，其中所述FinFET是P型的，并且所述半导体鳍片由Si组成，所述源区和漏区由Ge的含量约为原子百分比15-75％的SiGe组成。
15.根据权利要求8所述的FinFET，其中掺杂穿通阻止层存在着沿半导体鳍片的宽度方向的掺杂浓度分布，使得掺杂穿通阻止层中间部分的掺杂浓度大于两端部分的掺杂浓度。
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