540135 五、發明說明（1) 技術領域 本發明係有關於半導體積體電路的製造，特別是有關 於一種用於高深寬比之淺溝槽隔離區（Shal low trench isolation)的製作方法。 背景技術 近年來，隨著半導體積體電路製造技術的發展，晶片 中所含元件的數量不斷增加，元件的尺寸也因積集度的提 昇而不斷地縮小，生產線上使用的線路寬度已由次微米 (sub-micron)進入了 四分之一微米（quarter-micron)甚或 更細微尺寸的範圍。而無論元件尺寸如何縮小化，在晶片 中各個元件之間仍必須有適當地絕緣或隔離，方可得到良 好的元件性質。這方面的技術一般稱為元件隔離技術 (device isolation technology)，其主要 g 的係在各元 件之間形成隔離物，並且在確保良好隔離效果的情況下， 儘篁縮小隔離物的區域’以空出更多的晶片面積來容納更 多的元件。 在各種元件隔離技術中’局部石夕氧化方法（L 〇 c 〇 s)和 淺溝槽隔離區（shallow trench isolation)製程是最常被 採用的兩種技術，尤其後者具有隔離區域小和完成後仍保 持基底平坦性等優點，更是近來頗受重視的半導體製造技 術。傳統上，係先利用化學氣相沈積（CVD)程序，形成一 介電層以填入基底的溝槽中’之後再回蝕刻（etch back) 去除表面多餘的介電層’以完成溝槽隔離區製程。但隨著 積體電路密度不斷提高而元件尺寸日漸縮小的發展7上述540135 V. Description of the Invention (1) Technical Field The present invention relates to the manufacture of semiconductor integrated circuits, and more particularly to a method for manufacturing a shallow trench isolation region with a high aspect ratio. 2. Description of the Related Art In recent years, with the development of semiconductor integrated circuit manufacturing technology, the number of components contained in a wafer has been increasing, and the size of components has been continuously reduced due to the increase in the degree of integration. Sub-micron enters the range of quarter-micron or even finer sizes. Regardless of how the component size is reduced, each component in the wafer must still be properly insulated or isolated to obtain good component properties. This technology is generally referred to as device isolation technology. Its main g is to form a spacer between components, and to ensure a good isolation effect, minimize the area of the spacer. Make more chip area to accommodate more components. Among the various component isolation technologies, the 'local oxidization method (LoC) and shallow trench isolation process are the two most commonly used technologies, especially the latter has a small isolation area and after completion The advantages of maintaining the flatness of the substrate are the semiconductor manufacturing technologies that have received much attention recently. Traditionally, a chemical vapor deposition (CVD) process has been used to form a dielectric layer to fill the trenches in the substrate 'and then etch back to remove excess dielectric layers on the surface' to complete trench isolation District process. However, as the density of integrated circuits continues to increase and component sizes shrink, 7
540135540135
習知之沈積技術因步階覆蓋能力（s t e p c 〇 v e r a g e )的問 題，並不易將介電層完全填滿溝槽，導致元件的隔離效果 受到影響。 高密度電漿化學氣相沈積（HDPCVD)程序由於具有極佳 的溝槽填充（gap—filling)能力，因此非常適合用來製作 細微的半導體元件淺溝槽隔離區，然而其沈積之氧化層具 有獨特的表面構形（top〇graphy)，必須藉化學性機械研磨 程序（CMP)來進行平坦化處理。The conventional deposition technology is not easy to completely fill the trench with the dielectric layer due to the problem of step coverage (s t e p c 〇 v e r a g e), which causes the isolation effect of the device to be affected. The high-density plasma chemical vapor deposition (HDPCVD) process is very suitable for making fine semiconductor device shallow trench isolation regions due to its excellent gap-filling capability. However, the deposited oxide layer has The unique topography must be planarized by a chemical mechanical polishing program (CMP).
f前在業界的製程中，為了提昇溝槽之沈積技術的步 階覆蓋能力，通常都使用高密度電漿化學氣相沈積，為了 進一步說明該技術内容，以下請參照第丨A至丨B圖，說明其 製程流程。 〃fIn the industry's previous processes, in order to improve the step coverage capability of the trench deposition technology, high-density plasma chemical vapor deposition is usually used. To further explain the technical content, please refer to Figures 丨 A to 丨 B below , Explain its process flow. 〃
如第1A圖所示者，在一半導體基底1〇表面上形成一遮 蔽層三例如於一矽晶圓表面上，以化學氣相沈積法（CVD) 或熱氧化成長法形成一厚度介於5〇 A至2〇〇a的墊氧化層 (pad oxide layer)ll。然後，在墊氧化層u表面上，二 CVD程序沈積一厚度介於12〇〇 a至丨7〇〇 a的氮化矽層12， 二者共同構成遮蔽層。接著，以微影成像 (photolithography)和蝕刻程序，定義出氮化矽層12和墊 氧化層11的圖案，用以露出半導體基底1〇欲形成元件 區的部分。利用上述遮蔽層的圖案當作罩幕，施行一蝕刻 程序而在半導體基底中形成一溝槽以露出半導體基底1〇欲 形成元件隔離區的部分，其深度介於5〇〇〇入至6〇〇〇入之 間。As shown in FIG. 1A, a masking layer 3 is formed on the surface of a semiconductor substrate 10, for example, on a silicon wafer surface, and a thickness of 5 is formed by chemical vapor deposition (CVD) or thermal oxidation growth. OA to 2000a pad oxide layers. Then, on the surface of the pad oxide layer u, a silicon nitride layer 12 having a thickness ranging from 12000a to 7000a is deposited by two CVD processes, and the two together form a shielding layer. Then, a pattern of the silicon nitride layer 12 and the pad oxide layer 11 is defined by photolithography and etching procedures to expose the portion of the semiconductor substrate 10 where the device region is to be formed. Using the pattern of the above shielding layer as a mask, an etching process is performed to form a trench in the semiconductor substrate to expose the portion of the semiconductor substrate 10 where the element isolation region is to be formed, the depth of which ranges from 5000 to 600. 〇〇 入 之间。 Between 〇〇 入.
540135 五、發明說明（3)540135 V. Description of the invention (3)
其次，請參照第1B圖，以熱氧化程序（thermal oxidation)成長一薄氧化層14，覆蓋在溝槽底面及側壁 上’用以當作襯裡（nner)，其厚度約為18〇A〜22〇A。之 後’於上述遮蔽層與薄氧化層1 4表面順應性地形成一薄氮 化石夕層1 6 ’亦為當作襯裡。接著，施行高密度電漿化學氣 相沈積程序，例如使用〇2和sih4當作反應物，同時施以Ar 電漿錢擊而沈積一作為絕緣層之二氧化矽層1 8，並填滿溝 槽’得到如第1 B圖之構造。其中，由於溝槽分布的密度不 同’加上HDPCVD技術的特性，使得所沈積之氧化層18形成 如圖中所示高低起伏的構造。 目則在面深寬比之淺溝槽隔離區的製程上，習知技術 可能造成的缺點可參照第丨c和丨D圖。 、如第1 C圖顯示，當溝槽的開口寬度越小且/或深寬比 越大時，例如當該溝槽開口寬度小於0· 15 //m且/或深寬比 大，3時則目知的咼密度電漿化學氣相沈積程序所沈積 的氧化層1 8就很容易有孔洞2 〇發生，而影響淺溝槽隔離區 的絕緣特性。 此外、’如第丨D圖顯示，在高密度電漿化學氣相沈積程Secondly, please refer to FIG. 1B, a thin oxide layer 14 is grown by a thermal oxidation process, covering the bottom surface and sidewalls of the trench, 'for the nner, and its thickness is about 18A ~ 22 〇A. After that, a thin nitrogen fossil evening layer 16 is formed on the surface of the shielding layer and the thin oxide layer 14 in conformity with each other, and it is also used as a lining. Next, a high-density plasma chemical vapor deposition process is performed, for example, using 02 and sih4 as reactants, and applying an Ar plasma coin to deposit a silicon dioxide layer 18 as an insulating layer, and fill the trench. The grooves are constructed as shown in FIG. 1B. Among them, due to the different density of the trench distribution 'and the characteristics of the HDPCVD technology, the deposited oxide layer 18 is formed into a undulating structure as shown in the figure. In the process of manufacturing shallow trench isolation areas with aspect ratios, the disadvantages caused by conventional techniques can be referred to Figures 丨 c and 丨 D. As shown in Figure 1C, when the opening width of the trench is smaller and / or the aspect ratio is larger, for example, when the opening width of the trench is less than 0 · 15 // m and / or the aspect ratio is large, 3 Then, the oxide layer 18 deposited by the known pseudo-density plasma chemical vapor deposition process can easily have holes 20, which affects the insulation characteristics of the shallow trench isolation region. In addition, as shown in Figure 丨 D, during the high-density plasma chemical vapor deposition process
擊的過程也可能有擊落的碎片2 1殘留於溝槽 中’也很容易產生孔洞。 發明概述 播随ίΐΪ此’本發明之目的係提供-種半導體元件淺溝 坦曰值絡-从表耘其可改善絕緣層填入溝槽的能力， 挺幵隔離7〇件的性質。There may also be downed fragments 21 remaining in the trench during the striking process, and holes may be easily generated. SUMMARY OF THE INVENTION The purpose of the present invention is to provide a semiconductor device with shallow trenches, which means that it can improve the ability of an insulating layer to fill trenches, and it can isolate 70 properties.
第6頁 540135 五、發明說明（4) ，為了達成上述目的，本發明提出一種淺溝槽隔離區之 製作方法，其步驟包括：提供一半導體基底，其表面上形 成一溝槽；將基底置於一反應室中，以高密度電漿化學氣 相沈積去，於上述基底表面形成一第一絕緣層，且部分填 入上述溝槽；於上述反應室中，以氟化碳氣體進行原位蝕 以去除上述溝槽外大部分之第一絕緣層；以及再以高 ，度電漿化學氣相沈積法，形成一第二絕緣層覆蓋在上述 ^ 一絕緣層表面上，使溝槽填滿而無空隙。藉由高密度電 漿化學氣相沈積法併用原位蝕刻法以形成元件隔離區絕緣 層’可避免淺溝槽隔離區中發生孔洞的缺點。 根據本發明之一種淺溝槽隔離區製作方法的較佳實施 例其中上述南费度電漿化學氣相沈積程序係使用氧氣 (〇2)和矽甲烧（S i & )當作反應物，並施以a r電漿濺擊 (^putter)以沈積第一氧化層。而原位蝕刻係採用氟化碳 氣體，該類氣體具有對於二氧化矽與氮化矽的高選擇比， 可以控制㈣對於溝槽外之基底h溝槽侧壁以及溝槽底 面的沈積等不同厚度的二氧化矽層。 一 實施例 β百先’如第2A圖所示者’在一半導體基底1〇〇，例如 晶圓表面上’以CVD程序或熱氧化成長一 厚度介於50 A和20 0 A的埶备儿a，λ, 的墊乳化層1 01 〇然後，在墊氣化® 1 〇 1表面上，以CVD敕皮、士 n ^ ^ ^ 長序沈積一厚度介於500A和2〇〇〇A的 氮化矽層102，二者妓回播士 夺uuu a的 务r "门構成一遮蔽層。接著，以微影成 像（photol i thography)和蝕列 々 ϋ φ，儿 、成 不蚀刻矛王序，疋義出虱化石夕層1 〇 2Page 6 540135 V. Description of the invention (4) In order to achieve the above object, the present invention proposes a method for manufacturing a shallow trench isolation region, the steps of which include: providing a semiconductor substrate with a trench formed on the surface thereof; In a reaction chamber, a high-density plasma chemical vapor deposition is performed to form a first insulating layer on the surface of the substrate, and part of the groove is filled; in the reaction chamber, in-situ carbon fluoride gas is used. Etch to remove most of the first insulating layer outside the trench; and then use a high-degree plasma chemical vapor deposition method to form a second insulating layer over the surface of the aforementioned insulating layer to fill the trench. Without voids. The high-density plasma chemical vapor deposition method and the in-situ etching method to form the insulating layer of the element isolation region can avoid the disadvantage of holes in the shallow trench isolation region. According to a preferred embodiment of the method for fabricating a shallow trench isolation region according to the present invention, the above-mentioned South Ferto plasma CVD process uses oxygen (02) and sintered silicon (Si &) as reactants. And applying ar plasma sputtering to deposit a first oxide layer. The in-situ etching system uses a carbon fluoride gas, which has a high selection ratio for silicon dioxide and silicon nitride, and can control the deposition of the trenches on the substrate outside the trench, the sidewalls of the trench, and the bottom of the trench. Thick silicon dioxide layer. An embodiment β hundred first 'as shown in FIG. 2A' on a semiconductor substrate 100, such as on the surface of a wafer, 'was grown by a CVD process or thermal oxidation to a thickness between 50 A and 200 A a, λ, the pad emulsified layer 1 01 〇 Then, on the surface of the pad gasification ® 〇1, in a long order of CVD 士 skin, n ^ ^ ^ deposition of a thickness between 500A and 2000A nitrogen The silicon layer 102 is a shielding layer formed by the prostitutes of the two. Next, using photolithography and eclipse 々 ϋ φ, Er, Cheng did not etch the order of the spear king, and the meaning of the lice fossils layer was 〇 2
540135 五、發明說明（5) 和塾氧化層101的圖案，用以露出半導體基底10〇欲形成元 件隔離區的部分。利用上述遮蔽層的圖案當作罩幕，施行 一敍刻程序而在半導體基底中形成一溝槽，其深度介於 5 0 0 0 A至600 0 A之間。然後，以熱氧化程序（<(：|：16〇181 oxidation)成長一薄氧化層1〇4，覆蓋在溝槽底面及側壁 上’用以當作襯裡（liner)，其厚度約為18()A〜220A。之 ，’於上述遮蔽層與薄氧化層丨〇 4表面順應性地形成一薄 氮化矽層1 0 6，亦為當作襯裡。 产接著’請參照第2B圖，進行本發明第一次高密度化學 氣相沈積程序，將基底置於一反應室中，以高密度化學氣 相沈積法，例如使用氧氣（〇2)和矽甲烷（SiH4)當作反應 物，同時施以Ar電漿濺擊，於薄氮化矽層表面沈積第一絕 緣層108a ’例如二氧化石夕層，其厚度為介於25〇〇人〜35〇() A ’通常約為30 00 A，並由於高密度電漿化學氣相沈積法 之特性，使溝槽側壁成傾斜狀。 然後，請參見第2C圖，於同—反應室中，以氣化碳氣 體進行原位餘刻’例如以Μ氣體進行餘刻，以去除該遮 ΐ層上方過多的沈積° #用氟化礙氣體㈣的優點是該氣 2有高選擇比’對於二氧切與氮切之則比約為 HDp之姓可丨以产控制蝕刻時對於溝槽外表面HDP/側壁HDP/底面 HDP之#刻情形。 再者，請參見第2D圖，仍 次的高密度化學氣相沈積程序 面上形成一第二絕緣層1 〇 8 b， 然在同一反應室，進行第二 ，藉此在第一絕緣層108a表 亦為一乳化秒層，其厚度介540135 V. Description of the invention (5) and the pattern of the hafnium oxide layer 101 are used to expose the portion of the semiconductor substrate 100 where the device isolation region is to be formed. Using the pattern of the shielding layer as a mask, a groove is formed in the semiconductor substrate by performing a engraving process, the depth of which is between 5 0 0 A and 6 0 0 A. Then, a thin oxide layer 104 is grown by a thermal oxidation process (< (: |: 160181 oxidation), covering the bottom surface and sidewalls of the trench, 'to be used as a liner, and its thickness is about 18 () A ~ 220A. Among them, 'a thin silicon nitride layer 106 is formed on the surface of the shielding layer and the thin oxide layer in compliance with the above, and is also used as a lining. Next, please refer to FIG. 2B, Perform the first high-density chemical vapor deposition process of the present invention, place the substrate in a reaction chamber, and use high-density chemical vapor deposition, for example, using oxygen (02) and silicon methane (SiH4) as reactants, At the same time, an Ar plasma splash is applied to deposit a first insulating layer 108a 'on the surface of the thin silicon nitride layer, such as a dioxide layer, and the thickness is between 2500 and 3500 (A), usually about 30. 00 A, and due to the characteristics of the high-density plasma chemical vapor deposition method, the sidewall of the trench is inclined. Then, refer to Figure 2C, in the same reaction chamber, the in-situ etching with gasified carbon gas 'For example, with M gas for the remainder to remove excessive deposition above the masking layer. The advantage is that the gas 2 has a high selection ratio. The ratio of dioxygen cutting to nitrogen cutting is about HDp. It is possible to control the etching of the outer surface of the trench HDP / side wall HDP / bottom HDP # when the etching is controlled. For example, referring to FIG. 2D, a second insulating layer 108b is formed on the next high-density chemical vapor deposition process surface, and then a second is performed in the same reaction chamber to thereby form a first insulating layer 108a. It is also an emulsified second layer.
540135 五、發明說明（6) :2一'0入〜350〇a，通常約為3000 A。第二絕緣層1〇此盥 苐一絶緣層1 0 8a共同形成一絕緣層丨〇 8。如此 /、 洞在溝槽中產生的缺點。 、 方止孔 接著，請參見第2E圖，施行一化學性機械， 磨除第二絕緣層！·和第一絕緣層1(^高出氮化石夕層1 的部分，留下二者填在溝槽中的部分，即形成所i汽 槽隔離區。之後，可以適當溶劑或蝕刻程序，依 二二 ^層和墊氧化層1G1而露出元件區，由於 = 重點，在此不予贅述。 ^月 與習知技術相比較，本發明之淺溝槽隔離區製 具有數項優點。首先，本發明方法避免了高深汽 槽，，區製程上可能發生的孔洞缺陷。其次，本發明：“ 用高密度電漿化學氣相沈積程序併用原位敍刻程序，不= 可以解決上述缺點，也不會增加太多處理時間。此外， 的姓刻氣體具有高選擇比，可以控制姓刻時對= 溝槽外表面HDP/側壁HDP/底面HDp之蝕刻情形，因而使、 溝槽以外部分過多的二氧化矽層得以去除。綜上所述，伕 照本發明方法，可以形成具有高深寬比且無孔洞的淺溝样又 隔離區，將有助於提昇淺溝槽隔離區的性質。 曰 —本發明雖以一較佳實施例揭露如上，然其並非用以限 疋^發明，任何熟習此項技藝者，在不脫離本發明之精 和範圍内，當可作些許之更動與潤飾，因此本發明之保 範圍當視後附之申請專利範圍所界定者為準。 °540135 V. Description of the invention (6): 2 ~ 0 ~~ 350〇a, usually about 3000 A. The second insulating layer 108 and an insulating layer 108a together form an insulating layer 08. So, the disadvantage of holes in the trench. Square stop hole Next, refer to Figure 2E, implement a chemical machine to remove the second insulation layer! And the first insulating layer 1 (^ higher than the nitride layer 1 layer, leaving the two filled in the trench portion, that is, the formation of the steam tank isolation area. After that, you can use appropriate solvents or etching procedures, according to Twenty-two layers and the pad oxide layer 1G1 expose the component area. Because = is important, it will not be repeated here. Compared with the conventional technology, the shallow trench isolation system of the present invention has several advantages. First, this The method of the invention avoids the high-deep steam troughs and hole defects that may occur in the zone process. Secondly, the invention: "The use of high-density plasma chemical vapor deposition procedures and in-situ engraving procedures does not = can solve the above-mentioned shortcomings, nor It will increase too much processing time. In addition, the last name engraving gas has a high selection ratio, which can control the etching of the outer surface of the trench HDP / side wall HDP / bottom HDp when the last name is engraved. The silicon oxide layer is removed. In summary, according to the method of the present invention, a shallow trench-like isolation region with high aspect ratio and no holes can be formed, which will help improve the properties of the shallow trench isolation region. Although the invention is better The embodiment is disclosed as above, but it is not intended to limit the invention. Any person skilled in this art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be regarded as The scope of the attached patent application shall prevail. °