CN100388439C - Method for depositing silicide on silicon substrate - Google Patents
Method for depositing silicide on silicon substrate Download PDFInfo
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- CN100388439C CN100388439C CNB2004100930098A CN200410093009A CN100388439C CN 100388439 C CN100388439 C CN 100388439C CN B2004100930098 A CNB2004100930098 A CN B2004100930098A CN 200410093009 A CN200410093009 A CN 200410093009A CN 100388439 C CN100388439 C CN 100388439C
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- silicon nitride
- silicon substrate
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Abstract
The present invention relates to a method for depositing silicide on a silicon substrate, which avoids the influence of the pinhole phenomenon in the prior art on semiconductor devices. The present invention has the steps that a layer of silica dioxide is deposited on a silicon substrate in a PECVD method; then, a layer of silicon nitride is deposited on the silica dioxide; finally, a layer of silicon nitride layer is deposited in an LPCVD method. Because the silicon dioxide layer and the silicon nitride layer are respectively deposited, respective pin holes of the silicon dioxide layer and the silicon nitride layer are mutually staggered, so the influence of the pinhole phenomenon is effectively avoided, and the drain current is reduced.
Description
Technical field
The present invention relates to integrated circuit and make the field, especially relate to a kind of on silicon substrate the method for depositing silicide.
Background technology
Along with development of integrated circuits, the polysilicon live width and between the live width spacing just become more and more narrow, simultaneously, also to the pin hole phenomenon of Salicide block (autoregistration silicon compound barrier layer) and the requirement of the leakage current that causes also is more and more higher.This just requires this tunic of Salicide block not only to require to approach, and will avoid the influence of pin hole phenomenon to device as far as possible.
See also shown in Figure 1, under existing technical situation, general Salicideblock adopts PECVD (Plasma Enhanced Chemicai Vapor DepositiOn usually, electricity slurry enhanced chemical gaseous phase Shen is long-pending) method growthing silica 12 on silicon substrate 11 at first, because the silica 12 of PECVD method growth, a fairly large number of pin hole 121 is all arranged usually, for fear of this phenomenon, have only look as far as possible thick of silica 12, Salicide block is thin as far as possible to run in the opposite direction mutually with the requirement of satisfying the needs that design but this requires with the developing direction of technology now.
Therefore to design a kind of on silicon substrate the method for depositing silicide, its thickness is unlikely to excessive, also can prevent the generation of pin hole phenomenon simultaneously.
Summary of the invention
Technical problem to be solved by this invention provide a kind of on silicon substrate the method for depositing silicide, it can effectively prevent the generation of pin hole phenomenon, guarantees that simultaneously the thickness of the silicide of deposit on silicon substrate is unlikely to excessive.
For finishing above technical problem, the present invention by the following technical solutions, a kind of on silicon substrate the method for depositing silicide, comprising: at first, on silicon substrate, use PECVD mode deposit one layer thickness to be
Silicon dioxide; Then, on described silicon dioxide, use the PECVD mode again deposit one layer thickness be
First silicon nitride; At last, on described first silicon nitride, use the LPCVD mode again deposit one layer thickness be
Second silicon nitride.
Compared with prior art, the invention has the beneficial effects as follows: because silicon dioxide and silicon nitride are divided into two-layer deposit, so its pin hole that produces separately staggers, and seldom can form the pin hole that runs through, guaranteed also that simultaneously the thickness of the silicide of deposit on silicon substrate is unlikely to excessive.
Description of drawings
Fig. 1 be in the prior art on silicon substrate deposit silicon dioxide form the schematic diagram of pin hole.
Fig. 2 be the present invention a kind of on silicon substrate the flow chart of an embodiment of the method for depositing silicide.
Fig. 3 is the structural representation of a kind of silicide that the method for depositing silicide forms on silicon substrate of the present invention.
Fig. 4 is to use in the present invention and the prior art square resistance test result comparison chart of Salicide block on p type single crystal silicon of growing on the silicide of the same thickness that the method at depositing silicide on the silicon substrate forms.
Embodiment
Below in conjunction with drawings and Examples the present invention is further described.
See also Fig. 2 and shown in Figure 3, in the mill, at first also be on silicon substrate 21 earlier with the method growthing silica 22 of PECVD, just the thickness of growth to approach many, be about prior art the technological process growth the silicon dioxide layer thickness about 1/4, be about
Because, the defective that the PECVD method is intrinsic, this moment, the silicon dioxide 22 of growth also had more pin hole 221.
Secondly, the method grown silicon nitride 23 of PECVD is used in technological process of the present invention again on PECVD method growthing silica 22, its thickness be about the growth of prior art processes flow process silicon dioxide thickness about 1/4, be about equally
Though equally also have the pin hole 231 of some with the method grown silicon nitride 23 of PECVD, this moment,, make the phenomenon of pin hole be improved because the pin hole 221 of many pin holes 231 and PECVD method growthing silica 22 staggers mutually.
At last, technological process of the present invention is also on the grown silicon nitride 23 of PECVD method, use LPCVD (Low-pressure Chemical Vapor Deposition again, Low Pressure Chemical Vapor Deposition) the method one deck silicon nitride 24 of having grown again, thickness be about prior art processes flow process growth silicon dioxide thickness about 1/5, be about
Because pin hole 241 phenomenons of the method grown silicon nitride 24 of LPCVD will be lacked, and the pin hole 241 of this moment again with the silicon dioxide 22 of before PECVD method growth on pin hole 221 and the pin hole 231 on the silicon nitride 23 stagger each other, institute is so that the probability of the phenomenon of pin hole appearance has dropped to minimum.
After finishing above-mentioned deposit, carry out some gluings again, SAB mask light shield, steps such as HF etching and Salicide technology.
See also shown in Figure 4, it shows utilizing the PECVD growthing silica and earlier with PECVD growthing silica and silicon nitride, utilizing the LPCVD method of the regrowth silicon nitride square resistance test result of Salicide block on p type single crystal silicon of growing in the above again of same thickness.As seen, the Salicide block with the new process growth has effectively overcome the pin hole phenomenon, and the homogeneity of square resistance is greatly improved.
In sum, the present invention has finished inventor's goal of the invention, because seldom by the pin hole on the silicon nitride layer of LPCVD deposit, and the pin hole of pin hole on silicon dioxide layer and two-layer silicon nitride all can stagger mutually, so the pin hole that runs through does not have basically, can effectively overcome of the influence of the phenomenon of pin hole, reduce leakage current device.In addition, the thickness of each layer is all less, so also meet current trend.
Claims (2)
1. the method for a depositing silicide on silicon substrate is characterized in that: at first, using PECVD mode deposit one layer thickness on silicon substrate is 100
～300
Silicon dioxide; Then, on described silicon dioxide, use the PECVD mode again deposit one layer thickness be 100
～300
First silicon nitride; At last, on described first silicon nitride, use the LPCVD mode again deposit one layer thickness be 50
～200
Second silicon nitride.
2. as claimed in claim 2 on silicon substrate the method for depositing silicide, it is characterized in that: after deposit silicon nitride, also have gluing, SAB mask light shield, HF etching and silicide process step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100930098A CN100388439C (en) | 2004-12-15 | 2004-12-15 | Method for depositing silicide on silicon substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100930098A CN100388439C (en) | 2004-12-15 | 2004-12-15 | Method for depositing silicide on silicon substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1790630A CN1790630A (en) | 2006-06-21 |
| CN100388439C true CN100388439C (en) | 2008-05-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100930098A Active CN100388439C (en) | 2004-12-15 | 2004-12-15 | Method for depositing silicide on silicon substrate |
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| CN (1) | CN100388439C (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030203596A1 (en) * | 2002-04-24 | 2003-10-30 | Nanya Technology Corporation | Manufacturing method of a high aspect ratio shallow trench isolation region |
| US6780731B1 (en) * | 2002-08-22 | 2004-08-24 | Taiwan Semiconductory Manufacturing Co., Ltd. | HDP gap-filling process for structures with extra step at side-wall |
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2004
- 2004-12-15 CN CNB2004100930098A patent/CN100388439C/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030203596A1 (en) * | 2002-04-24 | 2003-10-30 | Nanya Technology Corporation | Manufacturing method of a high aspect ratio shallow trench isolation region |
| US6780731B1 (en) * | 2002-08-22 | 2004-08-24 | Taiwan Semiconductory Manufacturing Co., Ltd. | HDP gap-filling process for structures with extra step at side-wall |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1790630A (en) | 2006-06-21 |
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Effective date of registration: 20171218 Address after: Zuchongzhi road 201203 Shanghai Pudong New Area Zhangjiang High Tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: No. 1188, Chuan Qiao Road, Pudong, Shanghai Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |
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