CN103050382A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- CN103050382A CN103050382A CN2011103152854A CN201110315285A CN103050382A CN 103050382 A CN103050382 A CN 103050382A CN 2011103152854 A CN2011103152854 A CN 2011103152854A CN 201110315285 A CN201110315285 A CN 201110315285A CN 103050382 A CN103050382 A CN 103050382A
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Abstract
The invention relates to a manufacturing method of a semiconductor device. The manufacturing method comprises the following steps of: providing a semiconductor substrate on which a dielectric layer, a first mask layer and a second mask layer are sequentially arranged; forming a side wall on the side surface of the second mask layer; forming a graphical photomask layer which covers the second mask layer, the side wall and the first mask layer; taking the graphical photomask layer as a mask, and sequentially etching the second mask layer, the first mask layer and the dielectric layer. The characteristic size of the formed semiconductor device can be precisely controlled, and the impact on the performance of the semiconductor device is avoided.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of manufacture method of semiconductor device.
Background technology
Along with the development of semiconductor fabrication process, (CD, Critical Dimension) is more and more less for the characteristic size of semiconductor device in the integrated circuit, and be also more and more higher to the requirement of photoetching technique.In order to ensure the feasibility of the manufacturing of smaller szie, Dual graphing (Double Patterning) becomes at 22nm node and following explication thereof and goes out one of potential solution of figure.
Existing Double-patterning method generally comprises three kinds: photoetching-etching-photoetching-etching (LELE, Litho-Etch-Litho-Etch), photoetching-freeze-photoetching-etching (LFLE, Litho-Freeze-Litho-Etch), and interval/self-alignment type double exposure lithography (SADP, Spacer or self-aligned double-patterning).Wherein, LELE refers to follow an etch step after a lithography step, and then follows a photoetching, an etching step.Two above lithography steps all are crucial lithography steps, and it is right namely can to produce repeatedly, and in other words, the figure that lithography step exposes is extremely important with the relative position of the figure that another lithography step exposes.In order to solve the dependence to two cover photomask overlapping accuracies in the LELE technology, the SADP technology becomes main flow technique in the semiconductor fabrication of 22nm node and following magnitude thereof.
But more technology referenced patent about LELE, LFLE number are the United States Patent (USP) of US6042998.
Below in conjunction with accompanying drawing, describe the method that forms semiconductor device with the SADP method in detail.
With reference to figure 1, Semiconductor substrate 100 is provided, on described Semiconductor substrate 100, be formed with successively dielectric layer 110, the first mask layer 120 and the second mask layer 130.Described the second mask layer 130 defines the figure of the semiconductor device of design forming.
With reference to figure 2, form side wall 140 in the side of described the second mask layer 130.
With reference to figure 3, remove described the second mask layer 130, and take described side wall 140 as mask, take described dielectric layer 110 as stop-layer, described the first mask layer 120 of etching forms structure as shown in Figure 4.
With reference to figure 5, process deposition of antiglare layer 150 covers described the first mask layer 120 and described dielectric layer 110, and is coated with photoresist at described anti-reflecting layer 150, forms patterned photoresist 160 after the photoetching.
With reference to figure 6, take described patterned photoresist 160 as mask described anti-reflecting layer 150 and dielectric layer 110 are carried out etching, to form the semiconductor device of design.
When in the back-end process that semiconductor is made, forming through hole or groove at present, usually can select to have the titanium nitride (TiN) of higher etching selection ratio as the first mask layer.But the semiconductor device that utilizes above-mentioned prior art to form exists the coarse problem of size of its formation, thereby has affected the performance of semiconductor device.With reference to figure 6, the design size of described semiconductor device is S1 shown in Figure 6, but the S2 that the size that in fact forms may be as shown in Figure 6.This shows, utilize the semi-conductive actual size that prior art forms may be greater than the size of design, thereby affected the performance of semiconductor device.
Therefore, how accurately to control the characteristic size of semiconductor device, become those skilled in the art's problem demanding prompt solution with the performance that improves semiconductor device.
Summary of the invention
The problem that the present invention solves provides a kind of manufacture method of semiconductor device, with the size of accurately controlling semiconductor device and the performance that effectively improves semiconductor device.
For addressing the above problem, the invention provides a kind of manufacture method of semiconductor device, described method comprises:
Semiconductor substrate is provided, is formed with successively dielectric layer, the first mask layer and the second mask layer on the described Semiconductor substrate;
Side at described the second mask layer forms side wall;
Form patterned photo mask layer, cover described the second mask layer, side wall and the first mask layer;
Take described patterned photo mask layer as mask, successively described the second mask layer of etching, the first mask layer and dielectric layer.
Alternatively, the material of described dielectric layer is advanced low-k materials or ultra-low dielectric constant material.
Alternatively, the opening size of described patterned photo mask layer is greater than the characteristic size of described the second mask layer.
Alternatively, described the first mask layer is metal hard mask layer.
Alternatively, the material of described the first mask layer comprises titanium nitride, boron nitride or both combinations.Alternatively, the thickness of described the first mask layer is less than or equal to
Alternatively, the material of described the second mask layer is silica; The material of described side wall is silicon nitride.
Alternatively, take described patterned photo mask layer as mask, successively described the second mask layer of dry etching, the first mask layer and dielectric layer.
Alternatively, the manufacture method of described semiconductor device also comprises:
Remove described patterned photo mask layer, and take described side wall as mask etching remaining the first mask layer and part dielectric layer;
Remove described side wall, and take the first mask layer as mask, the remaining dielectric layer of etching.
Alternatively, remove described patterned photo mask layer, and take described side wall as the mask dry etching remaining the first mask layer and part dielectric layer.
Alternatively, wet etching is removed described side wall, and take the first mask layer as mask, the remaining dielectric layer of dry etching.
Alternatively, the manufacture method of described semiconductor device also comprises: after the side of described the second mask layer forms side wall, and before forming patterned photo mask layer, described side wall is carried out linearity cut.
Compared with prior art, technique scheme has the following advantages:
By adjusting part steps of the prior art, simultaneously as mask, form semiconductor device with etching with side wall and the first mask layer.Like this, by increasing side wall as mask, form in the semiconductor device process in etching, the actual size of formed semiconductor device can not appear greater than the dimensional problem of its design, thereby can accurately control the characteristic size of formed semiconductor device, avoided the impact on performance of semiconductor device.
Description of drawings
Fig. 1～Fig. 6 is the schematic diagram of the manufacture method of semiconductor device in the prior art;
Fig. 7 is the schematic flow sheet of the manufacture method of semiconductor device of the present invention;
Fig. 8～Figure 15 is the schematic diagram of using the manufacture method formation through hole of semiconductor device of the present invention in the metal line of back-end process;
Figure 16 is the plan structure schematic diagram of semiconductor device shown in Figure 9;
Figure 17 is the plan structure schematic diagram after the side wall linearity to semiconductor device shown in Figure 9 cuts.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
Just as described in the background section, the semiconductor device that utilizes above-mentioned prior art to form exists the coarse problem of its size, and the actual size of the semiconductor device that namely forms may be greater than the size of its design, thereby has affected the performance of semiconductor device.
The inventor finds by after analyzing, exist the reason of the problems referred to above to be: to adopt prior art, take patterned photoresist as mask antagonistic reflex layer and dielectric layer carry out (with reference to shown in Figure 6) in the process of etching, the first thinner mask layer 120 may be etched away, thereby so that the actual size (S2 as shown in Figure 6) of the semiconductor device that forms is greater than the size (S1 as shown in Figure 6) of its design, and then the performance of semiconductor device produced harmful effect.
In order to overcome the problems referred to above, the invention provides a kind of manufacture method of semiconductor device, with reference to figure 7, described manufacture method comprises:
Step S11 provides Semiconductor substrate, is formed with successively dielectric layer, the first mask layer and the second mask layer on the described Semiconductor substrate;
Step S12 forms side wall in the side of described the second mask layer;
Step S13 forms patterned photo mask layer, covers described the second mask layer, side wall and the first mask layer;
Step S14, take described patterned photo mask layer as mask, successively described the second mask layer of etching, the first mask layer and dielectric layer.
Method provided by the invention, when etching forms semiconductor device, with side wall and the first mask layer simultaneously as mask, like this by increasing side wall as mask, form in the semiconductor device process in etching, can it not etched away because the first mask layer is thinner, and then the actual size of formed semiconductor device appears greater than the problem of the size of design, thereby method provided by the invention can accurately control the characteristic size of formed semiconductor device, avoids the impact on performance of semiconductor device.
Below in conjunction with Fig. 8 to Figure 17, and method of the present invention is elaborated as example in the metal line of back-end process, to form through hole.
With reference to figure 8, the Semiconductor substrate (not shown) is provided, be formed with cushion oxide layer 200 on the described Semiconductor substrate, wherein, be formed with successively dielectric layer 210, the first mask layer 220 and the second mask layer 230 on the described cushion oxide layer 200.
Particularly, be formed with device in the described Semiconductor substrate, such as resistance, electric capacity, MOS transistor and interconnection structure etc.
The material of described dielectric layer 210 can be silica, advanced low-k materials or the ultra-low dielectric constant material of silica, doping.In the present embodiment, the material of described dielectric layer 210 is advanced low-k materials or ultra-low dielectric constant material.The formation technique of described dielectric layer 210 can be existing depositing operation, for example, can increase chemical vapor deposition method or inferior aumospheric pressure cvd technique for plasma, and this is well known to those skilled in the art, so do not repeat them here.
In the present embodiment, described the first mask layer 220 is metal hard mask layer, and its material is titanium nitride (TiN), boron nitride (BN) or its both combination, and the thickness of described the first mask layer 220 is less than or equal to
But this can not limit protection scope of the present invention, and in other embodiments, described the first mask layer 220 can also adopt other materials, and this knows for those skilled in the art, so do not repeat them here.
Described the second mask layer 230 is used for defining the size of metal connecting line, and its material can be silica.
With reference to figure 9, form side wall 240 in the side of described the second mask layer 230.
Wherein, the material of described side wall 240 can be a kind of in silica, silicon nitride, the silicon oxynitride or they make up arbitrarily.In the present embodiment, have higher selection ratio in order to make described side wall 240 and described the second mask layer 230 in etching, the material of described side wall 240 is silicon nitride.In addition, the formation technique of described side wall 240 is known for those skilled in the art, so do not repeat them here.
With reference to Figure 10, form patterned photo mask layer, cover described the second mask layer 230, side wall 240 and the first mask layer 220.
In the present embodiment, at first process deposition of antiglare layer 250, cover described the second mask layer 230, side wall 240 and the first mask layer 220, then form patterned photoresist layer 260 at described anti-reflecting layer 250, described anti-reflecting layer 250 and patterned photoresist layer 260 consist of patterned photo mask layer.
Particularly, described anti-reflecting layer 250 can form by the mode of physical vapour deposition (PVD) (PVD) or chemical vapour deposition (CVD) (CVD).Described anti-reflecting layer 250 is bottom layer anti-reflection layer (BARC, Bottom Anti-Reflective Coating), and it can be organic BARC or inorganic BARC.Because the chemical property of inorganic BARC is general and its lower caldding layer is similar, can effectively remove, and, inorganic BARC has higher selectivity than organic BARC in etching, so be preferably inorganic BARC in the present embodiment, form described inorganic BARC with method depositing silicon nitrogen oxide or the silicon-nitride layer of plasma enhanced chemical vapor deposition (PECVD).
The formation method of described patterned photoresist layer 260 is well known to those skilled in the art, for example, can adopt spin coating proceeding, spin coating one deck photoresist on described anti-reflecting layer 250, behind the overbaking post bake, adopt lithographic equipment that photoresist layer is exposed, develops, form described patterned photoresist layer 260.Wherein, described patterned photoresist layer 260 has opening 270, and the size of described opening 270 is greater than the size of described the second mask layer 230 defined metal connecting lines.
Need to prove that in other embodiments, described photo mask layer also can form other structures according to the actual requirements, for example, do not comprise described anti-reflecting layer 250.Those skilled in the art also can do similar popularization to it, only for illustrating, should not limit protection scope of the present invention in the present embodiment.
With reference to Figure 11, take described patterned photoresist layer 260 as mask, the successively described anti-reflecting layer 250 of etching, the second mask layer 230, the first mask layer 220 and dielectric layer 210.
In the present embodiment, the method that adopts dry etching is the described anti-reflecting layer 250 of etching, the second mask layer 230, the first mask layer 220 and dielectric layer 210 successively.Particularly, take described patterned photoresist layer 260 as mask described anti-reflecting layer 250 is carried out dry etching, to expose described side wall 240; Then, take described patterned photoresist layer 260 and side wall 240 as mask described the second mask layer 230, the first mask layer 220 are carried out dry etching; At last, take described patterned photoresist layer 260, described side wall 240 and the first mask layer 220 as mask described dielectric layer 210 is carried out dry etching.The method of described dry etching is well known to those skilled in the art, so do not repeat them here.
With reference to Figure 12 and Figure 13, remove described patterned photoresist layer 260 and anti-reflecting layer 250, and take described side wall 240 as mask etching remaining the first mask layer 220 and part dielectric layer 210.
Particularly, at first remove described patterned photoresist layer 260 and anti-reflecting layer 250, form structure as shown in figure 12.The method of the described patterned photoresist layer 260 of described removal and anti-reflecting layer 250 is known for those skilled in the art, so do not repeat them here.
Then, with reference to Figure 13, remaining the first mask layer 220 and part dielectric layer 210 take described side wall 240 as the mask dry etching.The method of described dry etching is what know for those skilled in the art, so do not repeat them here.
With reference to Figure 14 and Figure 15, remove described side wall 240, and take the first mask layer 220 as mask, the remaining dielectric layer 210 of etching.
Particularly, wet etching is removed described side wall 240, forms structure as shown in figure 14.In the present embodiment, the material of described side wall 240 is silicon nitride, and therefore, the liquid of described wet etching can be phosphoric acid.The method of described wet etching is well known to those skilled in the art, so do not repeat them here.
With reference to Figure 15, take the first mask layer 220 as mask, the remaining dielectric layer 210 of dry etching is with final formation through hole.The method of described dry etching is well known to those skilled in the art, so do not repeat them here.
In successive process, metal interconnected in order to realize, also need the step such as plated metal in the through hole, itself and prior art similar is well known to those skilled in the art, so do not repeat them here.
In addition, need to prove, in other embodiments, can be after the side of described the second mask layer 230 formation side wall 240 (with reference to figure 9), and before process deposition of antiglare layer 250 (with reference to Figure 10), increase described side wall 240 is carried out the step that linearity cuts.
Wherein, Figure 16 is the plan structure schematic diagram of semiconductor device shown in Figure 9, and Figure 17 is the schematic top plan view after side wall 240 linearities to semiconductor device shown in Figure 9 cut.
Particularly, with reference to figure 9 and Figure 16, after the side of described the second mask layer 230 forms side wall 240, the side-looking structure of described side wall 240 as shown in figure 16, namely described side wall 240 is around surrounding described the second mask layer 230.But described side wall 240 is parallel to the two side portions of A-A ' direction and is not used in the size of definition metal connecting line, carrying out for the ease of subsequent technique, reduce the impact on other sizes in the semiconductor device, need to remove the two side portions that described side wall 240 is parallel to A-A ' direction, to form structure as shown in figure 17.In the present embodiment, adopt dry etching to remove the two side portions that described side wall 240 is parallel to A-A ' direction.Certainly, in other embodiments, can also adopt additive method of the prior art, this is well known to those skilled in the art, so do not repeat them here.
Similarly, in FEOL, also can adopt the manufacture method of semiconductor device of the present invention to form contact hole or groove etc.Only for illustrating, it should not limit protection scope of the present invention to previous embodiment, and those skilled in the art can spirit according to the present invention do similar popularization.
To sum up, the manufacture method of the semiconductor device of the technical program has following beneficial effect at least:
Utilize the semiconductor device of the method formation of present embodiment, its actual size can not occur greater than the situation of its design size.This be because, when the present invention forms required semiconductor device in etching, described side wall 240 and described the first mask layer 220 have avoided the first thinner mask layer 220 to be etched away simultaneously as mask, and then cause the actual size of the semiconductor device that forms greater than the size of design.Therefore, the manufacture method of the semiconductor device of the technical program can accurately be controlled the characteristic size of formed semiconductor device, improves the performance of semiconductor device.
Although the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.
Claims (13)
1. the manufacture method of a semiconductor device is characterized in that, comprising:
Semiconductor substrate is provided, is formed with successively dielectric layer, the first mask layer and the second mask layer on the described Semiconductor substrate;
Side at described the second mask layer forms side wall;
Form patterned photo mask layer, cover described the second mask layer, side wall and the first mask layer;
Take described patterned photo mask layer as mask, successively described the second mask layer of etching, the first mask layer and dielectric layer.
2. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the material of described dielectric layer is advanced low-k materials or ultra-low dielectric constant material.
3. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the opening size of described patterned photo mask layer is greater than the size of described the second mask layer.
4. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, described the first mask layer is metal hard mask layer.
5. the manufacture method of semiconductor device as claimed in claim 4 is characterized in that, the material of described the first mask layer comprises titanium nitride, boron nitride or both combinations.
6. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the thickness of described the first mask layer is less than or equal to
7. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the material of described the second mask layer is silica; The material of described side wall is silicon nitride.
8. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, take described patterned photo mask layer as mask, and successively described the second mask layer of dry etching, the first mask layer and dielectric layer.
9. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, also comprises:
Remove described patterned photo mask layer, and take described side wall as mask etching remaining the first mask layer and part dielectric layer;
Remove described side wall, and take the first mask layer as mask, the remaining dielectric layer of etching.
10. the manufacture method of semiconductor device as claimed in claim 9 is characterized in that, removes described patterned photo mask layer, and take described side wall as the mask dry etching remaining the first mask layer and part dielectric layer.
11. the manufacture method of semiconductor device as claimed in claim 9 is characterized in that, wet etching is removed described side wall, and take the first mask layer as mask, the remaining dielectric layer of dry etching.
12. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, also comprises: after the side of described the second mask layer forms side wall, and before forming patterned photo mask layer, described side wall is carried out linearity cut.
13. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that, adopts dry etching that described side wall is carried out linearity and cuts.
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| CN201110315285.4A CN103050382B (en) | 2011-10-17 | 2011-10-17 | Manufacturing method of semiconductor device |
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| CN201110315285.4A CN103050382B (en) | 2011-10-17 | 2011-10-17 | Manufacturing method of semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104217942A (en) * | 2013-06-04 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of semiconductor device |
| CN111627801A (en) * | 2019-02-28 | 2020-09-04 | 中芯国际集成电路制造(北京)有限公司 | Method for forming semiconductor structure |
| CN114334613A (en) * | 2022-03-14 | 2022-04-12 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
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| CN101536160A (en) * | 2006-11-15 | 2009-09-16 | 美光科技公司 | Methods of etching a pattern layer to form staggered heights therein and intermediate semiconductor device structures |
| KR20100027995A (en) * | 2008-09-03 | 2010-03-11 | 신에쓰 가가꾸 고교 가부시끼가이샤 | Patterning process |
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| JPS6435916A (en) * | 1987-07-31 | 1989-02-07 | Hitachi Ltd | Formation of fine pattern |
| CN101536160A (en) * | 2006-11-15 | 2009-09-16 | 美光科技公司 | Methods of etching a pattern layer to form staggered heights therein and intermediate semiconductor device structures |
| CN101335185A (en) * | 2007-06-29 | 2008-12-31 | 海力士半导体有限公司 | Method for forming pattern in semiconductor device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104217942A (en) * | 2013-06-04 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of semiconductor device |
| CN104217942B (en) * | 2013-06-04 | 2017-11-10 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor devices |
| CN111627801A (en) * | 2019-02-28 | 2020-09-04 | 中芯国际集成电路制造(北京)有限公司 | Method for forming semiconductor structure |
| CN111627801B (en) * | 2019-02-28 | 2023-08-01 | 中芯国际集成电路制造(北京)有限公司 | Method for forming semiconductor structure |
| CN114334613A (en) * | 2022-03-14 | 2022-04-12 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
| CN114334613B (en) * | 2022-03-14 | 2022-06-17 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
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