CN102522370B - The formation method of contact hole - Google Patents
The formation method of contact hole Download PDFInfo
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- CN102522370B CN102522370B CN201110436358.5A CN201110436358A CN102522370B CN 102522370 B CN102522370 B CN 102522370B CN 201110436358 A CN201110436358 A CN 201110436358A CN 102522370 B CN102522370 B CN 102522370B
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Abstract
A formation method for contact hole, comprising: provide Semiconductor substrate; Form dielectric layer and the first resilient coating successively on a semiconductor substrate; First resilient coating is formed the first hard mask layer pattern of multiple line style; First hard mask layer pattern and the first resilient coating form the second resilient coating; Second resilient coating is formed the second hard mask layer pattern of multiple line style; Second hard mask layer pattern and the underlapped region of the first hard mask layer pattern form multiple contact hole pattern; With the second hard mask layer pattern and the first hard mask layer pattern for mask, etching the second resilient coating and the first resilient coating to exposing dielectric layer, forming the first resilient coating pattern; Remove the second hard mask layer pattern, the second resilient coating and the first hard mask layer pattern; With the first resilient coating pattern for mask, etch media layer, to exposing Semiconductor substrate, forms the dielectric layer pattern comprising multiple contact hole; Remove the first resilient coating pattern.The present invention can form the contact hole of reduced size.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of formation method of contact hole.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach arithmetic speed, larger memory data output and more function faster, wafer is towards higher component density, high integration future development, and the grid of metal oxide semiconductor device (MOS) becomes more and more thinner and length becomes shorter.The manufacturing technology of semiconductor device will enter 11nm process node.Wherein, contact hole technique most challenge.Up to the present, the report about 11nm device published is little, even laboratory device is also like this.Lithographic capabilities is the important index of 11nm technology node the next item up.
Number of patent application be 200510055489.3 Chinese patent disclose a kind of manufacture method of self-aligned contact hole.The generalized section of Fig. 1 ~ Fig. 4 corresponding structure of each step of manufacture method of self-aligned contact hole disclosed in this patent.
As shown in Figure 1, first semiconductor substrate 100 is provided, semiconductor substrate 100 is formed with multiple grid structure, wherein said grid structure is formed by the first stacking hard mask layer 102 and grid conductive layer 101, the described semiconductor substrate 100 being formed with grid structure forms etching barrier layer 103, described etching barrier layer 103 forms insulating barrier 104.
As shown in Figure 2, by insulating barrier 104 described in chemico-mechanical polishing planarization, and the etching barrier layer 103 on described first hard mask layer 102 is exposed.Described insulating barrier 104 is formed the second hard mask layer 105, and spin coating photoresist 106 on described second hard mask layer 105 also forms contact hole pattern by exposure imaging.
As shown in Figure 3, etch described second hard mask layer 105 and the contact hole pattern in described photoresist 106 is transferred in the second hard mask layer 105, remove described photoresist 106.
In conjunction with as shown in Figure 4, using the second hard mask layer 105 as barrier layer, etch described insulating barrier 104 and form contact hole 107, till the etching barrier layer 103 be etched on the substrate between grid structure exposes.Meanwhile, the second hard mask layer 105 is also etched away as sacrifice layer.
In prior art, the size of contact hole 107 is subject to the restriction of photoetching process.As: in order to obtain the contact hole 107 being of a size of 11nm, then must operation technique node be the mask aligner of 11nm.But the minimum half-pitch size of the contact hole that state-of-the-art mask aligner (Immersion ArF Lithography machine) obtains is 55nm in employing prior art, therefore adopt prior art just cannot realize.
Therefore, the contact hole how forming smaller szie just becomes those skilled in the art's problem demanding prompt solution.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of contact hole of smaller szie.
For solving the problem, the invention provides a kind of formation method of contact hole, comprising:
Semiconductor substrate is provided;
Form dielectric layer and the first resilient coating successively on the semiconductor substrate;
Described first resilient coating is formed the first hard mask layer pattern of multiple line style;
Described first hard mask layer pattern and described first resilient coating form the second resilient coating;
Described second resilient coating is formed the second hard mask layer pattern of multiple line style; Described second hard mask layer pattern and the underlapped region of described first hard mask layer pattern form multiple contact hole pattern;
With described second hard mask layer pattern and the first hard mask layer pattern for mask, etching described second resilient coating and the first resilient coating to exposing dielectric layer, forming the first resilient coating pattern;
Remove described second hard mask layer pattern, the second resilient coating and the first hard mask layer pattern;
With described first resilient coating pattern for mask, etching described dielectric layer to exposing Semiconductor substrate, forming the dielectric layer pattern comprising multiple contact hole;
Remove described first resilient coating pattern.
Alternatively, the material of described first resilient coating is identical with the material of described second resilient coating.
Alternatively, the etching selection ratio of described first resilient coating and described dielectric layer is less than or equal to 2.
Alternatively, the material of described dielectric layer comprises: silicon dioxide; The material of described first resilient coating comprises: polysilicon or silicon nitride.
Alternatively, the material of described first hard mask layer pattern is identical with the material of described second hard mask layer pattern.
Alternatively, the etching selection ratio of described first resilient coating and described first hard mask layer pattern is more than or equal to 10.
Alternatively, the material of described first resilient coating comprises: polysilicon or silicon nitride; The material of described first hard mask layer pattern comprises: silicon dioxide.
Alternatively, the thickness range of described dielectric layer comprises:
extremely
Alternatively, the thickness range of the first hard mask layer pattern comprises:
Alternatively, described first hard mask layer pattern adopts self-alignment type double exposure photolithographic process to be formed.
Alternatively, described second hard mask layer pattern adopts self-alignment type double exposure photolithographic process to be formed.
Alternatively, the step removing described first resilient coating pattern comprises: in the dielectric layer pattern comprising multiple contact hole, fill protective layer; Etching removes described first resilient coating pattern; Remove described protective layer.
Alternatively, described first hard mask layer pattern is the straight line of longitudinally arrangement.
Alternatively, described second hard mask layer pattern is the straight line of laterally arrangement.
Compared with prior art, the present invention has the following advantages: a kind of formation method providing contact hole, the line of bidimensional is first adopted to form contact hole pattern in the first resilient coating, and then the contact hole pattern in the first resilient coating is transferred in dielectric layer, finally achieve and form multiple contact hole in the dielectric layer.Due to the size of line can do very little, the size of center line of the present invention determines the size of contact hole, and the formation process of line is fairly simple, cost is low, therefore finally can form the smaller contact hole of size simply.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is the generalized section of the manufacture method corresponding construction of existing a kind of self-aligned contact hole;
Fig. 5 is the schematic flow sheet of the formation method of contact hole in embodiment of the present invention;
Fig. 6 to Figure 29 is the schematic diagram of the formation method of embodiment of the present invention contact hole.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.
Just as described in the background section, in prior art, the size of contact hole is subject to the restriction of photoetching process technology node, and the size of Photolithography Technology node equals the minimum dimension of contact hole.Particularly, the minimum half-pitch size adopting the contact hole that state-of-the-art mask aligner (Immersion ArF Lithography machine) obtains in prior art is 55nm.
For above-mentioned defect, inventor finds through research: the formation method of prior art center line (line) is simpler than the formation method of contact hole (hole), and the dimension limit of line can be less than the dimension limit of contact hole, therefore can form contact hole by line, finally can reduce the size of contact hole.
Be described in detail below in conjunction with accompanying drawing.
Shown in figure 5, the invention provides a kind of formation method of contact hole, comprising:
Step S1, provides Semiconductor substrate;
Step S2, forms dielectric layer and the first resilient coating on the semiconductor substrate successively;
Step S3, described first resilient coating is formed the first hard mask layer pattern of multiple line style;
Step S4, described first hard mask layer pattern and described first resilient coating form the second resilient coating;
Step S5, described second resilient coating is formed the second hard mask layer pattern of multiple line style; Described second hard mask layer pattern and the underlapped region of described first hard mask layer pattern form multiple contact hole pattern;
Step S6, with described second hard mask layer pattern and the first hard mask layer pattern for mask, etching described second resilient coating and the first resilient coating to exposing dielectric layer, forming the first resilient coating pattern;
Step S7, removes described second hard mask layer pattern, the second resilient coating and the first hard mask layer pattern;
Step S8, with described first resilient coating pattern for mask, etches described dielectric layer to exposing Semiconductor substrate, forms the dielectric layer pattern comprising multiple contact hole;
Step S9, removes described first resilient coating pattern.
The present invention forms resilient coating (bufferlayer) on the dielectric layer (Realholelayer) that really will form contact hole, and then utilize the line of bidimensional (2D) to form contact hole pattern, first contact hole pattern is formed in resilient coating (bufferholelayer), then the contact hole pattern in resilient coating is transferred in dielectric layer.
Wherein, described contact hole can be arbitrary hole in technical field of manufacturing semiconductors.Particularly, it may be used for forming grid, contact plunger etc.
Wherein, described contact hole is arranged in described dielectric layer, and therefore described dielectric layer can be arbitrary interlayer dielectric layer (ILD).
First, shown in figure 6, provide Semiconductor substrate 100.
Described Semiconductor substrate 100 can be silicon or SiGe, can comprise the devices such as metal-oxide-semiconductor in described Semiconductor substrate 100, and can also comprise for realizing the plain conductor be electrically connected, the present invention is not restricted this.
Then, shown in figure 7, described Semiconductor substrate 100 forms dielectric layer 200.
Wherein, the material of described dielectric layer 200 can be silicon dioxide (SiO
2).The formation process of described dielectric layer 200 is known for those skilled in the art, does not repeat them here.
Wherein, the thickness range of described dielectric layer 200 can comprise:
extremely
as:
or
Then, shown in figure 8, described dielectric layer 200 forms the first resilient coating 300.
Described first resilient coating 300 is the smaller the better with the etching selection ratio of described dielectric layer 200, thus can reduce the thickness of the first resilient coating 300, and then can improve the speed of subsequent etching.Described in the present embodiment, the first resilient coating 300 can be less than or equal to 2 with the etching selection ratio of described dielectric layer 200.
Wherein, etching selection ratio refers to the ratio of the etch rate of etching two kinds of different materials; Etch rate refers to the speed of certain material of etching in etching single bit time.
As an example, described first resilient coating 300 can be 1 with the etching selection ratio of described dielectric layer 200, thus the thickness of the first resilient coating 300 equals or less times greater than the thickness of described dielectric layer 200.Particularly, the material of described first resilient coating 300 can be polysilicon (poly), and its thickness range also comprises:
extremely
as:
or
As another example, described first resilient coating 300 can be 1/3 with the etching selection ratio of described dielectric layer 200, thus the thickness of the first resilient coating 300 equals or less times greater than 1/3rd thickness of described dielectric layer 200.Particularly, the material of described first resilient coating 300 can be silicon nitride (SiN), and its thickness range can comprise:
extremely
as:
or
Described first resilient coating 300 can adopt the method such as physical vapour deposition (PVD) (PVD) or chemical vapour deposition (CVD) (CVD) to be formed, and it does not limit the scope of the invention.
Then, shown in figure 9, described first resilient coating 300 forms the first hard mask layer 400.
Described first resilient coating 300 is the bigger the better with the etching selection ratio of described first hard mask layer 400, thus when the first resilient coating 300 that subsequent etching is not covered by the first hard mask layer 400, the first hard mask layer 400 can be protected not corroded simultaneously.Described in the present embodiment, the first resilient coating 300 can be more than or equal to 10 with the etching selection ratio of described first hard mask layer 400, as: 10,50 or 100 etc.
Wherein, the material of described first hard mask layer 400 is specifically as follows silicon dioxide (SiO
2).
Wherein, the thickness range of described first hard mask layer 400 can comprise:
as:
or
It should be noted that, although the material of the first hard mask layer 400 and dielectric layer 200 can be silicon dioxide, but when selecting different etching gas to etch, then this is two-layer very large with the etching selection ratio difference of the first resilient coating 300, it is known for those skilled in the art, does not repeat them here.
Then, with reference to shown in Figure 10, described first hard mask layer 400 forms the first photoresist layer 500.
Described first photoresist layer 500 can be arbitrary Other substrate materials, and it is not restricted this.
Then, with reference to shown in Figure 11, patterned process is carried out to described first photoresist layer 500, form the first photoetching agent pattern 500a comprising multiple longitudinally arrangements.
First photoetching agent pattern 500a described in the present embodiment can be straight-line pattern.
Then, with reference to shown in Figure 12, with described first photoetching agent pattern 500a for mask, etch described first hard mask layer 400, transfer on the first hard mask layer 400 by the first photoetching agent pattern 500a, and cineration technics can be adopted to remove described first photoetching agent pattern 500a.The first hard mask layer after etching comprises the first hard mask layer pattern 400a of multiple longitudinally arrangement.
First hard mask layer pattern 400a described in the present embodiment is straight line, and the distance between the first adjacent hard mask layer pattern 400a is D.
Distance D between adjacent described first hard mask layer pattern 400a determines the size of the contact hole of follow-up formation.In order to obtain contact hole little as far as possible, the distance D between adjacent described first hard mask layer pattern 400a also should be little as far as possible.
Preferably, the present embodiment can adopt self-alignment type double exposure lithography (SADP, Spacerorself-aligneddouble-patterning) technique to be formed, thus the technology node of mask aligner can be made to reduce half.It roughly comprises the following steps:
With reference to shown in Figure 13, before formation first photoetching agent pattern 500a, first barrier layer 410, the 3rd hard mask layer 430 and the second barrier layer 450 successively on the first hard mask layer 400; Then on the second barrier layer 450, the first photoetching agent pattern 500a is formed.Described first photoetching agent pattern 500a is longitudinal straight line.
With reference to shown in Figure 14, with described first photoetching agent pattern 500a for mask, etch described second barrier layer 450 and the 3rd hard mask layer 430 successively, the first photoetching agent pattern 500a is transferred on the second barrier layer 450 and the 3rd hard mask layer 430, form the second barrier layer pattern 450a and the 3rd hard mask layer pattern 430a, and remove described first photoetching agent pattern 500a.
With reference to shown in Figure 15, remove described second barrier layer pattern 450a; Existing side wall technique is adopted to form side wall 480 in the side of each described 3rd hard mask layer pattern 430a.
With reference to shown in Figure 16, remove described 3rd hard mask layer pattern 430a.
With reference to shown in Figure 17, with described side wall 480 for mask, etch described first barrier layer 410 and the first hard mask layer 400, form the first barrier layer pattern 410a and the first hard mask layer pattern 400a.
With reference to shown in Figure 18, remove described side wall 480 and the first barrier layer pattern 410a successively, form the first hard mask layer pattern 400a be positioned on the first resilient coating 300.
When adopting mask aligner can only form at most two the first photoetching agent pattern 500a on the second barrier layer 450, by in above-mentioned SADP technique, finally can form four the first hard mask layer pattern 400a on the first resilient coating 300, thus the distance reduced between line, make the width of the first hard mask layer pattern 400a be the half of photoetching machine technique node, and the distance between adjacent first hard mask layer pattern 400a also can reduce half.
Define four the first hard mask layer pattern 400a in the present embodiment, it is only citing, the quantity of described first hard mask layer pattern 400a can be greater than 1 arbitrary integer.
Then, with reference to shown in Figure 19, described first hard mask layer pattern 400a and the first resilient coating 300 form the second resilient coating 600.
Described second resilient coating 600 covers described first hard mask layer pattern 400a, namely there is certain distance difference between the upper surface of the first hard mask layer pattern 400a and the upper surface of the second resilient coating 600, thus the second hard mask layer pattern of the first hard mask layer pattern 400a and follow-up formation can be kept apart by the second resilient coating 600.
The material of described second resilient coating 600 can be identical with the material of the first resilient coating, and its thickness (namely from the distance between upper surface to the second resilient coating 600 upper surface of the first resilient coating 300) also can comprise:
extremely
as:
or
Described second resilient coating 600 also can be less than or equal to 2 with the etching selection ratio of described dielectric layer 200, and it is identical with the first resilient coating 300, does not repeat them here.
Then, with reference to shown in Figure 20, described second resilient coating 600 forms the second hard mask layer 700.
The material of described second hard mask layer 700 can be identical with the material of described first hard mask layer 400.The thickness range of described second hard mask layer 700 can comprise:
as:
or
particularly, the thickness of described second hard mask layer 700 can be identical with the thickness of described first hard mask layer 400, also can be different.
Described first resilient coating 300 or the second resilient coating 600 are the bigger the better with the etching selection ratio of described second hard mask layer 700; thus when the first resilient coating 300 that subsequent etching is not covered by the second hard mask layer 700 or the second resilient coating 600, the second hard mask layer 700 can be protected not corroded simultaneously.First resilient coating 300 described in the present embodiment or the second resilient coating 600 can be more than or equal to 10 with the etching selection ratio of described second hard mask layer 700, as: 10,50 or 100 etc.Specifically with reference to the first hard mask layer 400, can not repeat them here.
Then, with reference to shown in Figure 21, described second hard mask layer 700 forms the second photoresist layer 800.
The present invention does not limit the material of the second photoresist layer 800 equally.
Then, with reference to shown in Figure 22, photoetching treatment is carried out to described second photoresist layer 800, form the second photoetching agent pattern 800b of multiple laterally arrangement.
Described second photoetching agent pattern 800b can be straight line, thus the second photoetching agent pattern 800b is mutually vertical with the first hard mask layer pattern 400a.
Then, in conjunction with described in reference diagram 23, with the second photoetching agent pattern 800b for mask, etch described second hard mask layer 700, form the second hard mask layer pattern 700b, and remove the second photoetching agent pattern 800b.Thus the second photoetching agent pattern 800b has been transferred to the second hard mask layer 700.
The present embodiment, for three described second hard mask layer pattern 700b, namely defines three straight lines of laterally arranging.In other embodiments of the invention, the quantity of described second hard mask layer pattern 700b can also be the integer that other are greater than 1.
It should be noted that, described second hard mask layer pattern 700b also can adopt SADP technique to be formed, and specifically with reference to the forming process of the first hard mask layer pattern 400a, can not repeat them here.
Distance between the second hard mask layer pattern 700b adjacent in the present embodiment is d, and it equally also determines the size of contact hole.
The underlapped region of described second hard mask layer pattern 700b and described first hard mask layer pattern 400a forms multiple contact hole pattern.It should be noted that, described first hard mask layer pattern 400a can also be made in the present embodiment to be the straight line of laterally arranging, and described second hard mask layer 700b is the straight line of longitudinally arrangement; Described second hard mask layer pattern 700b and described first hard mask layer pattern 400a also can be the straight line of arranging to other directions, and it is all in protection scope of the present invention.Described first hard mask layer pattern 400a and described second hard mask layer pattern 700b intersects to form multiple contact hole pattern.
Then, with reference to shown in Figure 24, with described second hard mask layer pattern 700b for mask, described second resilient coating 600 is etched; After exposing the first not corresponding with the second hard mask layer pattern 700b hard mask layer pattern 400a, then simultaneously with the first hard mask layer pattern 400a and the second hard mask layer pattern 700b for mask, continue etching second resilient coating 600 to exposing the first resilient coating 300, to form the second resilient coating pattern 600c.
Particularly, can described second resilient coating 600 of using plasma method for selective etching etching.Because the etching selection ratio of the second resilient coating 600 and the second hard mask layer pattern 700b or the first hard mask layer pattern 400a is very large, and the thickness of the second resilient coating 600 is less, therefore at etching second resilient coating 600 in the process exposing the first resilient coating 400, the second hard mask layer pattern 700b and the first hard mask layer pattern 400a is not corroded substantially.
Now, with reference to shown in Figure 25, the Non-overlapping Domain of described first hard mask layer pattern 400a and the second hard mask layer pattern 700b forms multiple contact hole pattern, and the size of contact hole pattern is determined jointly by the distance D between adjacent first hard mask layer pattern 400a and the distance d between adjacent second hard mask layer pattern 700b.
Then, with reference to shown in Figure 26, to continue with the first hard mask layer pattern 400a and the second hard mask layer 700b, for mask, to etch the first resilient coating 300 to exposing dielectric layer 200, forming the first resilient coating pattern 300c.
Particularly, using plasma etching technics can be continued and etch the first resilient coating 300.Because the etching selection ratio of the first resilient coating 300 and the second hard mask layer pattern 700b or the first hard mask layer pattern 400a is very large, even if the thickness of the first resilient coating 300 is relatively thick, at etching first resilient coating 300 in the process exposing dielectric layer 200, the second hard mask layer pattern 700b and the first hard mask layer pattern 400a still can have residue.
Now, in conjunction with reference to shown in Figure 26 and 27, multiple contact hole patterns that the Non-overlapping Domain of the first hard mask layer pattern 400a and the second hard mask layer pattern 700b comprises are transferred in the first resilient coating 300, defined the first corresponding resilient coating pattern 300c.
Then, with reference to shown in Figure 28, described second hard mask layer pattern 700b, the second resilient coating pattern 600c and the first hard mask layer pattern 400a is removed successively to exposing the first resilient coating pattern 300c.
Particularly, dry etching or wet-etching technology can be adopted to realize, and it is known for those skilled in the art, does not repeat them here.
It should be noted that; in other embodiments of the invention; described second hard mask layer pattern 700b, part second resilient coating pattern 600c or part first hard mask layer pattern 400a just can be consumed in the process of etching first resilient coating 300, and it does not limit the scope of the invention.
Finally, with reference to shown in Figure 29, with described first resilient coating pattern 300c for mask, etching described dielectric layer 200 to exposing Semiconductor substrate 100, forming the dielectric layer pattern 200c comprising multiple contact hole, and removing the first resilient coating pattern 300c.
Because described first resilient coating 300 is smaller with the etching selection ratio of first medium layer 200, therefore while etching first medium layer 200, have part first resilient coating 300 to be also etched removal, it is known for those skilled in the art, does not repeat them here.
Particularly, the step removing described first resilient coating pattern 300c can comprise: in described contact hole, fill protective layer; Etching removes described second resilient coating pattern 300c; Remove described protective layer.
Wherein, the material of described protective layer can be bottom anti-reflection layer (BARC layer), and it does not limit the scope of the invention.
So far, the straight line of bidimensional is adopted to define multiple contact hole.The span of described contact hole depth-to-width ratio can be more than or equal to 1 and be less than or equal to 5.
It should be noted that, in other embodiments of the invention, the bidimensional line forming contact hole pattern in the first resilient coating 300 can also be other shapes, as curve, as long as the bidimensional line that can form contact hole pattern is all in protection scope of the present invention.
The contact hole adopting this implementation method to be formed can directly apply to and manufacture Flash (volatile holder) or PCM (PhaseChangedMemory, phase change memory) in, it is minimum can form the intensive contact hole of autoregistration that half spacing is 22nm, and this is that prior art institute is irrealizable.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a formation method for contact hole, is characterized in that, comprising:
Semiconductor substrate is provided;
Form dielectric layer and the first resilient coating successively on the semiconductor substrate;
Described first resilient coating is formed the first hard mask layer pattern of multiple line style;
Described first hard mask layer pattern and described first resilient coating form the second resilient coating, and the material of described first resilient coating is identical with the material of described second resilient coating, and the etching selection ratio of described first resilient coating and described dielectric layer is less than or equal to 2;
Described second resilient coating is formed the second hard mask layer pattern of multiple line style; Described second hard mask layer pattern and the underlapped region of described first hard mask layer pattern form multiple contact hole pattern, the material of described first hard mask layer pattern is identical with the material of described second hard mask layer pattern, and the etching selection ratio of described first resilient coating and described first hard mask layer pattern is more than or equal to 10;
With described second hard mask layer pattern and the first hard mask layer pattern for mask, etching described second resilient coating and the first resilient coating to exposing dielectric layer, forming the first resilient coating pattern;
Remove described second hard mask layer pattern, the second resilient coating and the first hard mask layer pattern;
With described first resilient coating pattern for mask, etching described dielectric layer to exposing Semiconductor substrate, forming the dielectric layer pattern comprising multiple contact hole;
Remove described first resilient coating pattern.
2. the formation method of contact hole as claimed in claim 1, it is characterized in that, the material of described dielectric layer comprises: silicon dioxide; The material of described first resilient coating comprises: polysilicon or silicon nitride.
3. the formation method of contact hole as claimed in claim 1, it is characterized in that, the material of described first resilient coating comprises: polysilicon or silicon nitride; The material of described first hard mask layer pattern comprises: silicon dioxide.
4. the formation method of contact hole as claimed in claim 1, it is characterized in that, the thickness range of described dielectric layer comprises:
extremely
5. the formation method of contact hole as claimed in claim 1, it is characterized in that, the thickness range of the first hard mask layer pattern comprises:
6. the formation method of contact hole as claimed in claim 1, is characterized in that, described first hard mask layer pattern adopts self-alignment type double exposure photolithographic process to be formed.
7. the formation method of contact hole as claimed in claim 1, is characterized in that, described second hard mask layer pattern adopts self-alignment type double exposure photolithographic process to be formed.
8. the formation method of contact hole as claimed in claim 1, it is characterized in that, the step removing described first resilient coating pattern comprises: in the dielectric layer pattern comprising multiple contact hole, fill protective layer; Etching removes described first resilient coating pattern; Remove described protective layer.
9. the formation method of contact hole as claimed in claim 1, is characterized in that, described first hard mask layer pattern is the straight line of longitudinally arrangement.
10. the formation method of contact hole as claimed in claim 1, is characterized in that, described second hard mask layer pattern is the straight line of laterally arrangement.
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| CN104124149B (en) * | 2013-04-28 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor device |
| CN103985629B (en) * | 2014-05-21 | 2017-07-11 | 上海华力微电子有限公司 | The preparation method of autoregistration bilayer figure semiconductor structure |
| CN105336667B (en) * | 2014-06-20 | 2018-10-23 | 中芯国际集成电路制造(北京)有限公司 | A kind of manufacturing method of semiconductor devices |
| US11120992B2 (en) * | 2019-11-11 | 2021-09-14 | Xia Tai Xin Semiconductor (Qing Dao) Ltd. | Method of fabricating semiconductor device |
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| CN101958245A (en) * | 2009-07-16 | 2011-01-26 | 中芯国际集成电路制造(上海)有限公司 | Etching method |
| US8012881B1 (en) * | 2010-05-31 | 2011-09-06 | Hynix Semiconductor Inc. | Method for forming contact holes in semiconductor device |
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