CN112447513A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN112447513A CN112447513A CN201910816171.4A CN201910816171A CN112447513A CN 112447513 A CN112447513 A CN 112447513A CN 201910816171 A CN201910816171 A CN 201910816171A CN 112447513 A CN112447513 A CN 112447513A
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
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Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate; forming a plurality of discrete first sidewall layers on a substrate; performing one or more graphic element forming processes on the first sidewall layer, the graphic element forming processes comprising: forming a sacrificial layer on a sidewall of the first sidewall layer; forming a second side wall layer on the side wall of the sacrificial layer; after the graphic unit forming process is finished, removing the sacrificial layer; and after the sacrificial layer is removed, the substrate is etched by taking the first side wall layer and the second side wall layer as masks, and a plurality of discrete fin parts are formed. In the embodiment of the invention, the sacrificial layer and the second side wall layer are formed on the side wall of the first side wall layer in the direction parallel to the surface of the substrate, the sacrificial layer is used for realizing the isolation of the first side wall layer and the second side wall layer, the problem of pattern transmission error in the process of forming the substrate mask by adopting a plurality of core layers to downwards transmit patterns is avoided, the formation precision of the substrate mask is favorably improved, and the electrical performance of the semiconductor structure is optimized.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
Photolithography (photolithography) is a commonly used patterning method, and is the most critical production technique in semiconductor manufacturing processes. With the continuous reduction of semiconductor process nodes, a self-aligned double patterning (SADP) method is becoming a favored patterning method in recent years, which can increase the density of patterns formed on a substrate and further reduce the pitch (pitch) between two adjacent patterns, so that the photolithography process overcomes the limit of the photolithography resolution.
As the feature size (CD) of the pattern is continuously reduced, a self-aligned quad patterning (SAQP) method is developed. The density of the patterns formed on the substrate by the self-aligned double patterning method is twice that of the patterns formed on the substrate by the photoetching process, so that 1/2 minimum spacing (1/2pitch) can be obtained, and the density of the patterns formed on the substrate by the self-aligned quadruple patterning method is four times that of the patterns formed on the substrate by the photoetching process on the premise of not changing the current photoetching technology (i.e. the size of a photoetching window is not changed), so that 1/4 minimum spacing (1/4pitch) can be obtained, so that the density of a semiconductor integrated circuit can be greatly improved, the characteristic size of the patterns is reduced, and the improvement of device performance is facilitated.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize electrical properties of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of discrete first sidewall layers on the substrate; performing one or more graphic element forming processes on the first sidewall layer, wherein the graphic element forming processes comprise the following steps: forming a sacrificial layer on the side wall of the first side wall layer; forming a second side wall layer on the side wall of the sacrificial layer; after the graphic unit forming process is completed, removing the sacrificial layer; and after removing the sacrificial layer, etching the substrate by taking the first side wall layer and the second side wall layer as masks to form a plurality of discrete fin parts.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises a substrate; a plurality of discrete first sidewall layers on the substrate; the sacrificial unit is positioned on the side wall of the first side wall layer, and the sacrificial unit positioned on any side wall of the same first side wall layer comprises a sacrificial layer or a plurality of sacrificial layers which are arranged in parallel; and the second side wall layer is positioned on the side wall of the sacrificial layer, and when the sacrificial unit positioned on any side wall of the first side wall layer comprises a plurality of sacrificial layers which are arranged in parallel, the second side wall layer is filled between two adjacent sacrificial layers on the same side wall of the first side wall layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the present invention, a plurality of discrete first sidewall layers are formed on the substrate, and one or more graphic unit forming processes are performed on the first sidewall layers, where the graphic unit forming process includes: forming a sacrificial layer on the side wall of the first side wall layer; forming a second side wall layer on the side wall of the sacrificial layer; and after the graphic unit forming process is finished, removing the sacrificial layer, and etching the substrate by using the first side wall layer and the second side wall layer as masks to form a plurality of discrete fin parts. Compared with the scheme of performing multiple patterning processing by adopting a plurality of core layers, in the embodiment of the invention, the first side wall layer is used as a base, the sacrificial layer and the second side wall layer are formed on the side wall of the first side wall layer in the direction parallel to the surface of the substrate, and the sacrificial layer is used for realizing the isolation of the first side wall layer and the second side wall layer, so that the problem of pattern transfer errors in the process of transferring patterns downwards by adopting the plurality of core layers to form the substrate mask is avoided, the formation precision of the substrate mask is improved, the formation precision of the fin part is improved, and the electrical performance of the semiconductor structure is further optimized.
Drawings
Fig. 1 to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 6 to 11 are schematic structural views corresponding to steps in a first embodiment of a method for forming a semiconductor structure according to the present invention;
fig. 12 and 14 are schematic structural views corresponding to respective steps in a second embodiment of a method of forming a semiconductor structure of the present invention;
fig. 15 and 17 are schematic structural views corresponding to respective steps in a third embodiment of a method of forming a semiconductor structure of the present invention;
fig. 18 and 20 are schematic structural views corresponding to respective steps in a fourth embodiment of the method for forming a semiconductor structure of the present invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1 to 5, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
As shown in fig. 1, a base is provided, the base comprising a substrate 1, a bottom layer of core material 2 on the substrate 1, and a top layer of core material 10 on the bottom layer of core material 2; a layer of photoresist material 11 is formed on the top layer of core material 10.
As shown in fig. 2, the photoresist material layer 11 is exposed to form a photoresist layer 12; the top core material layer 10 is etched using the photoresist layer 12 as a mask to form the top core layer 3.
As shown in fig. 3, a sidewall material layer (not shown) is formed on the top core layer 3 and the exposed bottom core material layer 2 of the top core layer 3; and removing the side wall material layers on the top of the top core layer 3 and the bottom core material layer 2, and taking the residual side wall material layers on the side wall of the top core layer 3 as a first side wall layer 4.
As shown in fig. 4, after the first sidewall layer 4 is formed, the top core layer 3 is removed (as shown in fig. 2); after removing the top core layer 3, etching the bottom core material layer 2 by using the first side wall layer 4 as a mask to form a bottom core layer 6; and conformally covering a side wall material layer (not shown in the figure) on the bottom core layer 6 and the substrate 1 exposed from the bottom core layer 6, removing the side wall material layer on the bottom core layer 6 and the substrate 1, and taking the residual side wall material layer on the side wall of the bottom core layer 6 as a second side wall layer 7.
As shown in fig. 5, the bottom core layer 6 is removed; the substrate 1 is etched by using the second sidewall layer 7 (as shown in fig. 4) as a mask, and a residual substrate 8 and a fin portion 9 on the residual substrate 8 are formed.
The bottom core material layer 2 is usually formed by a Chemical Vapor Deposition (CVD) process and a Chemical Mechanical Polishing (CMP) process, when a bump (bump) defect a is formed in the substrate 1, during the formation of the bottom core material layer 2, a larger bump defect B is formed in the bottom core material layer 2 at a position corresponding to the bump defect a, and similarly, a bump defect C corresponding to the bump defect B is formed in the top core material layer 10, and a bump defect D corresponding to the bump defect C is formed in the photoresist material layer 11. In the process of exposing the photoresist material layer 11 to form the photoresist layer 12, since the position of the bump defect D is high, it is difficult to align the photoresist layer 11 at the position corresponding to the bump defect D, which may result in a small width of the photoresist layer 12 at the position corresponding to the bump defect D, and accordingly, after etching the top core material layer 10 to form the top core layer 3, the width of the top core layer 3 at the position corresponding to the bump defect C is small, which may result in a small interval of the first sidewall layers 4 on the sidewalls of the top core layer 3 at the position corresponding to the bump defect C, which may result in a small interval of the bottom core layers 6 at the position corresponding to the bump defect B, and the second sidewall layers 7 formed on the sidewalls of the bottom core layers 6, which may be easily contacted, therefore, after the substrate 1 is etched by using the second sidewall layer 7 as a mask, the formed fin portion 9 is easily bridged (as shown in E) at the position corresponding to the bump defect a, and the electrical performance of the semiconductor structure is poor.
In order to solve the technical problem, in the embodiment of the present invention, compared with a scheme of performing multiple patterning processing by using a plurality of core layers, in the embodiment of the present invention, a first sidewall layer is used as a base, and a sacrificial layer and a second sidewall layer are formed on a sidewall of the first sidewall layer in a direction parallel to a substrate surface, and the sacrificial layer is used for realizing isolation between the first sidewall layer and the second sidewall layer, so that a problem of a pattern transfer error occurring in a process of transferring a pattern downwards by using the plurality of core layers to form a substrate mask is avoided, which is beneficial to improving the formation precision of the substrate mask, thereby improving the formation precision of a fin portion, and further optimizing the electrical performance of a semiconductor structure.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 6 to 11 are schematic structural views corresponding to steps in the first embodiment of the method for forming a semiconductor structure of the present invention.
Referring to fig. 6, a substrate 100 is provided.
In the present embodiment, the formed semiconductor structure is a fin field effect transistor (FinFET), and the base 100 is used to form a substrate and a fin portion on the substrate.
In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
Referring to fig. 7, a plurality of discrete first sidewall layers 104 are formed on a substrate 100.
The first sidewall layer 104 provides for the subsequent formation of a second sidewall layer, and the first sidewall layer 104 is used as a substrate mask for etching the substrate 100 in a subsequent process.
In the process of etching the substrate 100 by using the first sidewall layer 104 as a mask, the difficulty of etching the first sidewall layer 104 is greater than that of etching the substrate 100.
Specifically, the material of the first sidewall layer 104 includes one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride boron, and boron nitride silicon carbide. In this embodiment, the material of the first sidewall layer 104 is silicon nitride. .
In this embodiment, the first sidewall layer 104 is formed by a self-aligned double patterning process.
A sacrificial layer and a second side wall layer are formed on the side wall of the first side wall layer 104 in a direction parallel to the surface of the substrate subsequently, only one core layer needs to be formed by adopting a mode of forming the first side wall layer 104 through a self-aligned double patterning process, the problem of pattern transmission errors in the process of downwards transmitting patterns by adopting multiple core layers is solved, the formation precision of the first side wall layer 104 and the subsequent second side wall layer is favorably improved, the formation precision of the fin portion is improved, and the electrical performance of the semiconductor structure is optimized.
Therefore, with continued reference to fig. 6, before forming the first sidewall layer 104, further comprising: a core layer 101 is formed on a substrate 100.
The core layer 101 provides for the subsequent formation of a first sidewall layer overlying the sidewalls of the core layer 101.
Specifically, the material of the core layer 101 includes one or more of silicon oxide, SiON, SiOC, Si, SiN, amorphous silicon, and metal oxide. In this embodiment, the material of the core layer 101 is Si.
The formation process of the core layer 101 includes: forming a core material layer (not shown) on the substrate 100; the core material layer is etched to form the core layer 101.
The method for forming a semiconductor structure includes: after providing the substrate 100, a layer of masking material 102 is formed on the substrate 100 before forming the core layer 101.
The masking material layer 102 forms a masking layer for etching the substrate 100 in a subsequent process.
In this embodiment, the masking material layer 102 includes a bottom masking material layer 1021 and a top masking material layer 1022 disposed on the bottom masking material layer 1021.
Note that, the core material layer is formed on the mask material layer 102; in the process of etching the core material layer to form the core layer 101, the top mask material layer 1022 serves as an etch stop layer, and thus, the etching rate of the core material layer is greater than that of the top mask material layer 1022.
In the subsequent process of etching the top mask material layer 1022 to form the top mask layer, the bottom mask material layer 1021 serves as an etching stop layer; the bottom mask material layer 1021 is etched at a rate that is less than the rate at which the top mask material layer 1022 is etched.
It should be noted that after the substrate 100 is provided and before the mask material layer 102 is formed, the method further includes: a buffer material layer 103 is formed on the substrate 100.
In this embodiment, the material of the buffer material layer 103 is silicon oxide.
Accordingly, referring to fig. 7, the step of forming the first sidewall layer 104 includes: forming a side wall material layer (not shown) on the core layer 101 (shown in fig. 6) and the substrate 100 exposed from the core layer 101; and etching the top of the core layer 101 and the side wall material layer on the substrate 100 by using an anisotropic etching process, wherein the remaining side wall material layer on the side wall of the core layer 101 is used as a first side wall layer 104.
In this embodiment, an Atomic Layer Deposition (ALD) process is used to form the sidewall material layer. The atomic layer deposition process comprises multiple atomic layer deposition cycles to form a side wall material layer with required thickness. The atomic layer deposition process is selected, so that the thickness uniformity of the side wall material layer is improved, and the thickness of the side wall material layer can be accurately controlled; in addition, the gap filling performance and the step coverage performance of the atomic layer deposition process are good, and the conformal coverage capability of the side wall material layer is correspondingly improved. In other embodiments, the sidewall material layer may also be formed by a chemical vapor deposition process.
In this embodiment, the anisotropic etching process is a dry etching process. The dry etching process has better etching profile controllability, and the side wall material layer on the side wall of the core layer 101 is retained while the side wall material layer on the top of the core layer 101 and the substrate 100 are removed, thereby being beneficial to forming the first side wall layer 104. In addition, the dry etching process can use the top mask material layer 1022 as an etching stop position, and can reduce damage to other film structures.
The method of forming the semiconductor structure further includes removing the core layer 101 after forming the first sidewall layer 104.
It should be noted that, in other embodiments, the first sidewall layer may also be formed by a dry etching process, a self-aligned quadruple patterning process, or a self-aligned multiple patterning process.
Referring to fig. 8 and 9, the first sidewall layer 104 is subjected to one or more patterning process, which includes the steps of: forming a sacrificial layer 105 on sidewalls of the first sidewall layer 104 (as shown in fig. 8); a second sidewall layer 106 is formed on the sidewalls of the sacrificial layer 105 (as shown in fig. 9).
The first sidewall layer 104 and the second sidewall layer 106 serve as a substrate mask for subsequent etching of the substrate 100.
After the graphic unit forming process is completed, the subsequent process further comprises the following steps: the sacrificial layer 105 is removed, and the substrate 100 is etched using the first sidewall layer 104 and the second sidewall layer 106 as masks, thereby forming a plurality of discrete fin portions. Compared with the scheme of performing multiple patterning processing by using a plurality of core layers, in the embodiment of the invention, the first side wall layer 104 is used as a base, the sacrificial layer 105 and the second side wall layer 106 are formed on the side wall of the first side wall layer 104 in the direction parallel to the surface of the substrate 100, and the sacrificial layer 105 is used for realizing the isolation between the first side wall layer 104 and the second side wall layer 106, so that the problem of pattern transmission errors in the process of forming the substrate mask by adopting the plurality of core layers to transmit patterns downwards is avoided, the formation precision of the substrate mask is improved, the precision of a subsequently formed fin part is improved, and the electrical performance of a semiconductor structure is optimized.
In this embodiment, after the process of forming the graphic elements is completed, the first sidewall layer 104, and the sacrificial layer 105 and the second sidewall layer 106 on the same sidewall of the first sidewall layer 104 form the graphic elements, and the graphic elements are spaced from each other.
In this embodiment, the second sidewall layer 106 is used as a substrate mask for etching the substrate 100 in a subsequent process.
In the process of etching the substrate 100 by using the second sidewall layer 106 as a mask, the difficulty of etching the second sidewall layer 106 is greater than that of etching the substrate 100.
Specifically, the material of the second sidewall layer 106 includes one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride boron, and boron nitride silicon carbide. In this embodiment, the material of the second sidewall layer 106 includes silicon nitride.
The material of the sacrificial layer 105 is easily removed, and during the process of removing the sacrificial layer 105, the etching rate of the sacrificial layer 105 is greater than that of the first sidewall layer 104 and the second sidewall layer 106. In this embodiment, the material of the sacrificial layer 105 includes amorphous carbon.
Specifically, taking the number of times of the graphic unit forming process as an example, the steps of the graphic unit forming process include:
as shown in fig. 8, the step of forming the sacrificial layer 105 includes: conformally covering a sacrificial material layer (not shown) on the first sidewall layer 104 and the substrate 100 exposed by the first sidewall layer 104; and etching the sacrificial material layer by adopting an anisotropic etching process to expose the top of the first sidewall layer 104, wherein the residual sacrificial material layer on the sidewall of the first sidewall layer 104 is used as a sacrificial layer 105.
In this embodiment, the sacrificial material layer is formed by an atomic layer deposition process. The atomic layer deposition process includes performing multiple atomic layer deposition cycles to form a layer of sacrificial material of a desired thickness. The thickness uniformity of the sacrificial material layer is improved by selecting the atomic layer deposition process, so that the thickness of the sacrificial material layer can be accurately controlled; in addition, the gap filling performance and the step coverage performance of the atomic layer deposition process are good, and the conformal coverage capability of the sacrificial material layer is correspondingly improved. In other embodiments, the sacrificial material layer may be formed by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process with good step coverage and high gap filling performance, that is, the formation process of the sacrificial material layer includes, but is not limited to, an atomic layer Deposition process and a Plasma Enhanced Chemical Vapor Deposition process.
It should be noted that, in the step of etching the sacrificial material layer by using the anisotropic etching process to expose the top of the first sidewall layer 104, the sacrificial material layer on the mask material layer 102 is also removed.
In this embodiment, the anisotropic etching process is a dry etching process. The dry etching process has a better etching profile controllability, and the sacrificial material layer on the sidewall of the first sidewall layer 104 is retained while the sacrificial material layer on the top of the first sidewall layer 104 and the top mask material layer 1022 is removed, which is beneficial to forming the sacrificial layer 105. In addition, the dry etching process can use the top mask material layer 1022 as an etching stop position, and can reduce damage to other film structures.
As shown in fig. 9, the step of forming the second sidewall layer 106 includes: forming a side wall material layer on the first side wall layer 104, the sacrificial layer 105 and the substrate 100 exposed by the first side wall layer 104 and the sacrificial layer 105; and etching the side wall material layer by adopting an anisotropic etching process to expose the tops of the first side wall layer 104 and the sacrificial layer 105, wherein the residual side wall material layer on the side wall of the sacrificial layer 105 is used as a second side wall layer 106.
In this embodiment, the sidewall material layer is formed by using an atomic layer deposition process. The atomic layer deposition process comprises multiple atomic layer deposition cycles to form a side wall material layer with required thickness. The atomic layer deposition process is selected, so that the thickness uniformity of the side wall material layer is improved, and the thickness of the side wall material layer can be accurately controlled; in addition, the gap filling performance and the step coverage performance of the atomic layer deposition process are good, and the conformal coverage capability of the side wall material layer is correspondingly improved. In other embodiments, the sidewall material layer may also be formed by a chemical vapor deposition process.
It should be noted that, in the step of etching the sidewall material layer by using the anisotropic etching process to expose the top of the first sidewall layer 104, the sidewall material layer on the mask material layer 102 is also removed.
In this embodiment, the anisotropic etching process is a dry etching process. The dry etching process has a better etching profile controllability, and the sidewall material layer on the sidewall of the first sidewall layer 104 is retained while the sidewall material layers on the top of the first sidewall layer 104 and the sacrificial layer 105 and on the top mask material layer 1022 are removed, which is beneficial to forming the second sidewall layer 106. In addition, the dry etching process can use the top mask material layer 1022 as an etching stop position, and can reduce damage to other film structures.
Note that the second sidewall layer 106 is formed on the sidewall of the sacrificial layer 105 away from the first sidewall layer 104.
Referring to fig. 10, after the patterning unit forming process is completed, the sacrificial layer 105 is removed (as shown in fig. 9).
The sacrificial layer 105 is removed in preparation for subsequent etching of the substrate 100 with the first sidewall layer 104 and the second sidewall layer 106 as a substrate mask.
In this embodiment, the sacrificial layer 105 is amorphous carbon, and an ashing process is correspondingly used to remove the sacrificial layer 105. The ashing process is a common process in the art and is not described in detail herein.
Referring to fig. 11, after removing the sacrificial layer 105, the substrate 100 is etched using the first sidewall layer 104 and the second sidewall layer 106 as masks, so as to form a plurality of discrete fins 107.
The fin 107 provides for the subsequent formation of semiconductor structures.
In this embodiment, the substrate 100 is etched by a dry etching process using the first sidewall layer 104 and the second sidewall layer 106 as masks, so as to form a plurality of discrete fin portions 107. The dry etching process is an anisotropic etching process, has good etching profile controllability, is beneficial to enabling the appearance of the fin portion 107 to meet the process requirement, and is also beneficial to improving the etching efficiency of the substrate 100. And the substrate 100 is etched by adopting a dry etching process, so that the etching thickness of the substrate 100 can be accurately controlled, and the damage to other film layer structures can be reduced. And in the dry etching process, each film layer can be etched in the same etching equipment by replacing etching gas, so that the process steps are simplified.
The method for forming the semiconductor structure further comprises the following steps: before the substrate 100 is etched by using the first sidewall layer 104 and the second sidewall layer 106 as masks to form a plurality of discrete fins 107, the mask material layer 102 and the buffer material layer 103 are etched to form a mask layer 108 and a buffer layer 109.
Specifically, mask layer 108 includes: a top mask layer 1082 formed by etching the top mask material layer 1022 and a bottom mask layer 1081 formed by etching the bottom mask material layer 1021.
The mask layer 108, together with the first sidewall layer 104 and the second sidewall layer 106, serves as a substrate mask for etching the substrate 100.
In this embodiment, after the fin 107 is formed by etching, the first sidewall layer 104 and the second sidewall layer 106 are not completely consumed. In other embodiments, after the fin portion is formed, the first sidewall layer and the second sidewall layer may be consumed and removed.
It should be noted that, with the extending direction perpendicular to the core layer 101 as the lateral direction, in the formation process of the semiconductor structure, the fin portions 107 with equal spacing or unequal spacing may be selectively obtained by adjusting the spacing between the first sidewall layers 104 according to the process requirements.
It should be noted that, in the present embodiment, the number of times of the graphic unit forming process is taken as an example. In other embodiments, the number of the patterning process may be multiple, for example, two, according to the process requirement.
Fig. 12 to 14 are schematic structural diagrams corresponding to steps in a second embodiment of a method for forming a semiconductor structure according to the present invention.
The same parts of this embodiment as those of the first embodiment are not described herein again, and the differences between this embodiment and the first embodiment are: after the patterning process is completed, the first sidewall layer 304 and the sacrificial layer 305 and the second sidewall layer 306 on the same sidewall of the first sidewall layer 304 form a patterning unit, and the patterning units are in contact with each other.
In the present embodiment, the mutual contact means: in the adjacent pattern units, the second sidewall layers 306 formed in the last pattern unit forming process are in contact with each other.
In the embodiment of the present invention, the extending direction perpendicular to the first sidewall layer 304 is taken as a transverse direction, the graphic units are contacted with each other, so that the transverse dimension of the second sidewall layer 306 at the boundary of the graphic units is greater than the transverse dimensions of the other second sidewall layers 306, that is, the second sidewall layer 306 has two transverse dimensions, after the sacrificial layer 305 is removed, the substrate 300 is etched by taking the first sidewall layer 304 and the second sidewall layer 306 as masks, and the formed fin portion has various transverse dimensions, which is beneficial to meeting the diversified requirements of the semiconductor structure, and is further beneficial to improving the electrical performance of the semiconductor structure.
In this embodiment, the fin portions formed subsequently have various lateral dimensions, which is beneficial to providing a process foundation for forming various Static Random-Access memories (SRAMs).
It should be noted that by adjusting the spacing between the first sidewall layers 304, fins with equal or unequal spacing can be selectively obtained.
In this embodiment, the number of times of the pattern unit forming process is described as two.
For a detailed description of the first process of forming the graphic unit, reference may be made to the corresponding description in the foregoing embodiments, which is not repeated herein.
Specifically, the second patterning process includes:
as shown in fig. 12, after the first patterning process is completed, a sacrificial layer 305 is formed on the sidewalls of the second sidewall layer 306 formed by the first patterning process.
In this embodiment, the process of forming the sacrificial layer 305 is the same as that of the previous embodiment, and is not repeated herein.
As shown in fig. 13 and 14, a second sidewall layer 306 is formed on the sidewall of the sacrificial layer 305.
The step of forming the second sidewall layer 306 includes: forming a spacer material layer 307 (shown in fig. 13) on the first spacer layer 304, the sacrificial layer 305, and the substrate 300 where the first spacer layer 304 and the sacrificial layer 305 are exposed; and etching the side wall material layer 307 by using an anisotropic etching process to expose the tops of the first side wall layer 304 and the sacrificial layer 305, wherein the remaining side wall material layer 307 on the side wall of the sacrificial layer 305 is used as a second side wall layer 306.
In this embodiment, the direction perpendicular to the extending direction of the first sidewall layer 304 is a horizontal direction, and in the process of performing the second patterning process, after the sacrificial layers 305 are formed, the interval between the sacrificial layers 305 is the first size, the thickness of the sidewall material layer 307 is the second size, and twice of the second size is larger than the first size, so that in the process of forming the sidewall material layer 307, along with the continuous deposition of the material of the sidewall material layer 307, the interval between the sidewall material layers 307 on the sidewalls of adjacent sacrificial layers 305 is gradually reduced until the sidewalls are finally in contact with each other.
In this embodiment, the sidewall material layer 307 formed by the second patterning process is further formed on the second sidewall layer 306 formed by the first patterning process.
For the specific description of the forming method of this embodiment, reference may be made to the corresponding description of the first embodiment, which is not repeated herein.
Fig. 15 to 17 are schematic structural diagrams corresponding to steps in a third embodiment of a method for forming a semiconductor structure according to the present invention.
The same parts of this embodiment as those of the first embodiment are not described herein again, and the forming process of this embodiment is different from that of the first embodiment as follows:
referring to fig. 15, a plurality of discrete first sidewall layers 404 are formed on a substrate 400.
In this embodiment, the plurality of first sidewall layers 404 arranged in parallel form a sidewall group 410, in the same sidewall group 410, the interval between adjacent first sidewall layers 404 is a first interval d1, the interval between adjacent sidewall groups 410 is a second interval d2, and the first interval d1 is smaller than the second interval d 2.
Referring to fig. 16 and 17, a pattern unit forming process is performed on the first sidewall layer 404 once, and the pattern unit forming process includes: a sacrificial layer 405 is formed on sidewalls of the first sidewall layer 404, and a second sidewall layer 406 is formed on sidewalls of the sacrificial layer 405.
In this embodiment, in the step of forming the sacrificial layer 405 on the sidewall of the first sidewall layer 404, in the same sidewall group 410, the region between the adjacent first sidewall layers 404 is filled with the sacrificial layer 405.
As shown in fig. 16, the step of forming the sacrificial layer 405 includes: conformally covering a sacrificial material layer (not shown) on the first sidewall layer 404 and the substrate 400 exposed by the first sidewall layer 404, wherein the sacrificial material layers on the sidewalls of adjacent first sidewall layers 404 in the same sidewall group 410 are in contact with each other; the sacrificial material layer is etched by using an anisotropic etching process to expose the top of the first sidewall layer 404, and the remaining sacrificial material layer on the sidewall of the first sidewall layer 404 is used as a sacrificial layer 405.
In the same sidewall group 410, the region between the adjacent first sidewall layers 404 is filled with the sacrificial material layer, and the thickness of the sacrificial material layer at the position is larger, so that after the sacrificial material layer is etched by using the anisotropic etching process, the sacrificial material layer between the adjacent first sidewall layers 404 remains, so that the region between the adjacent first sidewall layers 404 is filled with the sacrificial layer 405.
Accordingly, as shown in fig. 17, in the step of forming the second sidewall layer 406 on the sidewall of the sacrificial layer 405, the second sidewall layer 406 is formed on the sidewall of the outermost sacrificial layer 405 in the sidewall group 410.
After the graphic element forming process is completed, the same sidewall group 410, the first sidewall layer 404, and the sacrificial layer 405 and the second sidewall layer 406 on the sidewall of the first sidewall layer 410 form graphic elements, and the graphic elements are spaced from each other.
In the embodiment of the invention, a direction perpendicular to the extending direction of the first sidewall layers 404 is taken as a transverse direction, the interval between the first sidewall layers 404 is a first interval d1, the interval between the adjacent sidewall groups 410 is a second interval d2, and the first interval d1 is smaller than the second interval d2, after the sacrificial layer 405 is removed, the substrate 400 is etched by taking the first sidewall layers 404 and the second sidewall layers 406 as masks, so that the formed fin has various transverse dimensions, which is favorable for meeting the diversified requirements of a semiconductor structure and improving the electrical performance of the semiconductor structure.
It should be noted that, by adjusting the spacing between the first sidewall layers 404, fins with equal spacing or unequal spacing can be selectively obtained according to the process requirements.
For example, the formation method can be applied to form a Dual Port static random access memory (Dual Port SRAM).
For the specific description of the forming method of this embodiment, reference may be made to the corresponding description of the first embodiment, which is not repeated herein.
Fig. 18 to 20 are schematic structural views corresponding to steps in a fourth embodiment of the method for forming a semiconductor structure of the present invention.
The same parts of this embodiment and the third embodiment are not described herein again, and the differences between this embodiment and the third embodiment are: in the step of forming the sacrificial layer on the sidewalls of the first sidewall layers, the regions between adjacent first sidewall layers are filled with the sacrificial layer.
Referring to fig. 18, a plurality of discrete first sidewall layers 504 are formed on a substrate 500.
In this embodiment, the plurality of first sidewall layers 504 arranged in parallel form a sidewall group 510, in the same sidewall group 510, the interval between adjacent first sidewall layers 504 is a first interval D1, the interval between adjacent sidewall groups 510 is a second interval D2, and the first interval D1 is smaller than the second interval D2.
Referring to fig. 19 and 20, a patterning process is performed on the first sidewalls 504, where the patterning process includes: forming a sacrificial layer 505 on sidewalls of the first sidewall layer 504; a second sidewall layer 506 is formed on the sidewalls of sacrificial layer 505 (as shown in fig. 20).
As shown in fig. 19, in the step of forming the sacrificial layer 505 on the sidewalls of the first sidewall layers 504, the region between adjacent first sidewall layers 504 is filled with the sacrificial layer 505, and the sidewall groups 510 and the sacrificial layer 505 are used as a pattern set.
The step of forming the sacrificial layer 505 includes: conformally covering a sacrificial material layer (not shown) on the first sidewall layer 504 and the substrate 500 exposed by the first sidewall layer 504, wherein the sacrificial material layers on different sidewalls of the first sidewall layer 504 in the same sidewall group 510 are in contact with each other; the sacrificial material layer is etched by using an anisotropic etching process to expose the top of the first sidewall layer 504, and the remaining sacrificial material layer on the sidewall of the first sidewall layer 504 is used as a sacrificial layer 505.
In the step of forming the sacrificial layer 505 on the sidewall of the first sidewall layer 504 with the direction perpendicular to the extending direction of the first sidewall layer 504 being the lateral direction, the lateral dimension of the sacrificial layer 505 is greater than the first interval D1 and less than the second interval D2, and twice the lateral dimension of the sacrificial layer 505 is greater than the second interval D2.
Accordingly, as shown in fig. 20, in the step of forming the second sidewall layer 506 on the sidewall of the sacrificial layer 505, the second sidewall layer 506 is formed on the sidewall of the pattern set.
In this embodiment, the extending direction perpendicular to the first sidewall layer 504 is taken as a transverse direction, in the same sidewall group 510, the interval between the adjacent first sidewall layers 504 is a first interval D1, the interval between the adjacent sidewall groups 510 is a second interval D2, the first interval D1 is smaller than the second interval D2, after the sacrificial layer 505 is removed, the substrate 500 is etched by using the first sidewall layer 504 and the second sidewall layer 506 as masks, and the interval sizes between the formed fins are at least three, which is favorable for meeting the diversified requirements of the semiconductor structure and improving the electrical performance of the semiconductor structure.
For a specific description of the forming method of this embodiment, reference may be made to corresponding descriptions of the first embodiment and the third embodiment, which are not repeated herein.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 9, a schematic structural diagram of a first embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100; a plurality of discrete first sidewall layers 104 on the substrate 100; the sacrificial unit is positioned on the side wall of the first side wall layer 104, and the sacrificial unit positioned on any side wall of the same first side wall layer 104 comprises a sacrificial layer 105 or a plurality of sacrificial layers 105 which are arranged in parallel; the second sidewall layer 106 is disposed on the sidewalls of the sacrificial layers 105, and when the sacrificial unit disposed on any sidewall of the same first sidewall layer 104 includes a plurality of sacrificial layers 105 arranged in parallel, the second sidewall layer 106 is filled between two adjacent sacrificial layers 105 on the same sidewall of the first sidewall layer 104.
In an embodiment of the present invention, the forming step of the semiconductor structure includes: forming a plurality of discrete first sidewall layers 104 on the substrate 100, and performing a pattern unit forming process on the first sidewall layers 104, wherein the pattern unit forming process includes: forming a plurality of discrete first sidewall layers 104 on the substrate 100; forming sacrificial layers 105 on sidewalls of the first sidewall layer 104, the number of the sacrificial layers 105 being one or more; a second sidewall layer 106 is formed on the sidewall of the sacrificial layer 105. Compared with the case of forming the mask for etching the substrate 100 by adopting a scheme of performing multiple patterning processing on a plurality of core layers, in the semiconductor structure of the embodiment of the invention, the first sidewall layer 104, the sacrificial layer 105 and the second sidewall layer 106 are positioned in the same horizontal plane, the sacrificial layer 105 is used for spacing the first sidewall layer 104 and the second sidewall layer 106 or the first sidewall layer 104 and the second sidewall layer 106, and the mask for etching the substrate 100 can be obtained by removing the sacrificial layer 105 subsequently.
In this embodiment, the first sidewall layer 104, and the sacrificial layer 105 and the second sidewall layer 106 on the same sidewall of the first sidewall layer 104 constitute a pattern unit, and the pattern units are spaced apart from each other.
It should be noted that, in this embodiment, the sacrificial unit includes a sacrificial layer 105, and the second sidewall layer 106 and the first sidewall layer 104 are respectively located on two sidewalls of the sacrificial layer 105. In other embodiments, the sacrificial unit includes a plurality of sacrificial layers arranged in parallel, and the second sidewall layer is further formed on a sidewall of the outermost sacrificial layer, which is far away from the first sidewall layer.
In the present embodiment, the formed semiconductor structure is a fin field effect transistor (FinFET), and the base 100 is used to form a substrate and a fin portion on the substrate.
In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the first sidewall layer 104 and the second sidewall layer 106 are used as a substrate mask for etching the substrate 100 in a subsequent process.
In this embodiment, the material of the first sidewall layer 104 includes one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride boron, and boron nitride silicon carbide. In this embodiment, the first sidewall layer 104 is made of silicon nitride.
In this embodiment, the material of the second sidewall layer 106 includes one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride boron, and boron nitride silicon carbide. In this embodiment, the material of the second sidewall layer 106 is silicon nitride.
It should be noted that, in the subsequent process of removing the sacrificial layer 105, the etching rate of the first sidewall layer 104 and the second sidewall layer 106 is smaller than the etching rate of the sacrificial layer 105.
In this embodiment, the material of the sacrificial layer 105 includes amorphous carbon.
In addition, the semiconductor structure further includes: a layer of masking material 102 is disposed between the substrate 100 and the first sidewall layer 104.
The mask material layer 102 forms a mask layer for etching the substrate 100 in a subsequent process, and the mask layer, the first sidewall layer 104 and the second sidewall layer 106 together serve as a substrate mask for etching the substrate 100.
In this embodiment, the masking material layer 102 includes a bottom masking material layer 1021 and a top masking material layer 1022 disposed on the bottom masking material layer 1021.
The bottom mask material layer 1021 is etched at a rate that is less than the rate at which the top mask material layer 1022 is etched. The bottom mask material layer 1021 acts as an etch stop during subsequent formation of the top mask layer.
In addition, the semiconductor structure further includes: a buffer material layer 103 is disposed between the substrate 100 and the mask material layer 102.
In this embodiment, the material of the buffer material layer 103 is silicon oxide.
In this embodiment, after the sacrificial layer 105 is subsequently removed, the fin portions 107 with equal intervals may be obtained. In other embodiments, after removing the sacrificial layer, fins with unequal intervals may also be obtained.
Referring to fig. 14, a schematic structural diagram of a second embodiment of the semiconductor structure of the present invention is shown.
The same parts of this embodiment as those of the first embodiment are not described herein again, and the differences between this embodiment and the first embodiment are: in this embodiment, the sacrificial unit includes a plurality of sacrificial layers 305 arranged in parallel, and a second sidewall layer 306 is further formed on a sidewall of the outermost sacrificial layer 305 away from the first sidewall layer 304.
The first sidewall layer 304 and the sacrificial layer 305 and the second sidewall layer 306 on the same sidewall of the first sidewall layer 304 constitute graphic units, and the graphic units are in contact with each other.
In the embodiment of the invention, the direction perpendicular to the extending direction of the first sidewall layer 304 is taken as a transverse direction, the graphic units are contacted with each other, so that the transverse dimension of the second sidewall layer 306 at the boundary of the graphic units is larger than that of the other second sidewall layers 306, that is, the second sidewall layer 306 has two transverse dimensions, after the sacrificial layer 305 is subsequently removed, the substrate 300 is etched by taking the first sidewall layer 304 and the second sidewall layer 306 as masks, and the formed fin part has various transverse dimensions, thereby being beneficial to meeting the diversified requirements of a semiconductor structure and further being beneficial to improving the electrical performance of the semiconductor structure.
In this embodiment, after the sacrificial layer 305 is subsequently removed, the fin portions 307 with equal intervals may be obtained. In other embodiments, after removing the sacrificial layer, fins with unequal intervals may also be obtained.
Referring to fig. 17, a schematic diagram of a third embodiment of the semiconductor structure of the present invention is shown.
The same parts of this embodiment as those of the first embodiment are not described herein again, and the differences between this embodiment and the first embodiment are:
the plurality of first sidewall layers 404 arranged in parallel form a sidewall group 410, in the same sidewall group 410, the interval between adjacent first sidewall layers 404 is a first interval d1, the interval between adjacent sidewall groups 410 is a second interval d2, and the first interval d1 is smaller than the second interval d 2.
In the same sidewall group 410, the sacrificial unit located on any sidewall of the same first sidewall layer 404 includes a sacrificial layer 405, and the sacrificial layer 405 is filled between the adjacent first sidewall layers 404.
The second sidewall layer 406 is formed on the sidewall of the outermost sacrificial layer 405 in the sidewall group 410.
In the same sidewall group, the first sidewall layer 404 and the sacrificial layer 405 and the second sidewall layer 406 on the sidewalls of the first sidewall layer 404 constitute graphic elements, and the graphic elements are spaced apart from each other.
In the embodiment of the invention, the extending direction perpendicular to the first sidewall layers 404 is taken as the transverse direction, the interval between the first sidewall layers 404 is the first interval d1, the interval between the adjacent sidewall groups 410 is the second interval d2, the first interval d1 is smaller than the second interval d2, after the sacrificial layer 405 is subsequently removed, the substrate 400 is etched by taking the first sidewall layers 404 and the second sidewall layers 406 as masks, and the formed fin has various transverse sizes, so that the requirement of diversification of a semiconductor structure is favorably met, and the electrical performance of the semiconductor structure is favorably improved.
It should be noted that the embodiments of the present invention are applicable to forming a dual-port sram.
Referring to fig. 20, a schematic diagram of a fourth embodiment of the semiconductor structure of the present invention is shown.
The same parts of this embodiment and the third embodiment are not described herein again, and the differences between this embodiment and the third embodiment are:
the plurality of first sidewall layers 504 arranged in parallel form a sidewall group, and in the same sidewall group, the interval between adjacent first sidewall layers 504 is a first interval D1, the interval between adjacent sidewall groups is a second interval D2, and the first interval D1 is smaller than the second interval D2.
A second sidewall layer 506 is formed on the sidewalls of the pattern assembly.
Taking the extending direction perpendicular to the first sidewall layer 504 as the lateral direction, the lateral dimension of the sacrificial layer 505 is larger than the first spacing D1 and smaller than the second spacing D2, and twice the lateral dimension of the sacrificial layer 505 is larger than the second spacing D2.
In the embodiment of the invention, the extending direction perpendicular to the first sidewall layer 504 is taken as the transverse direction, in the same sidewall group 510, the interval between the adjacent first sidewall layers 504 is the first interval D1, the interval between the adjacent sidewall groups is the second interval D2, the first interval D1 is smaller than the second interval D2, the transverse dimension of the sacrificial layer 505 is larger than the first interval D1 and smaller than the second interval D2, after the sacrificial layer 505 is subsequently removed, the substrate 500 is etched by taking the first sidewall layer 504 and the second sidewall layer 506 as masks, and the interval between the formed fins has at least three sizes, so that the requirement of diversification of the semiconductor structure can be met, and the electrical performance of the semiconductor structure can be improved.
The semiconductor structure of this embodiment may be formed by the formation method of the foregoing embodiment, or may be formed by other formation methods. For a detailed description of the semiconductor structure of this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (21)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a plurality of discrete first sidewall layers on the substrate;
performing one or more graphic element forming processes on the first sidewall layer, wherein the graphic element forming processes comprise the following steps: forming a sacrificial layer on the side wall of the first side wall layer; forming a second side wall layer on the side wall of the sacrificial layer;
after the graphic unit forming process is completed, removing the sacrificial layer;
and after removing the sacrificial layer, etching the substrate by taking the first side wall layer and the second side wall layer as masks to form a plurality of discrete fin parts.
2. The method of claim 1, wherein after the patterning process is completed, the first sidewall layer and the sacrificial layer and the second sidewall layer on the same sidewall of the first sidewall layer form a patterning unit, and the patterning units are spaced apart from each other.
3. The method of claim 1, wherein after the patterning process is completed, the first sidewall layer and the sacrificial layer and the second sidewall layer on the same sidewall of the first sidewall layer form a patterning unit, and the patterning units are in contact with each other.
4. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming a plurality of discrete first sidewall layers on the substrate, a plurality of the first sidewall layers arranged in parallel constitute a sidewall group, in the same sidewall group, an interval between adjacent first sidewall layers is a first interval, an interval between adjacent sidewall groups is a second interval, and the first interval is smaller than the second interval;
the number of times of the graphic unit forming process is one, and in the step of forming the sacrificial layer on the side wall of the first side wall layer, in the same side wall group, the region between the adjacent first side wall layers is filled with the sacrificial layer;
in the step of forming a second sidewall layer on the sidewall of the sacrificial layer, the second sidewall layer is formed on the sidewall of the sacrificial layer on the outermost side in the sidewall group;
after the graphic unit forming process is completed, in the same side wall group, the first side wall layer, the sacrificial layer positioned on the side wall of the first side wall layer and the second side wall layer form graphic units, and the graphic units are spaced from each other.
5. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming a plurality of discrete first sidewall layers on the substrate, a plurality of the first sidewall layers arranged in parallel constitute a sidewall group, in the same sidewall group, an interval between adjacent first sidewall layers is a first interval, an interval between adjacent sidewall groups is a second interval, and the first interval is smaller than the second interval;
the number of times of the graphic unit forming process is one, in the step of forming the sacrificial layer on the side wall of the first side wall layer, the area between the adjacent first side wall layers is filled with the sacrificial layer, and the side wall group and the sacrificial layer are used as a graphic set;
in the step of forming a second sidewall layer on the sidewalls of the sacrificial layer, the second sidewall layer is formed on the sidewalls of the pattern set.
6. The method of claim 5, wherein in the step of forming a sacrificial layer on the sidewalls of the first sidewall layer with a lateral direction perpendicular to the extending direction of the first sidewall layer, the sacrificial layer has a lateral dimension greater than the first spacing and less than the second spacing, and twice the lateral dimension of the sacrificial layer is greater than the second spacing.
7. The method of forming a semiconductor structure according to any one of claims 1 to 5, wherein the step of forming the sacrificial layer includes: conformally covering a sacrificial material layer on the first side wall layer and the substrate exposed by the first side wall layer; and etching the sacrificial material layer by adopting an anisotropic etching process to expose the top of the first side wall layer, and taking the sacrificial material layer remained on the side wall of the first side wall layer as the sacrificial layer.
8. The method of claim 7, wherein the sacrificial material layer is formed using an atomic layer deposition process or a plasma enhanced chemical vapor deposition process.
9. The method of forming a semiconductor structure according to any of claims 1 to 5, wherein the step of forming the second sidewall layer comprises: forming a side wall material layer on the first side wall layer, the sacrificial layer and the substrate exposed from the first side wall layer and the sacrificial layer; and etching the side wall material layer by adopting an anisotropic etching process to expose the tops of the first side wall layer and the sacrificial layer, wherein the rest side wall material layer positioned on the side wall of the sacrificial layer is used as the second side wall layer.
10. The method for forming a semiconductor structure according to claim 9, wherein the sidewall material layer is formed by an atomic layer deposition process or a chemical vapor deposition process.
11. The method of forming a semiconductor structure according to any one of claims 1 to 5, wherein a material of the sacrificial layer comprises amorphous carbon.
12. The method of forming a semiconductor structure according to any one of claims 1 to 5, wherein a material of the first sidewall layer includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride boron silicon and boron nitride silicon carbide;
the material of the second side wall layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride and boron nitride silicon carbide.
13. The method of forming a semiconductor structure according to any of claims 1 to 5, wherein the first sidewall layer is formed using a self-aligned double patterning process.
14. A semiconductor structure, comprising:
a substrate; a plurality of discrete first sidewall layers on the substrate;
the sacrificial unit is positioned on the side wall of the first side wall layer, and the sacrificial unit positioned on any side wall of the same first side wall layer comprises a sacrificial layer or a plurality of sacrificial layers which are arranged in parallel;
and the second side wall layer is positioned on the side wall of the sacrificial layer, and when the sacrificial unit positioned on any side wall of the first side wall layer comprises a plurality of sacrificial layers which are arranged in parallel, the second side wall layer is filled between two adjacent sacrificial layers on the same side wall of the first side wall layer.
15. The semiconductor structure of claim 14, wherein said first sidewall layer and said sacrificial layer and said second sidewall layer on the same sidewall of said first sidewall layer form a pattern unit, said pattern units being spaced apart from each other.
16. The semiconductor structure of claim 14, wherein said first sidewall layer and said sacrificial layer and said second sidewall layer on the same sidewall of said first sidewall layer form a pattern unit, said pattern units being in contact with each other.
17. The semiconductor structure of claim 14, wherein a plurality of said first sidewall layers arranged in parallel form a set of sidewalls, and in the same set of sidewalls, the spacing between adjacent first sidewall layers is a first spacing, the spacing between adjacent sets of sidewalls is a second spacing, and the first spacing is smaller than the second spacing;
in the same side wall group, the sacrificial unit positioned on any side wall of the same first side wall layer comprises a sacrificial layer, and the sacrificial layer is filled between the adjacent first side wall layers;
the second side wall layer is formed on the side wall of the sacrificial layer on the outermost side in the side wall group;
in the same side wall group, the first side wall layer and the sacrificial layer and the second side wall layer which are positioned on the side wall of the first side wall layer form graphic units, and the graphic units are mutually spaced.
18. The semiconductor structure of claim 14, wherein a plurality of said first sidewall layers arranged in parallel form a set of sidewalls, and in the same set of sidewalls, the spacing between adjacent first sidewall layers is a first spacing, the spacing between adjacent sets of sidewalls is a second spacing, and the first spacing is smaller than the second spacing;
the sacrificial layer is filled between the adjacent first side wall layers, and the side wall group and the sacrificial layer are used as a graph set;
the second sidewall layer is formed on the sidewalls of the pattern assembly.
19. The semiconductor structure of claim 18, wherein a lateral dimension of the sacrificial layer is greater than the first spacing and less than the second spacing, and wherein twice a lateral dimension of the sacrificial layer is greater than the second spacing, in a lateral direction perpendicular to an extension direction of the first sidewall layer.
20. The semiconductor structure of any one of claims 14 to 18, wherein a material of the sacrificial layer comprises amorphous carbon.
21. The semiconductor structure of any of claims 14 to 18, wherein the material of the first sidewall layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride boron silicon and boron nitride silicon carbide;
the material of the second side wall layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride and boron nitride silicon carbide.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023000458A1 (en) * | 2021-07-19 | 2023-01-26 | 长鑫存储技术有限公司 | Method for forming pattern |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8524605B1 (en) * | 2012-04-16 | 2013-09-03 | Vigma Nanoelectronics | Fabrication and mask design methods using spatial frequency sextupling technique |
| US20160307769A1 (en) * | 2015-04-17 | 2016-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lithographic Technique Incorporating Varied Pattern Materials |
| US9911619B1 (en) * | 2016-10-12 | 2018-03-06 | Globalfoundries Inc. | Fin cut with alternating two color fin hardmask |
-
2019
- 2019-08-30 CN CN201910816171.4A patent/CN112447513A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8524605B1 (en) * | 2012-04-16 | 2013-09-03 | Vigma Nanoelectronics | Fabrication and mask design methods using spatial frequency sextupling technique |
| US20160307769A1 (en) * | 2015-04-17 | 2016-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lithographic Technique Incorporating Varied Pattern Materials |
| US9911619B1 (en) * | 2016-10-12 | 2018-03-06 | Globalfoundries Inc. | Fin cut with alternating two color fin hardmask |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023000458A1 (en) * | 2021-07-19 | 2023-01-26 | 长鑫存储技术有限公司 | Method for forming pattern |
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