CN114373712A

CN114373712A - Semiconductor structure and forming method thereof

Info

Publication number: CN114373712A
Application number: CN202011094544.0A
Authority: CN
Inventors: 金吉松
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-10-14
Filing date: 2020-10-14
Publication date: 2022-04-19
Also published as: US20220115242A1; US11769672B2

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: forming discrete core layers, wherein the opposite side walls of the adjacent core layers in the second direction are respectively a first side wall and a second side wall; forming a sacrificial side wall on the side wall of the core layer; forming a sacrificial layer on a part of the substrate between the adjacent sacrificial side walls; forming a filling layer on a substrate; removing the sacrificial layer to form an opening; removing the sacrificial side wall to form a groove; forming a mask side wall on the side wall of the groove, filling the mask side wall between the side wall of the core layer and the filling layer, and enclosing the mask side wall on the side wall of the groove to form a first groove; forming a second groove which penetrates through the filling layer between the side wall of the groove and the mask side wall of the second side wall; removing the core layer to form a third groove; a dividing layer is formed in at least one of the third groove, the second groove and the first groove, and the corresponding groove is divided along the first direction; and etching the third groove, the second groove and the target layer below the first groove to form a target pattern. The embodiment of the invention improves the graphic precision of the target graphic.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

With the rapid growth of the semiconductor Integrated Circuit (IC) industry, semiconductor technology is driven by moore's law to move towards smaller process nodes, so that the Integrated circuit is developed towards smaller size, higher circuit precision and higher circuit complexity.

In the development of integrated circuits, as the functional density (i.e., the number of interconnect structures per chip) generally increases, the geometric size (i.e., the minimum component size that can be produced by the process steps) also decreases, which increases the difficulty and complexity of integrated circuit fabrication.

At present, with the shrinking of technology nodes, it is a challenge how to improve the matching between the pattern formed on the wafer and the target pattern.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve flexibility and freedom of layout design of a target pattern.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising a target layer for forming a target pattern; forming core layers extending along a first direction and arranged at intervals along a second direction on the substrate, wherein the second direction is perpendicular to the first direction, and the opposite side walls of the core layers adjacent to each other in the second direction are respectively a first side wall and a second side wall; forming a sacrificial side wall on the side wall of the core layer; forming a sacrificial layer extending along a first direction on a part of the substrate between the adjacent sacrificial side walls, wherein the sacrificial layer covers the side walls of the sacrificial side walls on the first side walls and is spaced from the sacrificial side walls on the second side walls; forming a filling layer on the base exposed by the core layer, the sacrificial side wall and the sacrificial layer; removing the sacrificial layer and forming an opening in the filling layer; removing the sacrificial side wall; the opening and the first side wall enclose a groove; forming a mask side wall on the side wall of the groove, wherein the mask side wall is further filled between the core layer side wall and the filling layer, and the mask side wall positioned on the side wall of the groove is surrounded into a first groove; forming a second groove which penetrates through the filling layer between the side wall of the groove and the mask side wall on the second side wall; removing the core layer to form a third groove; a dividing layer is formed in at least one of the third groove, the second groove and the first groove, and the dividing layer divides the corresponding groove along the first direction; and imaging the third groove, the second groove and the target layer below the first groove by taking the partition layer, the mask side wall and the filling layer as masks to form a target image.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate including a target layer for forming a target pattern; the core layers are positioned on the substrate, extend along a first direction and are arranged at intervals along a second direction, the second direction is perpendicular to the first direction, and the side walls opposite to the core layers adjacent to each other in the second direction are a first side wall and a second side wall respectively; the filling layer is positioned on the substrate exposed out of the core layers, a groove penetrating through part of the filling layer is formed between every two adjacent core layers in the second direction, and the groove is exposed out of the first side wall and is spaced from the second side wall; the mask side walls are positioned on the side walls of the grooves and between the side walls of the core layer and the filling layer, and the mask side walls positioned on the side walls of the grooves are encircled to form a first groove; the second groove penetrates through the first groove and the filling layer positioned between the mask side walls of the second side walls; wherein the core layer occupies a space for forming a third groove; and a division layer penetrating at least one of the core layer, the second groove and the first groove in the second direction, the division layer dividing the corresponding groove in the first direction.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the method for forming a semiconductor structure provided by the embodiment of the invention, the sacrificial layer and the mask side wall are used for defining the shape and the position of the first groove, the core layer is used for defining the shape and the position of the second groove, and the second groove is formed in different steps, so that the difficulty in forming the first groove, the second groove and the third groove is reduced, a process window is increased (for example, the optical proximity effect is improved, the limitation of the photoetching resolution is relieved), and the precision of pattern transmission is improved, so that the pattern precision of the first groove, the second groove and the third groove is ensured; wherein, be formed with in at least one recess in third recess, second recess and the first recess and cut apart the layer, cut apart the layer and cut apart corresponding recess along first direction, thereby make and be located can realize less distance between the recess of cutting apart layer both sides, correspondingly, after the target layer formation target figure of third recess, second recess and first recess below is patternized, adjacent target figure also can realize less distance in Head To Head, HTH's position department, and then be favorable To improving the overall arrangement design flexibility and the degree of freedom of target figure, and satisfy the demand that Pitch (Pitch) constantly reduces among the integrated circuit.

Drawings

Fig. 1 to fig. 32 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As can be seen from the background art, it is a challenge to improve the matching between the pattern formed on the wafer and the target pattern. Specifically, in the current back-end process, the difficulty of the patterning process of the metal interconnection line is large, and the process window is small.

For example: when the pattern of the interconnection pattern is complex, the number of masks (masks) required by the photolithography process is large, which not only results in high process cost, but also results in complex pattern of the masks, and the optical proximity correction processing of the masks also has high difficulty, which results in poor pattern precision and pattern quality of the formed interconnection line, and even easily causes the problem of short circuit (Bridge) of the interconnection line at the position where the interconnection line is not needed.

One approach utilizes Dummy interconnect lines (Dummy lines) to increase the window of the lithography process and reduce mask pattern complexity. These dummy interconnect lines are in a floating state during device operation, that is, they are not electrically connected to external circuitry or other interconnect structures. However, these floating dummy interconnect lines tend to increase the parasitic capacitance of the back-end interconnect, resulting in poor performance of the resulting semiconductor structure. The devices formed at present still have the problem of poor performance.

In order to solve the technical problem, in the method for forming a semiconductor structure provided in the embodiment of the present invention, the sacrificial layer and the mask sidewall are used to define the shape and the position of the first groove, the core layer is used to define the shape and the position of the second groove, and the second groove is formed in different steps, which is beneficial to reducing the difficulty in forming the first groove, the second groove and the third groove, increasing the process window (for example, improving the optical proximity effect and alleviating the limitation of the photolithography resolution), and improving the precision of pattern transfer, so that the pattern precision of the first groove, the second groove and the third groove is ensured; the third groove, the second groove and at least one of the first grooves are formed with a dividing layer, the dividing layer divides the corresponding grooves along the first direction, so that the corresponding grooves on two sides of the dividing layer can be separated by a smaller distance, correspondingly, after the target layers below the third groove, the second groove and the first grooves are patterned, the adjacent target patterns can be separated by a smaller distance at the positions of Head To Head (HTH), and therefore the layout design flexibility and the freedom degree of the target patterns can be improved, and the requirement that the Pitch (Pitch) in the integrated circuit is reduced continuously is met.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Referring to fig. 1 and 2, fig. 2 is a cross-sectional view of fig. 1 at position AA, providing a substrate 200 including a target layer 100 for forming a target pattern.

The substrate 200 is used to provide a platform for subsequent processing. The target layer 100 is a film layer to be patterned to form a target pattern. The target pattern may be a gate structure, an interconnection trench in a back-end process, a fin in a fin field effect transistor (FinFET), a channel stack in a Gate All Around (GAA) transistor or a fork gate transistor (forkheet), a Hard Mask (HM) layer, or the like.

In this embodiment, the target layer 100 is a dielectric layer. And patterning the dielectric layer, forming a plurality of interconnection grooves in the dielectric layer, and forming interconnection lines in the interconnection grooves, wherein the dielectric layer is used for realizing the electrical isolation between the adjacent interconnection lines. Accordingly, the target pattern is an interconnect slot. The Dielectric layer is an Inter Metal Dielectric (IMD) layer. The dielectric layer is made of low-k dielectric material, ultra-low-k dielectric material, silicon oxide, silicon nitride or silicon oxynitride.

In this embodiment, a semiconductor device such as a transistor or a capacitor may be formed in the substrate 200, and a functional structure such as a resistance structure or a conductive structure may be formed in the substrate 200. In this embodiment, the base 200 further includes a substrate 110 located at the bottom of the target layer 100. As an example, the substrate 110 is a silicon substrate.

In this embodiment, the substrate 200 further includes a hard mask material layer 115 on the target layer 100. The hard mask material layer 115 is patterned to form a hard mask layer, and then the target layer 100 is patterned by using the hard mask layer as a mask, which is beneficial to improving the process stability of the patterned target layer 100 and the precision of pattern transfer.

The material of the hard mask material layer 115 includes one or more of titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon oxycarbonitride. As an example, the material of the hard mask material layer 115 is titanium nitride.

In a specific process, according to actual process requirements, a stress buffer layer can be further disposed between the hard mask material layer 115 and the target layer 100, so as to improve adhesion between the hard mask material layer 115 and the target layer 100 and reduce stress generated between films. In addition, an etching stop layer can be arranged between the hard mask material layer 115 and the stress buffer layer and on the hard mask material layer 115 to define a stop position of a subsequent etching process, which is beneficial to improving the effect of the subsequent patterning process. The description of the stress buffer layer and the etch stop layer is not repeated herein.

With continued reference to fig. 1 and 2, core (Mandrel) layers 120 extending in a first direction (as shown by the X-direction in fig. 1) and arranged at intervals in a second direction (as shown by the Y-direction in fig. 1) perpendicular to the first direction are formed on the substrate 200, and the sidewalls opposite to the core layers 120 in the second direction are a first sidewall 11 and a second sidewall 12, respectively.

In this embodiment, the core layer 120 is used to occupy a space position for forming the third groove, thereby defining the shape and position of the third groove. Compared with the method of directly forming the third groove through the etching process, in the embodiment, the core layer 120 occupying the third groove is formed first, and then the third groove is formed by removing the core layer 120, which is beneficial to reducing the forming difficulty of the third groove and increasing the process window for forming the third groove, so that the pattern precision of the third groove is ensured, and correspondingly, after the target layer 100 below the third groove is subsequently etched to form the target pattern, the pattern precision of the target pattern is beneficial to being improved. The core layer 120 also provides support for the subsequent formation of the sacrificial sidewall.

In this embodiment, the core layer 120 is made of a material that is easy to remove, so as to reduce the difficulty of the subsequent process for removing the core layer 120. The core layer 120 is a single-layer or multi-layer structure, and the material of the core layer 120 includes one or more of amorphous silicon, polysilicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride and silicon oxycarbonitride.

As an example, the core layer 120 has a single-layer structure, and the material of the core layer 120 is amorphous silicon.

Referring to fig. 3 and 4, fig. 4 is a cross-sectional view of fig. 3 at position AA, and a sacrificial side wall 130 is formed on the side wall of the core layer 120.

The sacrificial sidewall spacers 130 are used to occupy space for the subsequent formation of mask sidewall spacers. The thickness of the sacrificial side wall 130 also defines the interval between the subsequent adjacent third grooves and the second grooves, and in this embodiment, the designed minimum interval between the adjacent third grooves and the second grooves is easily satisfied by adjusting the thickness of the sacrificial side wall 130.

In this embodiment, a core layer 120 is formed first, and then a sacrificial side wall 130 is formed on the side wall of the core layer 120, where the sacrificial side wall 130 is an Outer side wall (Outer Spacer); after the third grooves are formed by removing the core layer 120, the distance between the adjacent third grooves along the first direction is defined by the core layer 120, and compared with the method of forming the grooves first and then forming the inner side walls on the side walls of the grooves, in the embodiment, the distance between the adjacent second grooves along the first direction is not the sum of the distance between the adjacent core layers and twice the thickness of the inner side walls, so that a smaller distance between the adjacent third grooves along the first direction is favorably realized, correspondingly, after the target layer below the third grooves is patterned to form the target pattern, the adjacent target pattern can realize a smaller distance at the position of the head to the head, which is favorable for improving the layout design flexibility and the freedom of the target pattern, and is also favorable for saving the process cost.

The sacrificial side wall 130 is made of a material having an etching selectivity with the core layer 120 and the target layer 100, and the material of the sacrificial side wall 130 includes one or more of titanium oxide, silicon nitride, silicon carbide, silicon oxycarbide, aluminum oxide, and amorphous silicon. As an example, the sacrificial spacer 130 is made of silicon nitride.

In this embodiment, the forming of the sacrificial side wall 130 includes an atomic layer deposition process, which is beneficial to improving the thickness uniformity of the sacrificial side wall 130 and is easy to accurately control the thickness of the sacrificial side wall 130.

Referring to fig. 5 and 6, fig. 6 is a cross-sectional view of fig. 5 at a position AA, a sacrificial layer 140 extending along a first direction (as shown in an X direction in fig. 5) is formed on a portion of the substrate 200 between adjacent sacrificial side walls 130, and the sacrificial layer 140 covers sidewalls of the sacrificial side walls 130 on the first side walls 11 and is spaced apart from the sacrificial side walls 130 on the second side walls 12.

The sacrificial layer 140 is used to occupy a spatial location for forming the opening. And forming a filling layer on the substrate 200 exposed by the core layer 120, the sacrificial side wall 130 and the sacrificial layer 140, and removing the sacrificial side wall 130 to form a trench by enclosing the opening and the first side wall 11, wherein the trench is used for providing support for forming a mask side wall subsequently, so that the mask side wall in the trench can be enclosed to form a first groove. Therefore, in this embodiment, the shape and the position of the first groove are defined by the sacrificial layer 140 and the mask sidewall.

Compared with the method that the shape and the position of the first groove are directly defined by the etching process or a single film, the shape and the position of the first groove are defined by the sacrificial layer 140 and the mask sidewall, and in the step of forming the sacrificial layer 140, the critical dimension of the sacrificial layer 140 is larger than the critical dimension of the subsequent first groove (for example, the dimension along the first direction and the second direction), which is beneficial to reducing the process difficulty of forming the sacrificial layer 140 and reducing the process precision requirement for forming the sacrificial layer 140, for example: the difficulty of the photoetching process for forming the sacrificial layer 140 is reduced, the tolerance of the photoetching process for forming the sacrificial layer 140 is improved, the pattern quality and the pattern precision of the sacrificial layer 140 are higher, and the pattern quality and the pattern precision of the subsequent first groove are correspondingly ensured.

In this embodiment, the sacrificial layer 140 covers the sidewall of the sacrificial sidewall 130 on the first sidewall 11 and is spaced apart from the sacrificial sidewall 130 on the second sidewall 12, wherein, along the second direction, a space between the sacrificial layer 140 and the sacrificial sidewall 130 on the second sidewall 12 is used for filling a subsequent filling layer, so as to form a second groove in the subsequent step.

The sacrificial layer 140 is selected to have an etching selectivity with respect to the materials of the core layer 120 and the target layer 100. The material of the sacrificial layer 140 includes one or more of an organic planarization material, silicon oxide, and amorphous carbon. The organic planarization material includes BARC (Bottom Anti-reflective coating), SOC (spin-on carbon), and the like. In this embodiment, the material of the sacrificial layer 140 is spin-on carbon. The filling performance of the spin-coated carbon is good, and the spin-coated carbon material is easy to etch, which is beneficial to reducing the difficulty of forming the sacrificial layer 140 and the difficulty of subsequently removing the sacrificial layer 140.

In this embodiment, the top surface of the sacrificial layer 140 is higher than the top surface of the core layer 120. The process of forming the sacrificial layer 140 includes the steps of forming a sacrificial material layer covering the sacrificial sidewall 130 and the core layer 120 and patterning the sacrificial material layer, and the top surface of the sacrificial layer 140 is higher than the top surface of the core layer 120, so that the step of removing the sacrificial material layer higher than the top surface of the core layer is omitted, wherein the difficulty of removing the sacrificial material layer higher than the top surface of the core layer 120 is high, and the process difficulty of forming the sacrificial layer 140 is further reduced.

In this embodiment, the sacrificial layer 140 further covers the top surface of the sacrificial sidewall 130 on the first sidewall 11.

In other embodiments, the top surface of the sacrificial layer can also be flush with the top surface of the core layer.

Referring to fig. 7 to 9, a filling layer 160 is formed on the substrate 200 where the core layer 120, the sacrificial sidewall spacer 130 and the sacrificial layer 140 are exposed.

The filling layer 160 is used to provide a process base for the subsequent formation of the second groove. The filling layer 160 is used as a mask of the patterning target layer 100 with the subsequent mask sidewall and the subsequent dividing layer. In this embodiment, the filling layer 160 includes a predetermined region D (as shown in fig. 8) between the sidewall of the sacrificial layer 140 and the sacrificial sidewall 130 on the second sidewall 12, and the predetermined region D is used for forming the second groove.

The filling layer 160 is selected from materials having etching selectivity with the materials of the core layer 120, the sacrificial layer 140 and the sacrificial sidewall spacer 130. The material of the filling layer 160 includes spin-on silicon oxide, metal oxide (e.g., titanium oxide), polysilicon, and amorphous silicon. In this embodiment, the material of the filling layer 160 is spin-on silicon oxide. The process of forming the filling layer 160 includes a spin coating process, which is beneficial to improving the filling capability and filling quality of the filling layer 160, and is also beneficial to improving the flatness of the top surface of the filling layer 160.

In this embodiment, the step of forming the filling layer 160 includes:

as shown in fig. 7, fig. 7 is a cross-sectional view based on fig. 6, a filler material layer 150 covering the core layer 120 and the sacrificial layer 140, and the sacrificial sidewall spacers 130 is formed on the substrate 200.

The process of forming the layer of fill material 150 includes one or more of an atomic layer deposition process, a chemical vapor deposition process, and a spin-on process. As an example, the filling material layer 150 is formed using a spin coating process. The spin coating process is simple to operate, has low process cost, and is beneficial to improving the flatness of the top surface of the filling material layer 150.

As shown in fig. 8 and 9, fig. 9 is a cross-sectional view of fig. 8 at position AA, with the filler material layer 150 above the top surface of the core layer 120 removed, and the remaining filler material layer 150 serving as the filler layer 160.

In this embodiment, the filling material layer 150 above the top surface of the core layer 120 is removed by a dry etching process (e.g., an anisotropic dry etching process).

Referring to fig. 10 and 11, fig. 11 is a cross-sectional view of fig. 10 at AA, where the sacrificial layer 140 is removed and an opening 10 is formed in the filling layer 160.

In this embodiment, the forming method further includes: the sacrificial sidewall spacers 130 are removed. After removing the sacrificial side wall 130, the opening 10 is used to form a trench with the first side wall 11.

In this embodiment, the sacrificial layer 140 further covers the top surface of the sacrificial sidewall 130 on the first sidewall 11. Therefore, the sacrificial layer 140 is removed first to expose the sacrificial sidewall spacers 130 on the first sidewalls 11, so as to remove the sacrificial sidewall spacers 130. In other embodiments, the sequence of removing the sacrificial layer and removing the sacrificial side wall can be flexibly adjusted according to actual process requirements.

The process of removing the sacrificial layer 140 includes one or both of wet etching and dry etching. In this embodiment, the sacrificial layer 140 is removed by a dry etching process. Specifically, the material of the sacrificial layer 140 is spin-on carbon, and the sacrificial layer 140 is removed by an ashing process. As an example, the sacrificial layer 140 is removed by using oxygen plasma, and the process for removing the sacrificial layer 140 is simple, has low difficulty, and has little influence on other film layers.

Referring to fig. 12 and 13, fig. 13 is a cross-sectional view of fig. 12 at position AA, with the sacrificial side wall 130 removed; the opening 10 and the first side wall 11 enclose a groove 30.

The sidewalls of the trench 30 are used to provide support for forming the mask sidewalls. Accordingly, the trench 30 and the mask sidewall on the sidewall of the trench 30 are used to define the shape and position of the first recess.

By removing the sacrificial side wall 130, the first side wall 11 of the core layer 120 is exposed, and after the mask side wall is formed on the side wall of the trench 30, the mask side wall located on the side wall of the trench 30 encloses a first groove, the interval between the first groove and the first side wall 11 is the thickness of the mask side wall, and the interval between the first groove and the third groove is the thickness of the mask side wall, so that the minimum interval between the first groove and the third groove can be designed.

In this embodiment, the sacrificial spacer 130 is removed, and a gap 20 is formed between the sidewall of the core layer 120 and the filling layer 160. The gap 20 is used for reserving a space for forming a mask sidewall.

The process of removing the sacrificial sidewall spacers 130 includes one or both of dry etching and wet etching. In this embodiment, the sacrificial side wall 130 is removed by using a wet etching process, which is easy to realize a high etching selection ratio, and is beneficial to completely removing the sacrificial side wall 130, and the operation is simple.

Referring to fig. 14 and 15, in the present embodiment, the forming method further includes: after the core layer 120 is formed, a third blocking groove 210 (shown in fig. 15) penetrating the core layer 120 in the second direction is formed.

The third blocking groove 210 serves to divide the core layers 120 in the first direction, so that a smaller distance can be achieved between the adjacent core layers 120 in the first direction. The third blocking groove 210 is also used to provide a spatial location for forming a third dividing layer, so that the third dividing layer divides the third groove along the first direction after the core layer 120 is subsequently removed to form the third groove.

As an example, after removing the sacrificial layer 140 and the sacrificial sidewall spacers 130, and before forming mask sidewall spacers, the third blocking trench 210 is formed. Before the mask side wall is formed, the third blocking groove 210 is formed, so that in the subsequent step of forming the mask side wall, the mask side wall can be formed in the third blocking groove 210, the mask side wall located in the third blocking groove 210 can be used as a third segmentation layer, the steps of forming the mask side wall and the third segmentation layer are correspondingly integrated, the step of additionally forming the third segmentation layer is omitted, the process is simplified, and the process integration degree is improved.

In other embodiments, the third division layer may be formed by other process steps according to actual process requirements.

The specific steps for forming the third blocking groove in this embodiment will be described in detail below with reference to the accompanying drawings.

As shown in fig. 14, a capping layer 170 covering the core layer 120 is formed on the filling layer 160, and the capping layer 170 also fills the gap 20 and the trench 30.

Subsequently, a division opening is formed in the capping layer 170, and the remaining capping layer 170 is used as a mask for etching the core layer 120. In this embodiment, the material of the capping layer 170 includes spin-on carbon.

As shown in fig. 14, division openings 180 are formed in the clad layer 170 to cross the core layer 120, the trenches 30, the filling layer 160, and the gaps 20 in a second direction (as shown in a Y direction in fig. 14).

The division openings 180 are used to define the size and position of the cutting of the core layer 120.

In this embodiment, the dividing opening 180 spans the core layer 120, the trench 30, the filling layer 160 and the gap 20, so that the requirement on the dimensional accuracy of the dividing opening 180 along the second direction is low, which is beneficial to reducing the difficulty of forming the dividing opening 180 and increasing the process window for forming the dividing opening 180.

As shown in fig. 15, the cladding layer 170 is used as a mask to remove the core layer 120 exposed by the dividing openings 180, and form a third blocking groove 210 penetrating the core layer 120 along the second direction; the capping layer 170 is removed.

Due to the etching selection ratio between the core layer 120 and the substrate 200 or the filling layer 160, even if the segmentation openings 180 still span the trenches 30, the filling layer 160 and the gaps 20, the process of removing the core layer 120 exposed by the segmentation openings 180 has a low probability of causing false etching on the substrate 200 and the filling layer 160.

In this embodiment, an anisotropic dry etching process is used to remove the core layer 120 exposed by the dividing openings 180, thereby improving the precision of pattern transfer. In this embodiment, the cap layer 170 is removed by one or both of an ashing process and a wet stripping process.

In other embodiments, the step of forming the third division layer may further include: after the core layer is formed and before the core layer is removed, ion doping is performed on a part of the core layer, which is suitable for improving the etching resistance of the core layer, and the core layer doped with ions is used as the third division layer. The core layer is made of one or more of amorphous silicon, polycrystalline silicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride and silicon oxycarbonitride; ions that ion-dope a portion of the core layer include one or more of boron ions, phosphorus ions, and argon ions. The third division layer is formed by ion doping of a part of the core layer, so that the etching resistance of the third division layer is larger than that of the core layer, the core layer and the third division layer can have a high selection ratio in the step of removing the core layer to form the third groove, the third division layer can be reserved to be used for dividing the third groove along the first direction correspondingly, the third division layer is formed by ion doping of the part of the core layer, the steps of forming the third blocking groove by etching and filling the third division layer in the third blocking groove are omitted, and the process is simplified.

Referring to fig. 16 to 17, the forming method further includes: after the filling layer 160 is formed and before the mask sidewall is formed, a second blocking trench 230 penetrating through the filling layer 160 in the predetermined region D along the second direction is formed.

The second blocking groove 230 is used for dividing the filling layer 160 of the preset region D along the first direction, and the second blocking groove 230 also provides a spatial position for forming a second divided layer. The second dividing layer in the second blocking groove 230 is formed subsequently, and after the second groove is formed in the filling layer 160 of the second preset region D, the second groove can be divided by the second dividing layer along the first direction, which is beneficial to realizing a smaller distance between the second grooves along the first direction.

In this embodiment, after the sacrificial layer 140 and the sacrificial sidewall spacer 130 are removed and before the mask sidewall spacer is formed, the second blocking trench 230 is formed. The second blocking groove 230 is formed before the mask side wall is formed, so that in the step of forming the mask side wall, the mask side wall can be formed in the second blocking groove 230, the mask side wall in the second blocking groove 230 is in contact with the mask side wall, the mask side wall filled in the second blocking groove can be used as a second division layer, correspondingly, the steps of forming the mask side wall and the second division layer are integrated, the step of additionally forming a third division layer is omitted, the process is simplified, and the process integration degree is improved.

The process sequence of forming the second blocking groove 230 is not limited thereto. In other embodiments, the process sequence for forming the second blocking groove can be flexibly adjusted according to the actual process.

As an example, the second blocking groove 230 is formed after the third blocking groove 210 is formed. The order of forming the second blocking groove 230 and the third blocking groove 210 is not limited thereto.

The specific steps of forming the second blocking groove 230 in this embodiment will be described below with reference to the accompanying drawings.

As shown in fig. 16, a pattern definition layer 190 covering the core layer 120 is formed on the filling layer 160, and the pattern definition layer 190 also fills the gaps 20 and the trenches 30.

Subsequently, a cutting opening is formed in the pattern definition layer 190, and the remaining pattern definition layer 190 is used as a mask for etching the filling layer 160 to form a second blocking trench.

In this embodiment, the material of the pattern definition layer 190 is spin-on carbon.

As shown in fig. 16, a cut opening 220 crossing the filling layer 160, the trench 30, the core layer 120 and the gap 20 in the preset region D in the second direction is formed in the pattern definition layer 190.

The cutting opening 220 is used to define the size, shape and location of the second blocking slot.

In this embodiment, the cut opening 220 spans the filling layer 160, the trench 30, the core layer 120 and the gap 20 in the preset region D, so that the requirement on the dimensional accuracy of the cut opening 220 along the second direction is low, which is beneficial to reducing the difficulty of forming the cut opening 220 and increasing the process window for forming the cut opening 220.

As shown in fig. 17, the pattern definition layer 190 is used as a mask to remove the filling layer 160 exposed by the cutting opening 220, and the second blocking groove 230 is formed in the filling layer 160 in the predetermined region D; the pattern definition layer 190 is removed.

In this embodiment, an anisotropic dry etching process is used to remove the filling layer 160 exposed by the cut opening 220, which is beneficial to improving the precision of pattern transfer and the controllability of etching profile. In this embodiment, the pattern definition layer 190 is removed by one or both of an ashing process and a wet stripping process.

Referring to fig. 18 and 19, fig. 19 is a cross-sectional view of fig. 18 at a position AA, a mask sidewall 240 is formed on the sidewall of the trench 30, the mask sidewall 240 is further filled between the sidewall of the core layer 120 and the filling layer 160, and the mask sidewall 240 located on the sidewall of the trench 30 encloses a first groove 101.

The mask sidewall spacers 240 fill the gap 20.

The mask sidewall spacers 240 are used to mask the patterning target layer 100 with the filling layer 160 and the partition layer. The mask sidewall 240 is also used to realize isolation between adjacent grooves, so that the thickness of the mask sidewall 240 is easily adjusted to satisfy the designed minimum interval between adjacent grooves in this embodiment.

The first groove 101 is used to define the shape and position of the target pattern.

In this embodiment, the thickness of the mask sidewall 240 on the sidewall of the trench 30 is greater than or equal to 0.5 times the thickness of the sacrificial sidewall 130, so as to ensure that the mask sidewall 240 can fill the gap 20.

In this embodiment, the thickness of the mask sidewall 240 is the same as that of the sacrificial sidewall 130, accordingly, after the second groove and the third groove are formed subsequently, the intervals between two adjacent grooves in the second direction are the same, and after the target layer 100 below the patterned first groove 101, the second groove, and the third groove forms the target pattern, the intervals between the target patterns in the second direction are also the same, so that the interval uniformity of the target pattern is improved.

In specific implementation, the thickness of the mask side wall 240 can be different from that of the sacrificial side wall 130, so that the interval between two adjacent grooves is different by adjusting the thicknesses of the mask side wall 240 and the sacrificial side wall 130 according to actual requirements, and diversified intervals are formed between target patterns.

In this embodiment, the mask sidewall 240 is made of a material having an etching selectivity with the materials of the core layer 120 and the substrate 200, the material of the mask sidewall 240 includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, titanium nitride, silicon carbide, silicon oxycarbide, and amorphous silicon, and the material of the mask sidewall 240 is the same as or different from the material of the sacrificial sidewall 130.

In this embodiment, the process for forming the mask sidewall 240 includes an atomic layer deposition process, which is beneficial to improving the thickness uniformity, the gap filling capability and the film forming quality of the mask sidewall 240, and is beneficial to accurately controlling the thickness of the mask sidewall 240.

In this embodiment, the method for forming the semiconductor structure further includes: after the filling layer 160 is formed, the second division layer 320 (as shown in fig. 18) penetrating a portion of the filling layer 160 of the predetermined region D in the second direction is formed, and the second division layer 320 divides the filling layer 160 of the predetermined region D in the first direction.

The second segmentation layer 320 is also used as a mask for subsequent patterning of the target layer 100. By forming the second dividing layer 320, after the second grooves penetrating the filling layer 160 of the predetermined region D are formed, the second grooves can be divided by the second dividing layer 320 along the first direction, which is advantageous to realize a smaller distance between the second grooves along the first direction.

In this embodiment, the step of forming the second dividing layer 320 includes: in the step of forming the mask sidewall spacers 240, the mask sidewall spacers 240 are further formed in the second blocking groove 230, the mask sidewall spacers 240 located in the second blocking groove 230 are in contact with each other, and the mask sidewall spacers 240 filled in the second blocking groove 230 are used as the second division layers 320.

Therefore, in this embodiment, the second division layer 320 is formed by the mask sidewall 240 with a sidewall in contact, and the material of the second division layer 320 is correspondingly the same as the material of the mask sidewall 240.

In this embodiment, the method for forming the semiconductor structure further includes: after the core layer 120 is formed, before the core layer 120 is removed, a third divided layer 330 (shown in fig. 18) penetrating the core layer 120 in the second direction is formed, and the third divided layer 330 divides the core layer 120 in the first direction.

The third division layer 330 is also used as a mask for the subsequent patterning of the target layer 100.

Subsequently, the core layer 120 is removed to form a third groove, the third groove is correspondingly formed with the third dividing layer 330, and the third dividing layer 330 divides the third groove along the first direction, so that a smaller distance can be realized between the third grooves located at two sides of the third dividing layer 330, and accordingly, after the target layer 100 below the third groove is patterned to form the target pattern, a smaller distance can also be realized between adjacent target patterns at the head-to-head position.

In this embodiment, the step of forming the third dividing layer 330 includes: in the step of forming the mask sidewall 240, the mask sidewall 240 is further formed in the third blocking groove 210, the mask sidewall 240 located in the third blocking groove 210 is in contact with the third blocking groove, and the mask sidewall 240 located in the third blocking groove 210 is used as the third division layer 330.

Therefore, in this embodiment, the third dividing layer 330 is formed by the mask sidewall 240 with the sidewall in contact, and the material of the third dividing layer 330 is correspondingly the same as the material of the mask sidewall 240.

In this embodiment, the mask sidewall spacers 240 are filled in the second blocking trench 230 to form the second dividing layer 320, and are further filled in the third blocking trench 210 to form the third dividing layer 330 as an example. In other embodiments, forming the second and third division layers may also include other steps according to actual process requirements.

Referring to fig. 20 to 24, in this embodiment, after forming the first groove 101, before forming the second groove and removing the core layer, the method for forming a semiconductor structure further includes: a first division layer 310 is formed in the first groove 101.

The first segmentation layer 310 is also used as a mask for the subsequent patterning of the target layer 100.

The first dividing layer 310 is used for dividing the first grooves 101 along the first direction, so that a smaller distance can be realized between adjacent first grooves 101 along the first direction, and after the target layer 100 below the patterned first grooves 101 forms a target pattern, the target pattern can correspondingly realize a smaller distance at the head-to-head position, which is beneficial to improving the design flexibility and the degree of freedom of the target pattern and meeting the requirement of continuously reducing the pitch in an integrated circuit.

The first division layer 310 is selected to have an etch selectivity with respect to the materials of the core layer 120 and the substrate 200. The material of the first division layer 310 includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, titanium nitride, silicon carbide, silicon oxycarbide, and amorphous silicon.

The specific steps of forming the first dividing layer 310 according to this embodiment will be described below with reference to the accompanying drawings.

As shown in fig. 20 and 21, fig. 21 is a cross-sectional view of fig. 20 at position AA, and a support layer 250 covering the mask sidewall 240, the core layer 120 and the first groove 101 is formed on the filling layer 160.

The support layer 250 is used for forming a first blocking groove later, and after the first blocking groove is formed, the support layer 250 is used for providing a support function for forming a first division layer in the first blocking groove.

After the first division layer is formed, the supporting layer 250 is also removed, so that the supporting layer 250 is made of a material which is easy to remove, thereby reducing the difficulty of removing the supporting layer 250. In this embodiment, the material of the supporting layer 250 is Spin-On Carbon (SOC). The method is suitable for a spin coating process, is beneficial to reducing the difficulty of forming the supporting layer 250 and improving the flatness of the top surface of the supporting layer 250, and the spin-coated carbon is easy to remove.

In other embodiments, the material of the supporting layer may further include one or more of an Organic Dielectric Layer (ODL), a Bottom Anti-reflective Coating (BARC), a Silicon Anti-reflective Coating (Si-ARC), a Deep ultraviolet light absorbing Oxide (DUO), a Dielectric Anti-reflective Coating (DARC), and an Advanced Patterning Film (APF). In this embodiment, the supporting layer 250 is formed by a spin coating process.

As shown in fig. 20 and 21, a first blocking groove 260 extending in the second direction and crossing the first groove 101 is formed in the support layer 250.

The first blocking groove 260 is used to define the size, shape and position of the first division layer. In this embodiment, the first blocking groove 260 further spans the adjacent mask sidewall 240, the core layer 120 and the filling layer 160 along the second direction, which is beneficial to reducing the requirement on the dimensional accuracy of the first blocking groove 260 along the second direction.

As shown in fig. 22 to 24, the first division layer 310 is formed in the first blocking groove 260.

In this embodiment, the step of forming the first division layer 310 in the first blocking groove 260 includes: as shown in fig. 22, a material layer 270 is fully filled in the first blocking groove 260, and the material layer 270 also covers the support layer 250; as shown in fig. 23 to 24, fig. 24 is a cross-sectional view of fig. 23 at position AA, the dividing material layer 270 on the support layer 250, the mask sidewall 240, the core layer 120 and the filling layer 160 is removed, and a portion of the dividing material layer 270 in the first blocking groove 260 is remained to be the first dividing layer 310.

As an example, the partition material layer 270 is formed using a chemical vapor deposition process or an atomic layer deposition process. In the step of forming the partition material layer 270, as the deposition thickness increases, the partition material layer 270 in the first blocking groove 260 gradually contacts, thereby filling the first blocking groove 260.

In this embodiment, a dry etching process (e.g., an anisotropic dry etching process) is used to remove the dividing material layer 270 on the support layer 250, the mask sidewall 240, the core layer 120, and the filling layer 160.

The method for forming the semiconductor structure further comprises the following steps: the support layer 250 is removed in preparation for subsequent processing. The process of removing the support layer 250 includes one or both of an ashing process and a wet stripping process.

Referring to fig. 25 and 26, fig. 26 is a cross-sectional view of fig. 25 at position AA, and a second recess 102 is formed through the fill layer 160 between the sidewalls of the trench 30 and the mask sidewall 240 on the second sidewall 12. The second groove 102 is used to define the shape and position of the target pattern.

In this embodiment, in the step of forming the second groove 102, the mask sidewall 240 may further define a position where etching is stopped along the second direction, so that the etching process for forming the second groove 102 may achieve self-alignment according to the position of the mask sidewall 240, the process window for forming the second groove 102 is correspondingly increased, and the second groove 102 and the first groove 101, and the second groove 102 and the core layer 120 may be isolated by the mask sidewall 240.

In this embodiment, after the second groove 102 is formed, a second dividing layer 320 is formed in the second groove 102, and the second dividing layer 320 divides the second groove 102 along the first direction, so that the second groove 102 can realize a smaller distance at the position of the second dividing layer 320.

Referring to fig. 27 to 28, fig. 28 is a cross-sectional view of fig. 27 at position AA, with the core layer 120 removed, forming a third recess 103; at least one of the third groove 103, the second groove 102 and the first groove 101 has a dividing layer formed therein, and the dividing layer divides the corresponding groove along the first direction.

The third groove 103 is used for defining the shape and position of the target pattern with the second groove 102 and the first groove 101. In this embodiment, the sacrificial layer 140 and the mask sidewall 240 are used to define the shape and position of the first groove 101, the core layer 120 is used to define the shape and position of the second groove 102, and the second groove 102 is formed in different steps, which is beneficial to reducing the difficulty of forming the first groove 101, the second groove 102, and the third groove 103, increasing the process window (for example, improving the optical proximity effect, alleviating the limitation of the photolithography resolution), and improving the precision of pattern transfer, thereby ensuring the pattern precision of the first groove 101, the second groove 102, and the third groove 103.

Moreover, a dividing layer is formed in at least one of the third groove 103, the second groove 102 and the first groove 101, and the dividing layer divides the corresponding grooves along the first direction, so that a smaller distance can be realized between the corresponding grooves at two sides of the dividing layer, accordingly, after the target layer below the third groove 103, the second groove 102 and the first groove 101 is patterned To form a target pattern, a smaller distance can be realized at the position of a Head To Head (HTH) of an adjacent target pattern, which is favorable for improving the layout design flexibility and freedom of the target pattern, and meets the requirement of the Pitch (Pitch) in the integrated circuit being continuously reduced.

In this embodiment, the third grooves 103, the second grooves 102, and the first grooves 101 extend along the first direction and are arranged at intervals along the second direction, and adjacent grooves are isolated by the mask sidewall 240, which is beneficial to meeting the designed minimum interval between adjacent grooves, and accordingly, after the target layer 100 below the patterned third grooves 103, the second grooves 102, and the first grooves 101 forms the target pattern, the designed minimum interval between adjacent target patterns is also easy to meet.

The process of removing the core layer 120 includes one or both of wet etching and dry etching.

As an example, the core layer 120 is removed using a wet etching process. In this embodiment, the etching solution of the wet etching process includes a TMAH solution (tetramethylammonium hydroxide solution), an SC1 solution, or an SC2 solution. Wherein SC1 solution refers to NH₄OH and H₂O₂The SC2 solution refers to HCl and H₂O₂The mixed solution of (1).

Specifically, in the present embodiment, the first groove 101 is formed with the first dividing layer 310 therein, and the first dividing layer 310 divides the first groove 101 in the first direction; a second dividing layer 320 is formed in the second groove 102, and the second dividing layer 320 divides the second groove 102 along a first direction; a third dividing layer 330 is formed in the third groove 103, and the third dividing layer 330 divides the third groove 103 in a first direction.

It should be noted that the position and number of the above division layers are only an example. In an actual process, the positions and the number of the dividing layers can be adjusted according to process requirements, for example: some grooves may not be provided with a dividing layer, and the same groove may be provided with a plurality of dividing layers.

Referring to fig. 29 and 20, fig. 30 is a cross-sectional view of fig. 29 at the position AA, and the target layer 100 under the third recess 103, the second recess 102 and the first recess 101 is patterned to form a target pattern 400 by using the dividing layer, the mask sidewall 240 and the filling layer 160 as masks.

As can be seen from the foregoing, the degree of freedom and flexibility in graphic design of the first groove 101, the second groove 102, and the third groove 103 are high, the graphic accuracy of the first groove 101, the second groove 102, and the third groove 103 can be guaranteed, the minimum design interval is easily satisfied between adjacent grooves, after the target layer 100 below the first groove 101, the second groove 102, and the third groove 103 is patterned to form the target graphic 400, the graphic quality and the graphic accuracy of the target graphic 400 can be correspondingly guaranteed, and the minimum design interval is easily satisfied between adjacent target graphics 400 along the second direction.

Moreover, smaller distances can be realized between the corresponding grooves on both sides of the division layer, and after the target pattern 400 is formed, the adjacent target patterns 400 can correspondingly realize smaller distances at the Head To Head (HTH) position, thereby being beneficial To improving the layout design flexibility and the degree of freedom of the target pattern 400 and meeting the requirement of continuously reducing the Pitch (Pitch) in the integrated circuit.

In this embodiment, the target layer 100 is a dielectric layer, and the dielectric layer under the first, second, and

third grooves

101, 102, and 103 is patterned to form an interconnection Trench (Trench) 40. Accordingly, the target pattern 400 is an interconnect slot 410. The interconnect trench 410 is used to provide space for forming interconnect lines.

Specifically, in this embodiment, the mask sidewall 240, the partition layer and the filling layer 160 are used as masks, and the hard mask material layer 115 under the first groove 101, the second groove 102 and the third groove 103 is patterned to form a hard mask layer 280; the dielectric layer is patterned using the hard mask layer 280 as a mask to form an interconnect trench 410.

Referring to fig. 31 and 32, fig. 32 is a cross-sectional view of fig. 31 at position AA, the method of forming further comprising: after the formation of the interconnection trenches 410, interconnection lines 420 are formed in the interconnection trenches 410.

In this embodiment, the interconnection groove 410 can achieve a smaller distance at the head-to-head position, and the interconnection line 420 can correspondingly achieve a smaller distance at the head-to-head position, thereby being beneficial to improving the wire connecting capability of the interconnection line 420 at the head-to-head position, and also being beneficial to improving the degree of freedom and flexibility of the layout design of the interconnection line 420; moreover, the spacing between the adjacent interconnection grooves 410 in the second direction is easy to satisfy the designed minimum spacing, and meanwhile, the pattern precision of the interconnection grooves 410 is high, which is correspondingly beneficial to make the spacing of the interconnection lines 420 in the second direction satisfy the designed minimum spacing and improve the pattern precision of the interconnection lines 420, thereby improving the performance of the semiconductor structure.

The interconnect lines 420 are used to electrically connect the semiconductor structure to external circuitry or other interconnect structures. In this embodiment, the interconnect 420 is made of copper. In other embodiments, the material of the interconnect line can also be a conductive material such as cobalt, tungsten, aluminum, or the like. In this embodiment, in the step of forming the interconnection line 420, the filling layer 160, the mask sidewall spacers 240, the dividing layer and the hard mask layer 280 are also removed, so as to prepare for the subsequent processes.

Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 25 and 26, fig. 26 is a cross-sectional view of fig. 25 at position AA showing a schematic structure of an embodiment of the semiconductor structure of the present invention.

The semiconductor structure includes: a substrate 200 including a target layer 100 for forming a target pattern; a core layer 120 disposed on the substrate 200, wherein the core layer 120 extends along a first direction (shown as an X direction in fig. 25) and is arranged at intervals along a second direction (shown as a Y direction in fig. 25), the second direction is perpendicular to the first direction, and the sidewalls of the core layer 1202 opposite to the second direction are a first sidewall 11 (shown in fig. 17) and a second sidewall 12 (shown in fig. 17), respectively; a filling layer 160 disposed on the substrate 200 exposed by the core layer 120, wherein a trench 30 (as shown in fig. 17) penetrating through a portion of the filling layer 160 is formed between adjacent core layers 120 in the second direction, and the trench 30 exposes the first sidewall 11 and is spaced apart from the second sidewall 12; the mask side walls 240 are positioned on the side walls of the trench 30 and between the side walls of the core layer 120 and the filling layer 160, and the mask side walls 240 positioned on the side walls of the trench 30 enclose a first groove 101; a second groove 102 penetrating the first groove 101 and the filling layer 160 between the mask sidewall 240 of the second sidewall 12; wherein the core layer 120 occupies a space for forming a third groove; and a division layer penetrating at least one of the core layer 120, the second groove 102, and the first groove 101 in the second direction, the division layer for dividing the corresponding groove in the first direction.

The core layer 120 occupies a space for forming a third groove, and the shape and position of the third groove are correspondingly defined by the core layer 120; the pattern and position of the first groove 101 are defined by the trench 30 and the mask sidewall 240, and the second groove 102 penetrates through the first groove 101 and the filling layer 160 located between the mask sidewall 240 of the second sidewall 12; therefore, in the present embodiment, the core layer 120, the trench 30 and the mask sidewall 240 respectively define the patterns and positions of the third groove and the first groove 101, and the second groove 102 is formed in different steps, which is beneficial to reducing the difficulty in forming the first groove 101, the second groove 102 and the third groove and increasing the process window (for example, improving the optical proximity effect and alleviating the limitation of the photolithography resolution), so as to improve the pattern design freedom and flexibility of the first groove 101, the second groove 102 and the third groove, ensure the pattern precision of the first groove 101, the second groove 102 and the third groove, and further, the adjacent grooves are isolated by the mask 240, which is beneficial to realizing the minimum design interval between the adjacent grooves, and is correspondingly beneficial to satisfying the minimum design interval between the adjacent target patterns.

In this embodiment, the semiconductor structure further includes the dividing layer, which penetrates through at least one of the core layer 120, the second groove 102 and the first groove 101 along the second direction, and the dividing layer is configured To divide the corresponding grooves along the first direction, so that a smaller distance can be achieved between the corresponding grooves on two sides of the dividing layer, and accordingly, after the target layer below the third groove, the second groove 102 and the first groove 101 is patterned To form the target pattern, a smaller distance can be achieved between adjacent target patterns at a position of a Head To Head (HTH), which is beneficial To improving flexibility and freedom of layout design of the target pattern, and meets a requirement of an integrated circuit that a Pitch (Pitch) is continuously reduced.

The substrate 200 is used to provide a platform for a process. The target layer 100 is a film layer to be patterned to form a target pattern. The target pattern may be a gate structure, an interconnection trench in a back-end process, a fin in a fin field effect transistor (FinFET), a channel stack in a Gate All Around (GAA) transistor or a fork gate transistor (forkheet), a Hard Mask (HM) layer, or the like.

In this embodiment, the target layer 100 is a dielectric layer. And patterning the dielectric layer, forming a plurality of interconnection grooves in the dielectric layer, and then forming interconnection lines in the interconnection grooves, wherein the dielectric layer is used for realizing the electrical isolation between the adjacent interconnection lines. Accordingly, in this embodiment, the target pattern is an interconnection trench, and the dielectric layer is an inter-metal dielectric (IMD) layer.

The core layer 120 is used to occupy a spatial position for forming the third groove.

In this embodiment, the core layer 120 is made of a material that is easy to remove, so as to reduce the difficulty of the subsequent process of removing the core layer 120 to form the third groove. The core layer 120 is a single-layer or multi-layer structure, and the material of the core layer 120 includes one or more of amorphous silicon, polysilicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride and silicon oxycarbonitride.

The filling layer 160 is used as a mask for the patterning target layer 100 together with the mask sidewall spacers 240 and the partition layer. The material of the filling layer 160 includes spin-on silicon oxide, metal oxide (e.g., titanium oxide), polysilicon, and amorphous silicon. In this embodiment, the material of the filling layer 160 is spin-on silicon oxide.

The sidewalls of the trenches 30 are used to provide support for forming the mask sidewall spacers 240. Accordingly, the trench 30 and the mask sidewall spacers 240 located on the sidewalls of the trench 30 are used to define the shape and position of the first recess 101.

The trench 30 exposes the first sidewall 11 of the core layer 120, so that the distance between the first groove 101 and the first sidewall 11 is the thickness of the mask sidewall 240, and the distance between the first groove 101 and the third groove is the thickness of the mask sidewall 240, thereby being beneficial to satisfying the designed minimum distance between the first groove 101 and the third groove.

The mask sidewall spacers 240 are used as a mask with the fill layer 160 and the partition layer for patterning the target layer 100. The mask sidewall 240 is also used to realize isolation between adjacent grooves, so that the embodiment easily realizes the designed minimum interval between adjacent grooves by adjusting the thickness of the mask sidewall 240.

In this embodiment, the mask sidewall 240 is made of a material having an etching selectivity with the materials of the core layer 120 and the substrate 200, and the material of the mask sidewall 240 includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, titanium nitride, silicon carbide, silicon oxycarbide, and amorphous silicon.

The second groove 102 is used to define the shape and position of the target pattern.

The first groove 101 and the second groove 102 each extend in a first direction and are aligned in a second direction.

The dividing layer serves to divide the corresponding groove in the first direction, thereby enabling the corresponding groove to achieve a smaller distance at the position of the dividing layer.

In this embodiment, the dividing layer includes a first dividing layer 310 located in the first groove 101; the first division layer 310 divides the first groove 101 in a first direction.

In this embodiment, the dividing layer includes a second dividing layer 320 located in the second groove 102; the second division layer 320 divides the second groove 102 in a first direction.

The second segmentation layer 320 is also used as a mask for subsequent patterning of the target layer 100. The second grooves 102 are divided by the second division layer 320 in the first direction, thereby advantageously enabling a smaller distance between the second grooves 102 in the first direction.

In this embodiment, the second division layer 320 is formed by the mask sidewall 240 with a sidewall in contact, and the material of the second division layer 320 is correspondingly the same as the material of the mask sidewall 240. The second division layer 320 is formed by the mask sidewall 240 with the sidewall in contact with each other, because the forming step of the second division layer 320 includes: after the filling layer 160 is formed and before the mask sidewall spacers 230 are formed, a second blocking groove is formed in the filling layer 160; in the step of forming the mask sidewall spacers 240, the mask sidewall spacers 240 are formed in the second blocking grooves, and the mask sidewall spacers 240 located in the second blocking grooves are in contact with each other and used as the second division layer 320.

In the present embodiment, the split layers include a third split layer 330 penetrating the core layer 120 in a second direction; the third division layer 330 divides the core layer 120 in a first direction.

Subsequently, the core layer 120 is removed to form a third groove, the third groove is provided with the third dividing layer 330, and the third dividing layer 330 divides the third groove along the first direction, so that a smaller distance can be realized between the third grooves at two sides of the third dividing layer 330, and accordingly, after the target layer 100 below the third groove, the second groove and the first groove is patterned to form the target pattern, a smaller distance can also be realized between adjacent target patterns at the head-to-head position.

In this embodiment, a third blocking groove 210 (shown in fig. 17) penetrating through the core layer 120 along the second direction is formed in the core layer 120; the mask sidewall 240 is located in the third blocking groove 210, and the mask sidewall 240 located in the third blocking groove 210 contacts with and serves as the third division layer 330. Therefore, in this embodiment, the material of the third division layer 330 is the same as the material of the mask sidewall 240.

In other embodiments, the material of the third divided layer is the same as the material of the core layer, and the third divided layer has dopant ions therein, the dopant ions being suitable for making the etching resistance of the third divided layer greater than that of the core layer. The third division layer is provided with doping ions for improving the etching resistance, so that the etching resistance of the third division layer is greater than that of the core layer, and in the subsequent step of removing the core layer to form the third groove, the core layer and the third division layer have a higher selection ratio, so that the third division layer can be reserved for dividing the third groove. The material of the third split layer includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, titanium nitride, silicon carbide, silicon oxycarbide, and amorphous silicon. The dopant ions include one or more of boron ions, phosphorous ions, and argon ions.

It should be noted that the position and number of the above division layers are only an example. In an actual process, the positions and the number of the division layers can be flexibly adjusted according to process requirements, for example: some grooves may not be provided with a dividing layer, and the same groove may be provided with a plurality of dividing layers.

The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate comprising a target layer for forming a target pattern;

forming core layers extending along a first direction and arranged at intervals along a second direction on the substrate, wherein the second direction is perpendicular to the first direction, and the opposite side walls of the core layers adjacent to each other in the second direction are respectively a first side wall and a second side wall;

forming a sacrificial side wall on the side wall of the core layer;

forming a sacrificial layer extending along a first direction on a part of the substrate between the adjacent sacrificial side walls, wherein the sacrificial layer covers the side walls of the sacrificial side walls on the first side walls and is spaced from the sacrificial side walls on the second side walls;

forming a filling layer on the base exposed by the core layer, the sacrificial side wall and the sacrificial layer;

removing the sacrificial layer and forming an opening in the filling layer;

removing the sacrificial side wall; the opening and the first side wall enclose a groove;

forming a mask side wall on the side wall of the groove, wherein the mask side wall is further filled between the core layer side wall and the filling layer, and the mask side wall positioned on the side wall of the groove is surrounded into a first groove;

forming a second groove which penetrates through the filling layer between the side wall of the groove and the mask side wall on the second side wall; removing the core layer to form a third groove;

a dividing layer is formed in at least one of the third groove, the second groove and the first groove, and the dividing layer divides the corresponding groove along the first direction;

and imaging the third groove, the second groove and the target layer below the first groove by taking the partition layer, the mask side wall and the filling layer as masks to form a target image.

2. The method of forming a semiconductor structure according to claim 1, wherein a first division layer is formed in the first groove;

forming the first division layer in the first groove after forming the first groove, before forming the second groove and removing the core layer.

3. The method of forming a semiconductor structure of claim 2, wherein the step of forming the first split layer comprises: forming a supporting layer covering the mask side wall, the core layer and the first groove on the filling layer; forming a first blocking groove extending in a second direction and crossing the first groove in the support layer; forming the first division layer in the first blocking groove; and removing the supporting layer.

4. The method according to claim 3, wherein the first blocking trench further spans the adjacent mask sidewall, core layer and filling layer along the second direction;

the step of forming the first partition layer in the first blocking groove includes: filling a dividing material layer in the first blocking groove, wherein the dividing material layer also covers the supporting layer; and removing the segmentation material layers on the support layer, the mask side wall, the core layer and the filling layer, and reserving part of the segmentation material layers in the first blocking groove to be used as the first segmentation layer.

5. The method of forming a semiconductor structure according to claim 1, wherein a second division layer is formed in the second groove;

in the step of forming the filling layer, the filling layer comprises a preset region located between the side wall of the sacrificial layer and the sacrificial side wall located on the second side wall, and is used for forming a second groove;

after the filling layer is formed and before the second groove is formed, forming a second division layer which penetrates through part of the filling layer of the preset area along a second direction, wherein the second division layer divides the filling layer of the preset area along a first direction.

6. The method of forming a semiconductor structure of claim 5, further comprising: after the filling layer is formed and before the mask side wall is formed, forming a second blocking groove penetrating through the filling layer of the preset area along a second direction;

the step of forming the second divided layer includes: in the step of forming the mask side wall, the mask side wall in the second blocking groove is in contact with the mask side wall filled in the second blocking groove and is used as the second division layer.

7. The method for forming a semiconductor structure according to claim 6, wherein the second blocking trench is formed after the sacrificial layer and the sacrificial sidewall are removed and before the mask sidewall is formed;

in the step of removing the sacrificial layer, a gap is formed between the side wall of the core layer and the filling layer;

the step of forming the second blocking groove includes: forming a pattern definition layer on the filling layer to cover the core layer, the pattern definition layer also filling the gaps and the trenches; forming a cut opening in the pattern definition layer crossing the filling layer, the trench, the core layer and the gap in a second direction; removing the filling layer exposed by the cutting opening by taking the pattern definition layer as a mask, and forming the second blocking groove in the filling layer of the preset area; and removing the graph definition layer.

8. The method of forming a semiconductor structure according to claim 1, wherein a third division layer is formed in the third groove;

after forming the core layer, before removing the core layer, forming the third divided layer penetrating the core layer in the second direction, the third divided layer dividing the core layer in the first direction.

9. The method of forming a semiconductor structure of claim 8, further comprising: after the core layer is formed and before the mask side wall is formed, forming a third blocking groove penetrating through the core layer along a second direction; the step of forming the third divided layer includes: in the step of forming the mask side wall, the mask side wall in the third blocking groove is in contact with the mask side wall, and the mask side wall in the third blocking groove is used as the third division layer;

alternatively, the first and second electrodes may be,

the step of forming the third divided layer includes: after the core layer is formed and before the core layer is removed, ion doping is performed on a part of the core layer, which is suitable for improving the etching resistance of the core layer, and the core layer doped with ions is used as the third division layer.

10. The method for forming a semiconductor structure according to claim 9, wherein the third blocking trench is formed after the sacrificial layer and the sacrificial sidewall are removed and before the mask sidewall is formed;

the step of forming the third blocking groove includes: forming a capping layer on the filling layer to cap the core layer, the capping layer further filling the gap and the trench; forming a division opening in the clad layer crossing the core layer, the trench, the filling layer and the gap in a second direction; and removing the core layer exposed by the segmentation openings by using the covering layer as a mask to form a third blocking groove penetrating through the core layer along a second direction.

11. The method of forming a semiconductor structure of claim 9, wherein the step of forming the third split layer comprises ion doping a portion of the core layer;

the core layer is made of one or more of amorphous silicon, polycrystalline silicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride and silicon oxycarbonitride; ions that ion-dope a portion of the core layer include one or more of boron ions, phosphorus ions, and argon ions.

12. The method of forming a semiconductor structure of claim 1, wherein the target layer is a dielectric layer; the target graph is an interconnection groove;

the method for forming the semiconductor structure further comprises the following steps: after forming the interconnection trench, an interconnection line is formed in the interconnection trench.

13. A semiconductor structure, comprising:

a substrate including a target layer for forming a target pattern;

the core layers are positioned on the substrate, extend along a first direction and are arranged at intervals along a second direction, the second direction is perpendicular to the first direction, and the side walls opposite to the core layers adjacent to each other in the second direction are a first side wall and a second side wall respectively;

the filling layer is positioned on the substrate exposed out of the core layers, a groove penetrating through part of the filling layer is formed between every two adjacent core layers in the second direction, and the groove is exposed out of the first side wall and is spaced from the second side wall;

the mask side walls are positioned on the side walls of the grooves and between the side walls of the core layer and the filling layer, and the mask side walls positioned on the side walls of the grooves are encircled to form a first groove;

the second groove penetrates through the first groove and the filling layer positioned between the mask side walls of the second side walls; wherein the core layer occupies a space for forming a third groove;

and a division layer penetrating at least one of the core layer, the second groove and the first groove in the second direction, the division layer dividing the corresponding groove in the first direction.

14. The semiconductor structure of claim 13, wherein the dividing layer comprises a first dividing layer located in the first recess; the first division layer divides the first groove in a first direction.

15. The semiconductor structure of claim 13, wherein the split layer comprises a second split layer located in the second recess; the second dividing layer divides the second groove in a first direction.

16. The semiconductor structure of claim 15, wherein the second split layer is comprised of mask sidewalls whose sidewalls are in contact.

17. The semiconductor structure of claim 13, wherein the split layers comprise a third split layer that penetrates the core layer in the second direction; the third divided layer divides the core layer in a first direction.

18. The semiconductor structure of claim 17, wherein the core layer has a third blocking groove formed therein that penetrates the core layer in the second direction; the mask side wall is positioned in the third blocking groove, and the mask side wall positioned in the third blocking groove is in contact with the mask side wall and is used as the third division layer;

or the material of the third division layer is the same as that of the core layer, and the third division layer has doping ions therein, wherein the doping ions are suitable for enabling the etching resistance of the third division layer to be greater than that of the core layer.

19. The semiconductor structure of claim 18, wherein the material of the third split layer is the same as the material of the core layer, and the third split layer has dopant ions therein; the material of the third segmentation layer comprises one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, titanium nitride, silicon carbide, silicon oxycarbide and amorphous silicon; the dopant ions include one or more of boron ions, phosphorous ions, and argon ions.

20. The semiconductor structure of claim 13, wherein the target layer is a dielectric layer; the target pattern is an interconnect slot.