WO2015169052A1 - 一种finfet制造方法 - Google Patents

一种finfet制造方法 Download PDF

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Publication number
WO2015169052A1
WO2015169052A1 PCT/CN2014/088572 CN2014088572W WO2015169052A1 WO 2015169052 A1 WO2015169052 A1 WO 2015169052A1 CN 2014088572 W CN2014088572 W CN 2014088572W WO 2015169052 A1 WO2015169052 A1 WO 2015169052A1
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fin
layer
forming
barrier layer
semiconductor substrate
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PCT/CN2014/088572
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English (en)
French (fr)
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刘云飞
尹海洲
张珂珂
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中国科学院微电子研究所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and in particular to a method of fabricating a FINFET.
  • the channel punch-through effect is a phenomenon in which the source junction of the field effect transistor is connected to the depletion region of the drain junction.
  • the potential/drain barrier is significantly reduced, and a large number of carriers are injected from the source to the channel, and drifts through the space-charge region between the source and the drain to form a large current;
  • the magnitude of this current will be limited by the space charge, which is the so-called space charge limited current.
  • This space charge limiting current is in parallel with the gate voltage controlled channel current, so channel passthrough will greatly increase the total current through the device; and in the case of channel punchthrough, even if the gate voltage is below the threshold voltage, the source - There will also be current flow through the drain.
  • This effect is an effect that may occur in small-sized field effect transistors, and as the channel width is further reduced, its influence on device characteristics is also becoming more and more significant.
  • the portion of the fin below the trench is typically heavily doped to suppress the channel punch-through effect.
  • the general doping method is to form a heavily doped region by ion implantation.
  • the depth of ion implantation is difficult to precisely control, and damage to the channel surface is caused.
  • a thin layer is usually formed on the surface of the channel. The oxide layer adds process complexity.
  • Another method of forming the through-barrier layer is side-scattering, that is, not directly implanting impurities into the bottom of the channel, but implanting the desired impurities into the isolation layers on both sides of the fin, by lateral scattering at the bottom of the channel. Pass through the barrier layer.
  • This method effectively reduces the defects and impurities introduced by the direct ion implantation in the channel, and improves the performance of the device.
  • the ion implantation energy and the dose required for forming the scattering are relatively large, this method is inevitable. Damage forms the dielectric properties of the isolation layer.
  • the present invention provides a FINFET fabrication method capable of effectively suppressing the punch-through current without affecting other characteristics of the device.
  • the manufacturing method provided by the present invention includes the following steps:
  • the height of the first fin depends on the difference between the predetermined height of the second fin to be formed and the height of the isolation layer; the height of the first fin is 30-50 nm, and the thickness is 10 ⁇ 30nm.
  • the material forming the mask layer is silicon nitride and/or silicon oxide.
  • the punch-through barrier layer is located at the bottom of the first fin, and a boundary thereof near the substrate is set to be located within the second fin to be formed.
  • step c the method of forming the through barrier layer is side scatter; the type of impurities forming the through barrier layer is the same as the substrate; and the impurity concentration of the through barrier layer is 1e17 cm -3 to 1e19 cm -3 .
  • the fins are etched twice, the first etching makes the fin height equal to the effective height of the channel, and the remaining portion of the silicon material is retained, and the silicon nitride is used as a mask to do it.
  • the impurity ions are implanted and annealed to form a punch-through barrier layer; the second etching causes the fins to reach an actual required height, and then forms an isolation layer, a source/drain region, and the like.
  • the present invention adopts a side-scattering method of doping ions to form a through-barrier layer while using a substrate material as a carrier for scattering impurities. And removing the portion of the material after forming the through-barrier layer to form the isolation layer, effectively solving the impurities and damage introduced into the isolation layer during lateral scattering, and greatly improving the device performance.
  • 1 to 6 are cross-sectional views showing respective stages of fabrication of a MOS device in accordance with an embodiment of the present invention
  • FIG. 7 is a three-dimensional perspective view of a FinFET according to an embodiment of the present invention after completion of fabrication
  • Embodiments of the present invention provide a method of fabricating a FINFET that effectively suppresses shoot-through current without affecting other characteristics of the device. Specifically, the method includes the following steps:
  • a semiconductor substrate 100 is provided, on the substrate forming a first fin 201;
  • the semiconductor substrate 100 is further etched by using the first fin 201 and the mask layer 202 as a mask to form a second fin 200, and the mask 202 is removed;
  • An isolation layer 400, a source/drain region, an interlayer dielectric layer 500, and a gate stack 600 are sequentially formed on the semiconductor substrate 100 and the second fin 200. Specifically forming a trench spacer on the semiconductor substrate From the structure, source and drain regions are formed on the second fin, and a gate stack and an interlayer dielectric layer are formed on the semiconductor substrate and the second fin.
  • the height of the first fin 201 is equal to the height difference between the second fin 200 and the isolation layer 400.
  • the height of the first fin 201 is 30-50 nm and the thickness is 10-30 nm.
  • the material forming the mask layer 202 is silicon nitride and/or silicon oxide.
  • the punch-through barrier layer 300 is located at the bottom of the first fin 201, and is located within the second fin 200 near the boundary of the substrate 100.
  • step c the method of forming the through-barrier layer 300 is lateral scattering; the type of impurities forming the through-barrier layer 300 is the same as that of the substrate; and the impurity concentration of the punch - through barrier layer 300 is 1e17 cm -3 to 1e19 cm - 3 .
  • the fins are etched twice, the first etching makes the fin height equal to the effective height of the channel, and the remaining portion of the silicon material is retained, and the silicon nitride is used as a mask to ionize it.
  • the implantation is performed and annealed to form a through-barrier layer; the second etching causes the fin to reach an actual required height, and then forms an isolation layer, a source/drain region, and the like.
  • the impurities and damage introduced into the isolation layer during side scatter are effectively solved, and the device performance is greatly improved.
  • first fins 201 are placed over substrate 100.
  • both substrate 100 and first fin 201 are comprised of silicon.
  • the first fin 201 is formed by epitaxially growing a semiconductor layer on the surface of the substrate 100 and etching the semiconductor layer.
  • the epitaxial growth method may be molecular beam epitaxy (MBE) or other methods, and the etching method may be dry Etching or dry/wet etching.
  • the first fin 201 has a height of 30 to 50 nm, and the bottom portion thereof is located at a position where the punch-through current is generated.
  • the mask layer 202 is covered on the surface of the first fin 201, as shown in FIG.
  • the function of the mask 202 is to protect the first fins 201 during subsequent ion implantation to avoid introducing impurities into the fins.
  • the material forming the mask 202 in this embodiment is silicon nitride, and the thickness thereof can be adjusted according to ions and energy injected by the particles, and is 20 to 60 nm.
  • ion implantation is performed, and impurities are implanted into the semiconductor substrate 100 not covered by the first fin 201. Since the fins of the FinFET are very thin, during the ion implantation process, the impurity ions incident on the substrates on both sides of the first fin can easily pass through the thermal motion to reach the substrate under the fin due to scattering.
  • the desired doping profile allows the via barrier to be formed where the through current is generated at the bottom of the trench without passing through the fins.
  • the particles forming the punch-through barrier layer 300 are As; for the P-type device, the program-through barrier layer 300 particles are B; and the impurity concentration of the punch - through barrier layer 300 is 1e17 cm -3 to 1e19 cm. -3 .
  • the formed through-barrier layer 300 is uniformly distributed under the first fin 201 as shown in FIG.
  • the first fin 201 is further etched by using the first fin 201 and the mask layer 202 as a mask to form a final second fin 200.
  • the specific etching method is the same as the method of forming the first fin 201 until the actually required fin height is reached. In this step, only the substrate region under the first fin 201, together with the punch-through barrier layer 300 therein, is retained, together with the first fin 201 to form the final second fin 200.
  • the formed second fin 200 still includes a punch-through barrier layer, and the distribution thereof is concentrated, and is located at a place where the through current is generated at the bottom of the channel, thereby effectively suppressing the punch-through current;
  • the scattering method forms a punch-through barrier layer, effectively avoiding the introduction of impurities and defects in the channel, and optimizing device performance.
  • a row isolation layer 400 is formed on the semiconductor structure.
  • a silicon nitride and buffered silicon dioxide pattern is first formed on the second fin 200 as a mask for trench etching.
  • a trench having a certain depth and a side wall angle is etched on the substrate 100.
  • a thin layer of silicon dioxide is then grown to round the apex of the trench and remove the damage introduced on the silicon surface during the etch.
  • the trench is filled after oxidation, and the filling medium may be silicon dioxide.
  • the surface of the semiconductor substrate is planarized using a CMP process to expose the mask layer 202 on the top of the second fin 200, and anisotropically etching is performed as a mask to expose the second fin 200.
  • a dummy gate structure is formed that is perpendicular to the second fin 200 and has a width equal to the channel length on the semiconductor structure fin.
  • the dummy gate stack may be a single layer or a plurality of layers.
  • the dummy gate stack may comprise a polymer material, amorphous silicon, polysilicon or TiN and may have a thickness of 10-100 nm.
  • the pseudo gate stack can be formed by processes such as thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like.
  • sidewalls are formed on the sidewalls of the gate stack for spacing the gates apart.
  • the sidewall spacers can be formed from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
  • the side walls can have a multi-layered structure. Side wall can It is formed by a deposition etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm or 80 nm.
  • source and drain regions are formed on both sides of the dummy gate stack.
  • the semiconductor structure is ion-implanted by using a dummy gate structure as a mask, and the isolation layer 400 serves as a protective layer for ion implantation to prevent damage on the surface of the fin when the impurity ions are incident on the second fin 200. Since the influence of silicon and silicon dioxide on the incident depth of the impurity during ion implantation is not large, after the ion implantation is completed, the heavy doping is formed at the second fin 200 and the isolation layer 400 which are not covered by the dummy gate structure. Area.
  • the semiconductor structure is annealed. Specifically, the annealing temperature is 950 ° C, and the annealing time is 15 to 30 minutes.
  • the second fin 200 is activated, and impurities in the source and drain regions are formed to form a uniform source/drain doping region.
  • the interlayer dielectric layer 500 is deposited and planarized in parallel to expose the dummy gate stack.
  • the interlayer dielectric layer 500 may be formed by CVD, high density plasma CVD, spin coating, or other suitable method.
  • the material of the interlayer dielectric layer 500 may be SiO 2 , carbon doped SiO 2 , BPSG, PSG, UGS, silicon oxynitride, low k material, or a combination thereof.
  • the thickness of the interlayer dielectric layer 500 may range from 40 nm to 150 nm, such as 80 nm, 100 nm, or 120 nm.
  • a planarization process is performed to expose the dummy gate stack and is flush with the interlayer dielectric layer 500 (the term "flush" in the present invention means that the height difference between the two is allowed in the process error. Within the scope).
  • the dummy gate stack is removed to form dummy gate vacancies exposing the surface of the isolation layer 400 beneath the dummy gate stack.
  • the dummy gate structure can be removed by dry etching.
  • the isolation layer 300 under the dummy gate vacancies is removed to expose the channel portion.
  • the dummy gate structure can be removed by wet etching and/or dry etching. In one embodiment, plasma etching is employed.
  • a gate structure 600 is formed in the dummy gate vacant. After the gate structure 600 includes the gate dielectric layer, the work function adjusting layer, and the gate metal layer gate structure 600, the semiconductor structure is as shown in FIG.
  • the above embodiment employs a back gate process to fabricate a FinFET, but is not limited to the embodiment, and the present invention is equally applicable to a gate first process.
  • the sidewall spacer is etched, a vacancy is formed in the interlayer dielectric layer above the gate and the source and drain regions, and the previous sidewall material is replaced by air, effectively reducing The dielectric constant of the material in the outer edge region is reduced, and the capacitive coupling effect between the source and drain regions and the gate is weakened, thereby effectively reducing parasitic capacitance and optimizing device performance.

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Abstract

一种FINFET的制造方法，包括：a.提供半导体衬底，在所述衬底上形成第一鳍片；b.在所述第一鳍片上覆盖掩膜层；c.在所述半导体衬底中形成穿通阻挡层；d.以第一鳍片和掩膜层为掩膜依次对所述通阻挡层和所述半导体衬底的一部分进行刻蚀，将所述第一鳍片扩展成第二鳍片，并去除掩膜；e.在所述半导体衬底上形成沟槽隔离结构，在第二鳍片上形成源漏区，在所述半导体衬底和第二鳍片上形成栅极叠层和层间介质层。采用侧向散射的方法形成穿通阻挡层，同时利用衬底材料作为散射杂质的载体，在形成穿通阻挡层之后形成隔离层，有效地解决了侧向散射时引入的杂质和损伤，极大地改善了器件性能。

Description

一种FINFET制造方法
本申请要求了2014年5月4日提交的、申请号为201410185412.7、发明名称为“一种FINFET制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及一种半导体器件制造方法，具体地，涉及一种FINFET制造方法。
技术背景
随着半导体器件的尺寸按比例缩小，出现了阈值电压随沟道长度减小而下降的问题，也即，在半导体器件中产生了短沟道效应。为了应对来自半导体涉及和制造方面的挑战，导致了鳍片场效应晶体管，即FinFET的发展。
沟道穿通效应(Channel punch-through effect)是场效应晶体管的源结与漏结的耗尽区相连通的一种现象。当沟道穿通，就使源/漏间的势垒显著降低，则从源往沟道即注入大量载流子，并漂移通过源-漏间的空间电荷区、形成一股很大的电流；此电流的大小将受到空间电荷的限制，是所谓空间电荷限制电流。这种空间电荷限制电流是与栅压控制的沟道电流相并联的，因此沟道穿通将使得通过器件的总电流大大增加；并且在沟道穿通情况下,即使栅电压低于阈值电压，源-漏间也会有电流通过。这种效应是在小尺寸场效应晶体管中有可能发生的一种效应，且随着沟道宽度的进一步减小，其对器件特性的影响也越来越显著。
在FinFET中，通常采用对沟道下方的鳍片部分进行重掺杂来抑制沟道穿通效应。目前通用的掺杂方法是离子注入形成所需重掺杂区，然而，离子注入的深度难以精确控制，同时会对沟道表面造成损伤，为了消除损伤，通常会在沟道表面形成一层薄氧化层，增加了工艺复杂度。
另一种形成穿通阻挡层的方法是侧向散射，即不直接向沟道底部注入杂质，而是向鳍片两侧的隔离层注入所需杂质，通过侧向散射在沟道底部形 成穿通阻挡层。这种方法有效的减小了直接离子注入在沟道中引入的缺陷和杂质，改善了器件的性能，然而，由于形成散射所需的离子注入能量和剂量都比较大，这种方法会不可避免的损伤形成隔离层的电介质特性。
发明内容
针对上述问题，本发明提供了一种FINFET制作方法，能有效的抑制穿通电流而不影响器件其他特性。具体地，本发明提供的制造方法包括以下步骤：
a.提供半导体衬底，在所述衬底上形成第一鳍片；
b.在所述第一鳍片上覆盖掩膜层；
c.在所述半导体衬底中形成穿通阻挡层；
d.以第一鳍片和掩膜层为掩膜依次对所述通阻挡层和所述半导体衬底的一部分进行刻蚀，将所述第一鳍片扩展成第二鳍片，并去除掩膜；
e.在所述半导体衬底上形成沟槽隔离结构，在第二鳍片上形成源漏区，在所述半导体衬底和第二鳍片上形成栅极叠层和层间介质层。
其中，在步骤a中，所述第一鳍片的高度取决于要形成的第二鳍片的预定高度与隔离层的高度差；所述第一鳍片的高度为30～50nm，厚度为10～30nm。
其中，在步骤b中，形成所述掩膜层的材料为氮化硅和/或氧化硅。其中，在步骤c中，所述穿通阻挡层位于第一鳍片底部，其靠近衬底的边界设定为位于要形成的第二鳍片之内。
其中，在步骤c中，形成穿通阻挡层的方法为侧向散射；形成所述穿通阻挡层的杂质类型与衬底相同；所述穿通阻挡层的杂质浓度为1e17cm-3～1e19cm-3。
根据本发明提供的FINFET制作方法，分两次刻蚀鳍片，第一次刻蚀使得鳍片高度等于沟道有效高度，保留其余部分的硅材料，以氮化硅为掩膜对其进行掺杂离子注入，并退火形成穿通阻挡层；第二次刻蚀使鳍片达到实际需要的高度，之后再形成隔离层、源漏区等部分。本发明采用掺杂离子的侧向散射的方法形成穿通阻挡层，同时利用衬底材料作为散射杂质的载体， 并在形成穿通阻挡层之后去除该部分材料而形成隔离层，有效地解决了侧向散射时引入隔离层的杂质和损伤，极大地改善了器件性能。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显：
图1～图6为根据本发明的一个具体实施方式的MOS器件各个制造阶段的剖面图；
图7为本发明的一个具体实施方式的FinFET的在制作完成后的三维立体图；
附图中相同或相似的附图标记代表相同或相似的部件。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明的实施例作详细描述。
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
本发明的实施例提供了一种FINFET制作方法，能有效的抑制穿通电流而不影响器件其他特性。具体地，该方法包括以下步骤：
a.提供半导体衬底100，在所述衬底上形成第一鳍片201；
b.在所述第一鳍片201上覆盖掩膜层202；
c.在所述半导体衬底100表中中形成穿通阻挡层300；
d.以第一鳍片201和掩膜层202为掩膜对所述半导体衬底100进行进一步刻蚀，形成第二鳍片200，并去除掩膜202；
e.在所述半导体衬底100和第二鳍片200上依次形成隔离层400、源漏区、层间介质层500和栅极叠层600。具体来说在所述半导体衬底上形成沟槽隔 离结构，在第二鳍片上形成源漏区，在所述半导体衬底和第二鳍片上形成栅极叠层和层间介质层。
其中，在步骤a中，所述第一鳍片201的高度等于第二鳍片200与隔离层400的高度差；所述第一鳍片201的高度为30～50nm，厚度为10～30nm。
其中，在步骤b中，形成所述掩膜层202的材料为氮化硅和/或氧化硅。其中，在步骤c中，所述穿通阻挡层300位于第一鳍片201底部，其靠近衬底100的边界位于第二鳍片200之内。
其中，在步骤c中，形成穿通阻挡层300的方法为侧向散射；形成所述穿通阻挡层300的杂质类型与衬底相同；所述穿通阻挡层300的杂质浓度为1e17cm-3～1e19cm-3。
根据本发明提供的FINFET制造方法，分两次刻蚀鳍片，第一次刻蚀使得鳍片高度等于沟道有效高度，保留其余部分的硅材料，以氮化硅为掩膜对其进行离子注入，并退火形成穿通阻挡层；第二次刻蚀使鳍片达到实际需要的高度，之后再形成隔离层、源漏区等部分。有效地解决了侧向散射时引入隔离层的杂质和损伤，极大地改善了器件性能。
下面结合附图对本发明的制作方法进行详细说明，包括以下步骤。需要说明的是，本发明各个实施例的附图仅是为了示意的目的，因此没有必要按比例绘制。
参见图1，首先制作位于衬底100上方的第一鳍片201。仅仅作为示例，衬底100和第一鳍片201都由硅组成。通过在衬底100表面外延生长半导体层并刻蚀该半导体层而形成第一鳍片201，所述外延生长方法可以是分子束外延法(MBE)或其他方法，所述刻蚀方法可以是干法刻蚀或干法/湿法刻蚀。第一鳍片201高度为30～50nm，其底部位于穿通电流产生的位置。
接下来，在所述第一鳍片201表面覆盖掩膜层202，如图2所示。掩膜202的作用是在接下来的离子注入中保护第一鳍片201，避免在鳍片中引入杂质。作为示例，本实施例中形成所述掩膜202的材料为氮化硅，其厚度可根据粒子注入的离子和能量调节，为20～60nm。
接下来，如图3所示，进行离子注入，在未被第一鳍片201覆盖的半导体衬底100中注入杂质。由于FinFET的鳍片很薄，在离子注入的过程中， 由于散射作用，射入第一鳍片两侧衬底中的杂质离子很容易的通过热运动到达鳍片下方的衬底中，形成所需要的掺杂分布，因此，不需要经过鳍片就可以在沟道底部穿通电流产生的地方形成穿通阻挡层。在本实施例中，对于N型器件，形成穿通阻挡层300的粒子为As；对于P型器件，程序穿通阻挡层300粒子为B；所述穿通阻挡层300的杂质浓度为1e17cm-3～1e19cm-3。形成的穿通阻挡层300均匀的分布在第一鳍片201下方，如图4所示。
接下来，如图5所示，以第一鳍片201和掩膜层202为掩膜，对第一鳍片201进行进一步刻蚀，形成最终的第二鳍片200。具体刻蚀方法与形成第一鳍片201的方法相同，直至达到实际需要的鳍片高度。在此步骤中，仅有位于第一鳍片201下方的衬底区域连同其中的穿通阻挡层300被保留了下来，与第一鳍片201一起形成了最终的第二鳍片200。经过上述步骤，完成刻蚀后，形成的第二鳍片200中依然包含穿通阻挡层，且其分布集中，位于沟道底部穿通电流产生的地方，有效的抑制了穿通电流；同时，采用侧向散射的方法形成穿通阻挡层，有效的避免了在沟道中引入杂质和缺陷，优化了器件性能。
接下来，如图6所示，在对所述半导体结构进上形成行隔离层400。优选地，首先在第二鳍片200上成氮化硅和缓冲二氧化硅图形，作为沟槽腐蚀的掩膜。接下来在衬底100上腐蚀出具有一定深度和侧墙角度的沟槽。然后生长一层薄二氧化硅，以圆滑沟槽的顶角并且去掉刻蚀过程中在硅表面引入的损伤。氧化之后进行沟槽填充，填充介质可以是二氧化硅。接下来使用CMP工艺对半导体衬底表面进行平坦化，露出第二鳍片200顶部的掩膜层202，并以其为掩膜进行各向异性刻蚀，露出第二鳍片200。
接下来，形成伪栅结构，所述伪栅结构与第二鳍片200垂直，其宽度等于所述半导体结构鳍片上的沟道长度。具体的，所述伪栅叠层可以是单层的，也可以是多层的。伪栅叠层可以包括聚合物材料、非晶硅、多晶硅或TiN，厚度可以为10-100nm。可以采用热氧化、化学气相沉积(CVD)、原子层沉积(ALD)等工艺来形成伪栅叠层。可选地，在栅极堆叠的侧壁上形成侧墙，用于将栅极隔开。侧墙可以由氮化硅、氧化硅、氮氧化硅、碳化硅及其组合，和/或其他合适的材料形成。侧墙可以具有多层结构。侧墙可以 通过包括沉积刻蚀工艺形成，其厚度范围可以是10nm-100nm，如30nm、50nm或80nm。
接下来在伪栅叠层两侧形成源漏区。具体的，以伪栅结构作为掩膜，对所述半导体结构进行离子注入，隔离层400作为离子注入的保护层，避免杂质离子射入第二鳍片200时在鳍片表面形成损伤。由于硅和二氧化硅对离子注入时杂质入射深度的影响差别不大，因此，离子注入完成之后，会在未被伪栅结构所覆盖的第二鳍片200和隔离层400处形成重掺杂区。接下来，对所述半导体结构进行退火，具体的，退火温度为950℃，退火时间为15～30分钟，激活第二鳍片200，源漏区的杂质，形成均匀的源漏掺杂区。
接下来，淀积层间介质层500，并并行平坦化，露出伪栅叠层。具体的，层间介质层500可以通过CVD、高密度等离子体CVD、旋涂或其他合适的方法形成。层间介质层500的材料可以采用包括SiO2、碳掺杂SiO2、BPSG、PSG、UGS、氮氧化硅、低k材料或其组合。层间介质层500的厚度范围可以是40nm-150nm，如80nm、100nm或120nm。接下来，执行平坦化处理，使伪栅叠层暴露出来，并与层间介质层500齐平(本发明中的术语“齐平”指的是两者之间的高度差在工艺误差允许的范围内)。
接下来，去除伪栅叠层，以形成伪栅空位，暴露出伪栅叠层下方的隔离层400表面。具体的，伪栅结构可以采用干刻除去。接下来，去除伪栅空位下方的隔离层300，露出沟道部分。具体的，伪栅结构可以采用湿刻和/或干刻除去。在一个实施例中，采用等离子体刻蚀。接下来，在伪栅空位中形成栅极结构600，栅极结构600包括栅介质层、功函数调节层和栅极金属层栅极结构600形成之后，半导体结构如图7所示。
上述实施例采用的是后栅工艺制作FinFET，但不限于所述实施例，本发明同样可适用于先栅工艺中。
根据本发明提供的FINFET结构，在形成层间介质层之后刻蚀掉侧墙，在栅极与源漏区上方的层间介质层中形成空位，用空气取代之前的侧墙材料，有效地减小了外部边缘区域材料的介电常数，同时削弱了源漏区与栅极之间的电容耦合效应，从而有效地减小了寄生电容，优化了器件性能。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、结构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易理解，对于目前已存在或者以后即将开发出的工艺、结构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、结构、制造、物质组成、手段、方法或步骤包含在其保护范围内。

Claims (8)

  1. 一种FINFET的制造方法，包括：
    a.提供半导体衬底(100)，在所述衬底上形成第一鳍片(201)；
    b.在所述第一鳍片(201)上覆盖掩膜层(202)；
    c.在所述半导体衬底(100)中形成穿通阻挡层(300)；
    d.以第一鳍片(201)和掩膜层(202)为掩膜依次对所述通阻挡层(300)和所述半导体衬底(100)的一部分进行刻蚀，将所述第一鳍片(201)扩展成第二鳍片(200)，并去除掩膜(202)；
    e.在所述半导体衬底(100)上形成沟槽隔离结构(400)，在第二鳍片(200)上形成源漏区，在所述半导体衬底和第二鳍片上形成栅极叠层和层间介质层。
  2. 根据权利要求1所述的制造方法，其特征在于，在步骤a中，所述第一鳍片(201)的高度取决于要形成的第二鳍片(200)的预定高度与隔离层(400)的高度差。
  3. 根据权利要求2所述的制造方法，其特征在于，在步骤a中，所述第一鳍片(201)的高度为30～50nm，厚度为10～30nm。
  4. 根据权利要求1所述的制造方法，其特征在于，在步骤b中，形成所述掩膜层(202)的材料为氮化硅和/或氧化硅。
  5. 根据权利要求1所述的制造方法，其特征在于，在步骤c中形成的所述穿通阻挡层(300)位于第一鳍片(201)底部，其靠近衬底(100)的边界设定为位于要形成的第二鳍片(200)之内。
  6. 根据权利要求1所述的制造方法，其特征在于，在步骤c中，形成穿通阻挡层(300)的方法为掺杂离子的侧向散射。
  7. 根据权利要求1或6所述的制造方法，其特征在于，在步骤c中，形成所述穿通阻挡层(300)的杂质类型与衬底相同。
  8. 根据权利要求1或6所述的制造方法，其特征在于，在步骤c中，所述穿通阻挡层(300)的杂质浓度为1e17cm-3～1e19cm-3。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447603A (zh) * 2019-08-30 2021-03-05 长鑫存储技术有限公司 半导体存储器的形成方法
CN113851529A (zh) * 2021-09-07 2021-12-28 上海集成电路装备材料产业创新中心有限公司 鳍式半导体器件及其制备方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107045982B (zh) * 2016-02-05 2020-08-07 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
CN106229258A (zh) * 2016-08-22 2016-12-14 曹蕊 一种FinFET制造方法及对应的FinFET结构
CN114446869B (zh) * 2020-11-06 2024-06-07 长鑫存储技术有限公司 半导体结构的形成方法及半导体结构
CN113571418B (zh) * 2021-05-31 2024-03-08 上海华力集成电路制造有限公司 一种FinFET的超级阱形成方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
CN102347349A (zh) * 2010-07-28 2012-02-08 中国科学院微电子研究所 半导体结构及其制作方法
CN103107089A (zh) * 2011-11-14 2013-05-15 联华电子股份有限公司 非平面晶体管的制作方法
CN103531477A (zh) * 2012-07-05 2014-01-22 台湾积体电路制造股份有限公司 具有位于下方的嵌入式抗穿通层的FinFET方法和结构
US20140117462A1 (en) * 2012-10-31 2014-05-01 International Business Machines Corporation Bulk finfet with punchthrough stopper region and method of fabrication

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102629627B (zh) * 2012-04-16 2014-08-06 清华大学 异质栅隧穿晶体管的形成方法
CN103390644B (zh) * 2012-05-08 2017-07-11 中国科学院微电子研究所 半导体器件及其制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
CN102347349A (zh) * 2010-07-28 2012-02-08 中国科学院微电子研究所 半导体结构及其制作方法
CN103107089A (zh) * 2011-11-14 2013-05-15 联华电子股份有限公司 非平面晶体管的制作方法
CN103531477A (zh) * 2012-07-05 2014-01-22 台湾积体电路制造股份有限公司 具有位于下方的嵌入式抗穿通层的FinFET方法和结构
US20140117462A1 (en) * 2012-10-31 2014-05-01 International Business Machines Corporation Bulk finfet with punchthrough stopper region and method of fabrication

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447603A (zh) * 2019-08-30 2021-03-05 长鑫存储技术有限公司 半导体存储器的形成方法
CN112447603B (zh) * 2019-08-30 2023-12-19 长鑫存储技术有限公司 半导体存储器的形成方法
CN113851529A (zh) * 2021-09-07 2021-12-28 上海集成电路装备材料产业创新中心有限公司 鳍式半导体器件及其制备方法

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