CN103632972A - 一种半导体结构及其制造方法 - Google Patents
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Abstract
本发明提供一种半导体结构的制造方法,该方法包括以下步骤:提供一个衬底,在所述衬底上形成栅堆叠,并在所述衬底之中形成源/漏区;刻蚀所述源/漏区,以形成沟槽;在刻蚀后的所述源/漏区的表面上形成接触层;在所述沟槽内形成应力产生材料层;沉积层间介质层,并形成与所述应力产生材料相接触的接触塞。相应地,本发明还提供一种半导体结构。本发明通过刻蚀源/漏区形成沟槽,以增加所述源/漏区暴露的区域,然后在所述源/漏区的表面上形成接触层,并在所述沟槽内填充应力产生材料,在有效地减小了源/漏区与接触层之间接触电阻的同时,还向沟道中引入了应力,改善了沟道中载流子的迁移率,从而提高了半导体结构的性能。
Description
技术领域
本发明涉及半导体制造技术,尤其涉及一种半导体结构及其制造方法。
背景技术
在现有技术中,常规半导体结构的制造方法如下(参考图1,图1为现有技术中半导体结构的剖面示意图):提供一个具有栅堆叠的衬底100,所述栅堆叠包括栅介质层210、金属栅极220以及侧墙240;在衬底100上、栅堆叠两侧形成源/漏区110;在所述源/漏区110的表面上形成接触层111(如金属硅化物层);沉积层间介质层300以覆盖所述源/漏区110以及栅堆叠;刻蚀所述层间介质层300至暴露所述源/漏区110以形成接触孔310或者接触沟310(a);在所述接触孔310或者接触沟310(a)内填充接触金属310,形成孔状接触塞(参考图1(a),图1(a)为根据图1示出的具有孔状接触塞的半导体结构的俯视示意图)或者沟状接触塞(参考图1(b),图1(b)为根据图1示出的具有沟状接触塞的半导体结构的俯视示意图)。由于在接触塞与源/漏区110之间存在接触层112,所以有利于减小源/漏区110的接触电阻。
但是,现有技术仅仅是通过在源/漏区的表面上形成接触层以提高半导体结构的性能,而没有在此基础上进一步通过向沟道引入应力以调整和提高半导体器件的性能。
因此,如何既可以减小源/漏区的接触电阻,又可以向沟道中引入应力,改善沟道中载流子的迁移率,从而进一步提高半导体结构的性能,就成了亟待解决的问题。
发明内容
本发明的目的是提供一种半导体结构及其制造方法,不但利于减小源/漏区与接触层之间的接触电阻,还可以提高沟道中的应力,以改善沟道中载流子的迁移率。
根据本发明的一个方面,提供一种半导体结构的制造方法,该方法包括以下步骤:
a)提供一个衬底,在所述衬底上形成栅堆叠,并在所述衬底之中形成源/漏区;
b)刻蚀所述源/漏区,以形成沟槽;
c)在刻蚀后的所述源/漏区的表面上形成接触层;
d)在所述沟槽内形成应力产生材料层;
e)沉积层间介质层,并形成与所述应力产生材料相接触的接触塞。
本发明另一方面还提出一种半导体结构,包括衬底、栅堆叠、源/漏区、接触层、层间介质层以及接触塞,其中:
所述栅堆叠形成于所述衬底之上;
所述源/漏区形成于所述衬底之中、位于所述栅堆叠两侧;
所述接触层位于所述源/漏区的表面上;
所述层间介质层覆盖所述源/漏区以及栅堆叠;
存在应力产生材料层,嵌于所述源/漏区之中,且形成于所述接触层之上;以及
所述接触塞嵌于所述层间介质层内并与所述应力产生材料层电连接。
与现有技术相比,本发明具有以下优点:
通过刻蚀源/漏区形成沟槽,以增加所述源/漏区暴露的区域,然后在所述源/漏区的表面上形成接触层,并在所述沟槽内填充应力产生材料,在有效地减小了源/漏区与接触层之间接触电阻的同时,还向沟道中引入了应力,改善了沟道中载流子的迁移率,从而提高了半导体结构的性能。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述,本发明的其它特征、目的和优点将会变得更明显:
图1为现有技术中半导体结构的剖面示意图;
图1(a)为根据图1示出的具有孔状接触塞的半导体结构的俯视示意图;
图1(b)为根据图1示出的具有沟状接触塞的半导体结构的俯视示意图;
图2为根据本发明的半导体结构制造方法的流程图;
图3至图12为根据本发明的一个实施例按照图2所示流程制造半导体结构的各个阶段的剖面示意图。
图3(a)至图12(a)为根据图3至图12示出的半导体结构的各个阶段的俯视示意图。
附图中相同或相似的附图标记代表相同或相似的部件。
具体实施方式
下面详细描述本发明的实施例,所述实施例的示例在附图中示出,其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的,仅用于解释本发明,而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开,下文中对特定例子的部件和设置进行描述。当然,它们仅仅为示例,并且目的不在于限制本发明。此外,本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的,其本身不指示所讨论各种实施例和/或设置之间的关系。此外,本发明提供了的各种特定的工艺和材料的例子,但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。另外,以下描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例,也可以包括另外的特征形成在第一和第二特征之间的实施例,这样第一和第二特征可能不是直接接触。应当注意,在附图中所图示的部件不一定按比例绘制。本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本发明。
图2为根据本发明的半导体结构制造方法的流程图,图3至图12为根据本发明的一个实施例按照图2所示流程制造半导体结构的各个阶段的剖面示意图,图3(a)至图12(a)为根据图3至图12示出的半导体结构的各个阶段的俯视示意图。其中,图3至图12所示的半导体结构的剖面示意图与图3(a)至图12(a)所示的半导体结构的俯视示意图相结合,利于更加清晰地示出各个阶段的半导体结构。下面,将结合图3至图12、以及图3(a)至图12(a)对图2中形成半导体结构的方法进行具体地描述。需要说明的是,本发明实施例的附图仅是为了示意的目的,因此没有必要按比例绘制。
参考图2、图3以及图3(a),在步骤S101中,首先提供一个衬底100,在所述衬底100上形成栅堆叠,然后在衬底100中形成源/漏区110。
在本实施例中,衬底100包括硅衬底(例如晶片)。根据现有技术公知的设计要求(例如P型衬底或者N型衬底),所述衬底100可以包括各种掺杂配置。在其他实施例中,衬底100可以包括其他基本半导体,例如锗。或者,衬底100可以包括化合物半导体,例如碳化硅、砷化镓、砷化铟或者磷化铟。或者,所述衬底100还可以为绝缘体上硅(SOI)。特别地,可以在衬底100中形成隔离区,例如浅沟槽隔离(STI)结构120,以便电隔离连续的半导体结构。
在形成源/漏区110之前,还需形成栅堆叠。所述栅堆叠形成于所述衬底100之上,其包括栅介质层210以及金属栅极220。在形成所述栅堆叠时,首先在衬底100上形成所述栅介质层210,所述栅介质层210的材料可以是氧化硅、氮化硅及其组合形成,也可以是高K介质,例如,HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合;而后,在所述栅介质层210上形成金属栅极220,可以通过沉积TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax中的一种或其组合来形成;特别地,可以通过沉积-刻蚀工艺在栅堆叠的侧壁上形成侧墙240,用于将栅堆叠隔开。侧墙240可以由氮化硅、氧化硅、氮氧化硅、碳化硅、及其组合,和/或其他合适的材料形成。侧墙240可以具有多层结构。在其他实施例中,所述栅堆叠可以包括栅介质层以及伪栅极,其中伪栅极可以通过沉积例如Poly-Si、Poly-SiGe、非晶硅和/或氧化物而形成于所述栅介质层之上。在后续的替代栅工艺中,伪栅极被去除,然后形成金属栅极。
接着,源/漏区110可以通过向衬底100中注入P型或者N型掺杂物或杂质而形成,例如,对于PMOS来说,源/漏区110可以是P型掺杂的SiGe,对于NMOS来说,源/漏区110可以是N掺杂的Si。源/漏区110可以由包括光刻、离子注入、扩散和/或其他合适工艺的方法形成。然后,对所述半导体结构进行退火,以激活源/漏区110中的掺杂,退火可以采用包括快速退火、尖峰退火等其他合适的方法形成。在另一个实施例中,源/漏区110可以是通过选择性生长所形成的提升的源/漏极结构,其外延部分的顶部高于栅堆叠的底部(本文件内,栅堆叠底部意指栅堆叠与衬底100的交界线)。
参考图2、图4以及图4(a),在步骤S102中,刻蚀所述源/漏区110,以形成沟槽。具体地,可以通过湿法刻蚀和/或干法刻蚀的方式,刻蚀所述源/漏区110以形成具有底部以及侧壁的孔状沟槽111。与未刻蚀前的所述源/漏区110相比,刻蚀后的所述源/漏区110所暴露的区域更大,从而可以增大后续工艺中所形成的接触层的面积,有效地减小源/漏区110与接触层之间的接触电阻。湿法刻蚀工艺包括四甲基氢氧化铵(TMAH)、氢氧化钾(KOH)或者其他合适刻蚀的溶液;干法刻蚀工艺包括六氟化硫(SF6)、溴化氢(HBr)、碘化氢(HI)、氯、氩、氦及其组合,和/或其他合适的材料。
优选地,还可以利用自组装嵌段共聚物在所述源/漏区110形成多条线状沟槽111(a),进一步增加所述源/漏区110的暴露区域,参考图5以及图5(a)。利用自组装嵌段共聚物在所述源/漏区110形成多条线状沟槽111(a)的步骤如下:首先在衬底100上形成自组装嵌段共聚物层,所述嵌段共聚物层包括两种彼此不能融合的第一嵌段共聚物组分A和第二嵌段共聚物组分B;接着,对半导体结构进行退火,以实现第一嵌段共聚物组分A和第二嵌段共聚物组分B的微相隔离,从而在所述衬底100上形成具有多条线状结构的图案层作为硬掩膜;选择性地去除第一嵌段共聚物组分A或第二嵌段共聚物组分B,未被去除的嵌段共聚物组分将构成周期性的多条凹凸图案;然后,以所述凹凸图案为掩膜选择性地刻蚀衬底100,在所述源/漏区110内形成周期性的线状沟槽111(a);最后,去除作为掩膜的凹凸图案。其中,嵌段共聚物优选是具有A-B分子式的线性双嵌段共聚物,可以从聚苯乙烯-嵌段-聚甲基丙烯酸甲酯(PS-b-PMMA)、聚环氧乙烷-嵌段-聚异戊二烯(PEO-b-PI)、聚环氧乙烷-嵌段-聚丁二烯(PEO-b-PBD)、聚环氧乙烷-嵌段-聚苯乙烯(PEO-b-PS)、聚环氧乙烷-嵌段-聚甲基丙烯酸甲酯(PEO-b-PMMA)、聚环氧乙烷-嵌段-聚乙基乙烯(PEO-b-PEE)、聚苯乙烯-嵌段-聚乙烯基吡啶(PS-b-PVP)、聚苯乙烯-嵌段-聚异戊二烯(PS-b-PI)、聚苯乙烯-嵌段-聚丁二烯(PS-b-PBD)、聚苯乙烯-嵌段-聚茂铁二甲基硅烷(PS-b-PFS)、聚丁二烯-嵌段-聚乙烯基吡啶(PBD-b-PVP)和聚异戊二烯-嵌段-聚甲基丙烯酸甲酯(PI-b-PMMA)中进行选择。
在其他实施例中,沟槽不限于上述孔状沟槽111,以及周期性的线状沟槽111(a),还可以为其他任何适合的形状,比如,图6以及图6(a)中随源/漏区的形状深度逐步递增的平行线状沟槽111(b)。
参考图2、图7以及图7(a),在步骤S103中,在刻蚀后的所述源/漏区110的表面上形成接触层112。其中,在本实施例中,衬底100为硅衬底,在刻蚀后的所述源/漏区110的表面上形成的接触层为金属硅化物层,下文中将以金属硅化物层来表示接触层。
首先,沉积一层金属层覆盖具有孔状沟槽111的源/漏区110以及栅堆叠;接着对该半导体结构进行退火,使所述金属层与源/漏区110的硅发生反应;退火后在源/漏区110的表面上形成金属硅化物层112;最后,通过选择性刻蚀的方式去除未参加反应形成金属硅化物层所残留的金属层。
参考图2、图9以及图9(a),在步骤S104中,在所述沟槽内形成应力产生材料层。具体地,为了仅仅在源/漏区110的沟槽内形成应力产生材料层,例如可以选择性原子层沉积(ALD)的方法来实现,在所述孔状沟槽111内形成应力产生材料层113,所述应力产生材料层113位于所述金属硅化物层112之上。所述应力产生材料层113的材料优选具有良好的导电性,例如能够产生应力的金属材料。其中,根据半导体结构类型的不同,形成不同的应力产生材料层。对于P型的半导体结构,所述应力产生材料层优选包括Ta、Zr中的一种或者其任意组合,既具有良好的导电性,又可以向源极和漏极之间的沟道施加压应力,提高沟道中空穴的迁移率;对于N型的半导体衬底,所述应力产生材料层优选包括Zr、Cr、Al中的一种或者其任意组合,既具有良好的导电性,又可以向源极与漏极之间的沟道施加拉应力,提高沟道中电子的迁移率。
参考图2、图11以及图11(a),在步骤S105中,沉积层间介质层300,并形成接触塞。
沉积层间介质层300以覆盖衬底100以及栅堆叠,其中,所述层间介质层300可以通过化学气相沉淀(CVD)、高密度等离子体CVD、旋涂和/或其他合适的工艺等方法形成。所述层间介质层300的材料可以包括氧化硅(USG)、掺杂的氧化硅(如氟硅玻璃、硼硅玻璃、磷硅玻璃、硼磷硅玻璃)、低k电介质材料(如黑钻石、coral等)中的一种或其组合。所述层间介质层300可以具有多层结构。
接着,通过例如光刻、干法刻蚀或湿法刻蚀工艺,刻蚀所述层间介质层300至暴露应力产生材料层113以形成接触孔;然后,在所述接触孔中填充接触金属310形成接触塞,所述接触塞的底部与所述应力产生材料层113电连接,其中,所述接触金属可以是W、Cu、TiAl、Al等金属或合金。
形成接触塞后,对所述接触塞进行化学机械研磨(CMP)平坦化处理,使接触塞的上表面与金属栅极220的上表面齐平(本文件内,术语“齐平”意指两者之间的高度差在工艺误差允许的范围内)。
参考图8、图10、图12以及图8(a)、图10(a)、图12(a),对于刻蚀源/漏区110后形成多条线性沟槽111(a)的半导体结构,采用与上述相同的方法在所述多条线性沟槽111(a)的表面上形成金属硅化物层112(a),然后在所述多条线性沟槽111(a)内形成应力产生材料层113(a),最后,沉积层间介质层300,并形成接触塞,所述接触塞的底部与所述应力产生材料层113(a)电连接。具体形成过程在此不再赘述。
随后按照常规半导体制造工艺的步骤完成该半导体结构的制造。
在上述步骤完成后,金属硅化物层形成于刻蚀后源/漏区110的表面上,由于刻蚀后的所述源/漏区110的暴露区域大于刻蚀前的所述源/漏区110的暴露区域,所以可以有效地增加源/漏区110与金属硅化物层之间的接触面积,从而减小源/漏区110与金属硅化物层之间的接触电阻,提高该半导体结构的性能。此外,在刻蚀源/漏区110所形成的沟槽内填充应力产生材料,形成应力产生材料层,可以向源极与漏极之间的沟道施加拉应力或者压应力,提高沟道中载流子的迁移率,从而进一步改善该半导体结构的性能。
参考图11以及图11(a),本发明还提供了一种半导体结构,该半导体结构包括衬底100、栅堆叠、源/漏区110、金属硅化物层112、层间介质层300以及接触塞,其中:所述栅堆叠形成于所述衬底100之上,其包括栅介质层210和金属栅极220;所述源/漏区110形成于所述衬底100之中、位于所述栅堆叠两侧;所述金属硅化物层112位于所述源/漏区110的表面上;所述层间介质层300覆盖所述源/漏区110以及栅堆叠;所述源/漏区110中形成孔状沟槽111;存在应力产生材料层113,嵌于所述源/漏区110中的孔状沟槽111内(参考图7),且形成于所述金属硅化物层112之上,其中,对于P型的半导体衬底,所述应力产生材料层113优选包括Ta、Zr中的一种或者其任意组合,既具有良好的导电性,又可以向源极和漏极之间的沟道施加压应力,提高沟道中空穴的迁移率;对于N型的半导体衬底,所述应力产生材料层113优选包括Zr、Cr、Al中的一种或者其任意组合,既具有良好的导电性,又可以向源极与漏极之间的沟道施加拉应力,提高沟道中电子的迁移率。所述接触塞包括嵌于所述层间介质层300内的接触金属310,且所述接触塞底部与所述应力产生材料层113电连接。
优选地,源/漏区110中的沟槽不限于孔状沟槽111,还可以是多条线状沟槽111(a)(参考图8),金属硅化物层112(a)形成于所述多条线状沟槽111(a)的表面上,应力产生材料层113(a)嵌于所述多条线状沟槽111(a)内,参考图12以及图12(a)。如图所示,与孔状沟槽111相比,所述多条线状沟槽111(a)具有更大的表面积,从而进一步增大了源/漏区110与金属硅化物层112(a)之间的接触面积,有效地减小了源/漏区110与金属硅化物层112(a)之间的接触电阻,提高该半导体结构的性能。在其他实施例中,源/漏区110中的沟槽也可以为其他任何适合的形状。
可选地,源/漏区110可以是通过选择性生长所形成的提升的源/漏极结构,其外延部分的顶部高于栅堆叠的底部。
其中,对半导体结构各实施例中各部分的结构组成、材料及形成方法等均可与前述半导体结构形成方法实施例中描述的相同,不再赘述。虽然关于示例实施例及其优点已经详细说明,应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下,可以对这些实施例进行各种变化、替换和修改。对于其他例子,本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时,工艺步骤的次序可以变化。
此外,本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容,作为本领域的普通技术人员将容易地理解,对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤,其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果,依照本发明可以对它们进行应用。因此,本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。
Claims (15)
1.一种半导体结构的制造方法,该方法包括以下步骤:
a)提供一个衬底(100),在所述衬底(100)上形成栅堆叠,并在所述衬底(100)之中形成源/漏区(110);
b)刻蚀所述源/漏区(110),以形成沟槽;
c)在刻蚀后的所述源/漏区(110)的表面上形成接触层(112);
d)在所述沟槽内形成应力产生材料层(113);
e)沉积层间介质层(300),并形成与所述应力产生材料相接触的接触塞。
2.根据权利要求1所述的制造方法,其中:
所述沟槽包括孔状沟槽(111)或者多条线状沟槽(111(a))。
3.根据权利要求2所述的制造方法,其中:
通过自组装嵌段共聚物作为硬掩膜在所述源/漏区(110)之上形成多条线状图案层;
以所述图案层为掩膜刻蚀所述源/漏区(110)形成所述多条线状沟槽(111(a))。
4.根据权利要求1所述的制造方法,其中:
通过选择性原子层沉积的方法在所述沟槽内形成所述应力产生材料层。
5.根据权利要求1或4所述的制造方法,其中:
所述应力产生材料层包括在N型半导体衬底中采用的产生拉应力的导电材料或者在P型半导体衬底中采用的产生压应力的导电材料。
6.根据权利要求5所述的制造方法,其中:
所述拉应力产生材料包括Zr、Cr、Al中的一种或者任意组合。
7.根据权利要求5所述的制造方法,其中:
所述压应力产生材料包括Ta、Zr中的一种或者任意组合。
8.根据权利要求1所述的制造方法,其中所述源/漏区(110)为提升的源/漏区。
9.根据权利要求3所述的制造方法,其中自组装嵌段共聚物的材料选自聚苯乙烯-嵌段-聚甲基丙烯酸甲酯(PS-b-PMMA)、聚环氧乙烷-嵌段-聚异戊二烯(PEO-b-PI)、聚环氧乙烷-嵌段-聚丁二烯(PEO-b-PBD)、聚环氧乙烷-嵌段-聚苯乙烯(PEO-b-PS)、聚环氧乙烷-嵌段-聚甲基丙烯酸甲酯(PEO-b-PMMA)、聚环氧乙烷-嵌段-聚乙基乙烯(PEO-b-PEE)、聚苯乙烯-嵌段-聚乙烯基吡啶(PS-b-PVP)、聚苯乙烯-嵌段-聚异戊二烯(PS-b-PI)、聚苯乙烯-嵌段-聚丁二烯(PS-b-PBD)、聚苯乙烯-嵌段-聚茂铁二甲基硅烷(PS-b-PFS)、聚丁二烯-嵌段-聚乙烯基吡啶(PBD-b-PVP)和聚异戊二烯-嵌段-聚甲基丙烯酸甲酯(PI-b-PMMA)之一或其组合。
10.一种半导体结构,该半导体结构包括衬底(100)、栅堆叠、源/漏区(110)、接触层(112)、层间介质层(300)以及接触塞,其中,所述栅堆叠形成于所述衬底(100)之上,所述源/漏区(110)形成于所述衬底(100)之中、位于所述栅堆叠两侧,所述接触层(112)位于所述源/漏区(110)的表面上,所述层间介质层(300)覆盖所述源/漏区(110)以及栅堆叠,其特征在于:
存在应力产生材料层(113),嵌于所述源/漏区(110)之中,且形成于所述接触层(112)之上;以及
所述接触塞嵌于所述层间介质层(300)内并与所述应力产生材料层电连接。
11.根据权利要求10所述的半导体结构,其中:
所述应力产生材料层(310)嵌于所述源/漏区(110)中的沟槽内,所述沟槽包括孔状沟槽(111)或者多条线状沟槽(111(a))。
12.根据权利要求10所述的半导体结构,其中:
所述应力产生材料层包括在N型半导体衬底中采用的产生拉应力的导电材料或者在P型半导体衬底中采用的产生压应力的导电材料。
13.根据权利要求12所述的半导体结构,其中:
所述拉应力产生材料包括Zr、Cr、Al中的一种或者任意组合。
14.根据权利要求12所述的半导体结构,其中:
所述压应力产生材料包括Ta、Zr中的一种或者任意组合。
15.根据权利要求10所述的半导体结构,其中所述源/漏区(110)为提升的源/漏区。
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CN105336717A (zh) * | 2014-07-14 | 2016-02-17 | 北大方正集团有限公司 | 一种引线孔、其制作方法、晶体管及cmos晶体管 |
CN106784007A (zh) * | 2016-12-30 | 2017-05-31 | 苏州通富超威半导体有限公司 | 一种载流子增强型mos结构 |
CN107731740A (zh) * | 2016-08-12 | 2018-02-23 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN108231564A (zh) * | 2016-12-21 | 2018-06-29 | Imec 非营利协会 | 半导体器件中的触点 |
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