CN106784007B - 一种载流子增强型mos结构 - Google Patents
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- 239000000758 substrate Substances 0.000 claims abstract description 8
- MEFBJEMVZONFCJ-UHFFFAOYSA-N molybdate Chemical compound [O-][Mo]([O-])(=O)=O MEFBJEMVZONFCJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052691 Erbium Inorganic materials 0.000 claims description 2
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 claims description 2
- 230000003014 reinforcing effect Effects 0.000 claims description 2
- 229910052727 yttrium Inorganic materials 0.000 claims description 2
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical group [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims description 2
- 230000008023 solidification Effects 0.000 claims 1
- 238000007711 solidification Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 abstract description 2
- 230000005012 migration Effects 0.000 abstract description 2
- 238000013508 migration Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000004925 denaturation Methods 0.000 description 2
- 230000036425 denaturation Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- 238000001259 photo etching Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
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Abstract
本发明提供了一种载流子增强型MOS结构，包括一具有第一掺杂型的衬底，及在衬底内形成的具有第二掺杂型的源区和漏区，所述源区及所述漏区之间开设有沟槽，所述沟槽内设置有负膨胀应力增强层，所述负膨胀应力增强层与所述沟槽内壁贴合。该结构不仅可以做到隔离沟槽的作用，而且还可以为MOS提供应力，负膨胀应力增强层在低温下，可以膨胀激发电子迁移活力，从而增强MOS的迁移率。
Description
技术领域
本发明涉及一种载流子增强型MOS结构。
背景技术
目前，集成电路一直在往频率更高，功率更低的方向发展。MOS集成电路主要用于高速计算和存储等领域。
PMOS的载流子的迁移率要远低于NMOS，会影响器件在高频下性能。应力应变会增强PMOSFET迁移率，因此，也可以减短信号传输的延迟时间和降低开关能量。
发明内容
本发明提供了一种载流子增强型MOS结构。
本发明的目的通过以下技术方案来实现：
一种载流子增强型MOS结构，包括一具有第一掺杂型的衬底，及在衬底内形成的具有第二掺杂型的源区和漏区，所述源区及所述漏区之间开设有沟槽，所述沟槽内设置有负膨胀应力增强层，所述负膨胀应力增强层与所述沟槽内壁贴合。
优选地，所述负膨胀应力增强层上设置有固化层。
优选地，所述固化层蒸镀于所述负膨胀应力增强层上。
优选地，所述第一掺杂型为p型，所述的第二掺杂型为n型。
优选地，所述第一掺杂型为n型，所述的第二掺杂型为p型。
优选地，所述沟槽至少为一个。
优选地，所述负膨胀应力增强层为钼酸钇应力增强层或钼酸铒应力增强层。
本发明的有益效果体现在：该结构不仅可以做到隔离沟槽的作用，而且还可以为MOS提供应力，负膨胀应力增强层在低温下，可以膨胀激发电子迁移活力，从而增强MOS的迁移率。
附图说明
图1：本发明的结构示意图。
具体实施方式
以下结合附图具体阐述下本发明的具体方案，本发明揭示了一种载流子增强型MOS结构，结合图1所示，包括一具有第一掺杂型的衬底1，及在衬底内形成的具有第二掺杂型的源区2和漏区3。所述第一掺杂型为p型，所述的第二掺杂型为n型。或者所述第一掺杂型为n型，所述的第二掺杂型为p型。
与现有技术不同的是，所述源区及所述漏区之间开设有沟槽，所述沟槽截面呈V形，所述沟槽至少为一个。所述沟槽内设置有负膨胀应力增强层4，所述负膨胀应力增强层4与所述沟槽内壁贴合。
所述负膨胀应力增强层上蒸镀有固化层5。具体的，当负膨胀应力增强层4在高的宽深比的沟槽内时，经过烘干，高温处理，形成内部负膨胀材料的结构。将wafer表面抛光，去除多余的负膨胀材料，蒸镀二氧化硅固化负膨胀材料，最后抛光或者光刻去除多余的二氧化硅固化层。
这样，沟槽内部即填充负膨胀材料，并且有二氧化硅绝缘层固化在沟槽内部。
所述负膨胀应力增强层的负膨胀材料可以采用钼酸盐，钼酸盐具有荧光性能，在检测的过程中，可以使用荧光性能来表征电容材料的失效，例如材料变性，质量偏差。材料变性导致荧光性能变化，质量偏差将导致荧光发射强度变化等，以此提高器件检测能力。
本发明能更好的应用于动态随机存储器，在沟槽的两侧分别制作电容，字线和位线，即可完成DRAM的制作。由于DRAM的制作与现有技术相同，同时，也不是本发明的技术重点，故在此不再赘述。
本发明的原理是，由于器件在低温下，电容材料膨胀，基质的收缩，将导致负膨胀应力增强层内部出现较大的压应力。由于这种电容设置在MOS旁边，因此，这个应力会传到MOS材料中。PMOS的载流子迁移率因此得到增强。
本发明尚有多种具体的实施方式。凡采用等同替换或者等效变换而形成的所有技术方案，均落在本发明要求保护的范围之内。
Claims (3)
1.一种载流子增强型MOS结构，包括一具有第一掺杂型的衬底，及在衬底内形成的具有第二掺杂型的源区和漏区，其特征在于：所述源区及所述漏区之间开设有沟槽，所述沟槽内设置有负膨胀应力增强层，所述负膨胀应力增强层与所述沟槽内壁贴合；所述沟槽截面呈V形；所述负膨胀应力增强层上设置有固化层；所述固化层蒸镀于所述负膨胀应力增强层上，所述沟槽至少为一个，所述负膨胀应力增强层为钼酸钇应力增强层或钼酸铒应力增强层。
2.如权利要求1所述的一种载流子增强型MOS结构，其特征在于：所述第一掺杂型为p型，所述的第二掺杂型为n型。
3.如权利要求1所述的一种载流子增强型MOS结构，其特征在于：所述第一掺杂型为n型，所述的第二掺杂型为p型。
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1154756A (ja) * | 1997-07-30 | 1999-02-26 | Internatl Business Mach Corp <Ibm> | 絶縁体上の半導体のキャリア移動度を強化する構造 |
| CN103632972A (zh) * | 2012-08-23 | 2014-03-12 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
| CN105448723A (zh) * | 2014-08-22 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
| CN105742353A (zh) * | 2014-12-11 | 2016-07-06 | 中芯国际集成电路制造(上海)有限公司 | Mos晶体管及其形成方法 |
| CN206432266U (zh) * | 2016-12-30 | 2017-08-22 | 苏州通富超威半导体有限公司 | 一种载流子增强型mos结构 |
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- 2016-12-30 CN CN201611254930.5A patent/CN106784007B/zh active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1154756A (ja) * | 1997-07-30 | 1999-02-26 | Internatl Business Mach Corp <Ibm> | 絶縁体上の半導体のキャリア移動度を強化する構造 |
| CN103632972A (zh) * | 2012-08-23 | 2014-03-12 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
| CN105448723A (zh) * | 2014-08-22 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
| CN105742353A (zh) * | 2014-12-11 | 2016-07-06 | 中芯国际集成电路制造(上海)有限公司 | Mos晶体管及其形成方法 |
| CN206432266U (zh) * | 2016-12-30 | 2017-08-22 | 苏州通富超威半导体有限公司 | 一种载流子增强型mos结构 |
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