WO2012041071A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
WO2012041071A1
WO2012041071A1 PCT/CN2011/075127 CN2011075127W WO2012041071A1 WO 2012041071 A1 WO2012041071 A1 WO 2012041071A1 CN 2011075127 W CN2011075127 W CN 2011075127W WO 2012041071 A1 WO2012041071 A1 WO 2012041071A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
shallow trench
trench isolation
forming
source
Prior art date
Application number
PCT/CN2011/075127
Other languages
English (en)
French (fr)
Inventor
朱慧珑
尹海洲
骆志炯
梁擎擎
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to US13/379,081 priority Critical patent/US20120261759A1/en
Publication of WO2012041071A1 publication Critical patent/WO2012041071A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled

Definitions

  • the present invention relates to a semiconductor device and a method of fabricating the same, and in particular to a
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • STI shallow trench isolation
  • STI Shallow Low Trench Isolation
  • the manufacturing process of the MOSFET mainly includes: forming a trench by mask etching on the silicon substrate 1, depositing a trench oxide layer to form STI 2, depositing a gate dielectric layer 3 and a gate electrode layer 4, and etching to form a gate stack structure And source/drain recesses, implanted to form source 5 and drain 6, epitaxially grown stress layer 7, which will provide stress to channel region 8 to increase carrier mobility and thereby increase saturation current.
  • the present invention accomplishes the above objects by providing a MOSFET that self-aligns shallow trench isolation sidewalls and methods of fabricating the same.
  • a semiconductor device comprising: a semiconductor substrate; an STI embedded in the semiconductor substrate and forming at least one semiconductor opening region; a channel region located in the semiconductor opening region; a gate stack, a gate dielectric layer and a gate conductor layer are disposed over the channel region; source/drain regions are located on both sides of the channel region, and the source/drain regions include first and opposite sides of the gate stack and adjacent to the STI a seed layer; wherein the upper surface of the STI is higher or closer to the upper surface of the gate dielectric layer.
  • the above-mentioned upper surface sufficiently close to the gate dielectric layer may be defined as: if the upper surface of the gate dielectric layer is higher than the upper surface of the STI, the higher value does not exceed 20 nm. With such a structure, stress leakage in the source/drain regions can be effectively avoided.
  • a method of fabricating a semiconductor device comprising: providing a semiconductor substrate; forming an STI on the semiconductor substrate, the STI forming at least one semiconductor opening region; forming a nitride layer over the STI To protect the STI; forming a gate stack and source/drain regions on both sides of the gate stack in the semiconductor opening region, the gate stack including a gate dielectric layer and a gate conductor layer, the source/drain regions including two oppositely distributed in the gate stack a first seed layer adjacent to the STI; removing a nitride layer above the STI; wherein, after removing the nitride layer, the upper surface of the shallow trench isolation is higher or closer to the gate dielectric The upper surface of the layer.
  • the height of the finally formed STI is higher or closer to the upper surface of the gate dielectric layer.
  • the above-mentioned upper surface sufficiently close to the gate dielectric layer may be defined as: if the upper surface of the gate dielectric layer is higher than the upper surface of the STI, the higher value does not exceed 20 nm. With such a method, stress leakage from the source/drain regions can be effectively avoided.
  • the source/drain regions can be confined to the opening region formed by the STI, thereby effectively improving the trench. Stresses on both sides of the track area, thereby increasing carrier mobility and improving the performance of the semiconductor device.
  • implementation of the invention can effectively prevent stress from being released outside the open area.
  • IA and IB are prior art MOSFET device structures having stress layers and shallow trench isolation
  • FIG. 2 shows a top view of an initial structure including a substrate, a pad oxide layer, a nitride layer, and a photoresist in this order;
  • 3A-3B illustrate a process of sequentially forming a pad oxide layer, a first nitride layer, and a first photoresist on a substrate;
  • 4A, 4B show a process of patterning and etching to form shallow trenches
  • Figures 5A, 5B show the process of depositing and planarizing a shallow trench isolation layer
  • 6A, 6B show the process of etching back the shallow trench isolation layer and depositing a second nitride layer
  • Figs. 7A, 7B show the process of depositing and planarizing the polysilicon layer up to the second nitride layer
  • 8A, 8B show a process of selectively etching a second nitride layer
  • 9A, 9B show the process of removing the polysilicon layer and the pad oxide layer
  • Figures 10A, 10B show the process of depositing shallow trench isolation sidewalls
  • Figure 11 shows a top view of the intermediate structure comprising the active region and the nitride layer
  • Figure 12 shows the patterning of the second photoresist, removing the second nitride layer in the active region along the 1 ⁇ direction Figure 11 structure;
  • Figure 13 shows a top view of the side wall structure to be etched
  • 14A-14B illustrate a process of etching a second nitride layer that is not covered by a second photoresist, and a shallow trench isolation sidewall;
  • Figure 15 shows the process of forming a gate dielectric layer after removing the second photoresist
  • Figure 16 shows the process of forming a gate stack structure
  • Figure 17-19 shows the process of forming the source and drain regions
  • Figure 20 shows a top view of the structure of the metal silicide to be formed
  • Figures 21A-21B show the process of forming a metal silicide and show the resulting new structural device
  • FIG. 2 is a top view
  • FIG. 3A is a side view of the structure shown in FIG. 2 taken along line A-A'
  • FIG. 3B is a side view of the structure shown in FIG. 2 taken along line 1-1'.
  • a pad oxide 11 is formed on the substrate 10.
  • the pad oxide layer 11 which is excellent in properties of the raw material flow rate, temperature, gas pressure, and the like to obtain a desired thickness is 10 to 40 nm, preferably 20 nm in the present embodiment.
  • the substrate 10 may be bulk Si or Sil icon On Insulator (SOI), or may be other suitable semiconductor compound materials such as III-V compound semiconductor materials such as GaAs.
  • SOI Sil icon On Insulator
  • the resulting pad oxide layer 11 is silicon oxide.
  • a first nitride layer 12 is formed on the pad oxide layer 11. It can be produced by a conventional deposition process, and the deposition parameters can also be controlled to obtain a first nitride layer 12 having excellent properties and being flattened, and the thickness thereof is 30 to 150 nm, preferably 60 to 120 nm in the present embodiment. More preferably, it is 90 nm.
  • the nitride layer produced is silicon nitride.
  • the pad oxide layer 11 can be used to protect the underlying substrate structure during etching and other processing.
  • the first nitride layer 12 is used as a mask layer during subsequent etching to form an STI.
  • first photoresist 13 on the first nitride layer 12, pre-baking at a certain temperature, then exposing and developing with a mask pattern required for the STI structure, and again after high-temperature treatment in the first nitride
  • a cured first photoresist pattern is formed over layer 12 that covers the active regions to leave a plurality of openings corresponding to the STI at the periphery.
  • the central region is the first photoresist 13, and the peripheral region is the substrate 10/pad oxygen as seen from above.
  • Figure 4A is a side view of the tangent line taken along line A-A' of Figure 2 after etching and stripping of the corresponding structure of Figure 3A
  • Figure 4B A side view taken along line 1-1 of FIG. 2 after etching and stripping the corresponding structure of FIG. 3B.
  • a certain figure A corresponds to a side view of the A-A' tangent
  • a figure B corresponds to a side view of the 1-1 'tangent line.
  • the shallow trench is then etched.
  • the STI structure is formed by a conventional process. Since the device size is small and the structure is complicated, in order to control the accuracy of the device structure, especially the STI verticality to avoid over-etching of the active region, anisotropic dry etching is usually used, in this embodiment. In the case, reactive ion etching (RIE) is preferably used, and the kind and flow rate of the etching gas can be reasonably adjusted depending on the kind of the material to be etched and the device structure.
  • RIE reactive ion etching
  • the pad oxide layer 11 and the first nitride layer 12 are completely etched in the STI region to expose the substrate 10 and continue deep into the substrate 10 to form trenches.
  • the trench depth HI deep into the substrate 10 is defined as the distance from the lower surface of the trench to the upper surface of the substrate 10 (i.e., the interface between the substrate 10 and the pad oxide layer 11), wherein in the present embodiment, the HI is 100 to 500 nm, preferably 150 to 350 nm.
  • the first photoresist 13 is removed using a method known in the art.
  • oxide 14 is first deposited in shallow trenches. Similar to the formation of the pad oxide layer, the STI 14 can be formed by a conventional process, and the STI 14 is generally made of Si0 2 . Preferably, after the oxide 14 is deposited, chemical mechanical polishing (CMP) is used to planarize the upper surface of the STI oxide 14 until the top of the first nitride layer 12 is exposed, at which time the first nitride layer 12 is used as The stop layer of the CMP.
  • CMP chemical mechanical polishing
  • 6A, 6B show the process of etching back the shallow trench isolation layer and depositing a second nitride layer.
  • the STI oxide 14 is etched back.
  • the STI oxide 14 is etched using a process similar to etching to form an STI trench such that the upper surface of the STI oxide 14 is lower than the upper surface of the first nitride layer 12 but higher than the semiconductor substrate 10, forming a plurality of a groove.
  • a second nitride layer 15 is formed.
  • the second nitride layer 15 is formed on the entire surface of the device by a method such as high density plasma chemical vapor deposition (HDPCVD).
  • the high density plasma chemical vapor deposition enables the sidewall thickness of the second nitride layer 15 formed on the sidewalls of the first nitride layer 12 to be smaller than that formed on the top of the first nitride layer 12 and the top of the STI oxide 14.
  • the second nitride layer 15 is formed on the sidewall of the first nitride layer 12 to have a thickness of 7 to 10 nm.
  • the thickness of the top of the first nitride layer 12 is 20 to 30 nm.
  • 7A, 7B show the process of depositing and planarizing the polysilicon layer 16 up to the second nitride layer.
  • polysilicon may be deposited on the entire surface of the device by a conventional CVD method or other methods, and then CMP is performed until reaching the upper surface of the second nitride layer 15, so that the polysilicon layer 16 is left only over the STI trench.
  • FIGS. 8A, 8B show the process of selectively etching the second nitride layer 15.
  • the nitride layer is selectively etched by reactive ion etching (RIE), and the reactive ions and etching conditions are selected such that the rate of etching the nitride exceeds the speed of etching the polysilicon and the oxide, thereby forming the shallow trench isolation 14
  • RIE reactive ion etching
  • the second nitride layer 15 and the first nitride layer 12 in the open region are completely etched, leaving only the second nitride layer 15 remaining under the polysilicon layer 16, and the pad oxide layer 11 is exposed.
  • the nitride above the STI 14 is not used in this etching step. Etched off. Since the nitride above the STI 14 can protect the STI, the surface of the resulting STI is not easily destroyed by subsequent cleaning or etching processes.
  • FIGS. 9A, 9B show the process of removing the polysilicon layer 16 and the pad oxide layer 11.
  • the polysilicon above the second nitride layer 15 and the pad oxide layer 11 lower than the second nitride 15 may be removed by isotropic dry etching or wet etching.
  • the structure shown in Figs. 9A, 9B is finally formed.
  • the etching of the STI 14 by the cleaning, etching, etc. process is greatly reduced to maintain the STI at an appropriate height.
  • a thin oxide layer (not shown) is formed by, for example, deposition, having a thickness of 2 to 5 nm, which is used as an etch stop layer required for a later STI sidewall process by reactive ion etching. .
  • a third nitride layer is then deposited by a conventional process to a thickness of 5 to 30 nm. The third nitride layer is then etched by reactive ions to form STI spacers 17 on the sidewalls of the STI 14 and at least partially on the active region 10'.
  • the STI spacer 17 is self-aligned to the edge of the STI and surrounds the inner wall of the opening, so that pattern distortion due to alignment deviation of the reticle can be avoided. As shown by the broken line portion in the substrate 10 in Figs. 10A, 10B, it is the active region 10'.
  • the STI spacers 17 in the channel region can be removed.
  • FIG. 11 is a top view, and the gray portion represents the second nitridation.
  • FIG. 12 is a side view of FIG. 11 along the 1 ⁇ direction. Similar to the formation of the first photoresist 13, a second photoresist 18 is applied on the gray area of FIG.
  • FIG. 13 14A-14B show the process of etching the second nitride layer 15, the STI spacer 17, which is not covered by the second photoresist 18.
  • the nitride is etched by a conventional method. Since AA in the top view shown in Fig. 13 does not cover the second photoresist 18, as shown in Fig. 14A, the top of the STI oxide 14 is exposed in this direction. The STI spacer 17 is also removed, and the semiconductor substrate 10 is completely exposed; and since 1-1 is partially covered with the second photoresist 18 in FIG. 13, the structure shown in FIG. 14B is formed, and remains. Part of the second nitride layer 15, a portion of the STI side wall 17.
  • a side view 15 along the line 1-1' shows the process of forming a gate dielectric layer after removing the second photoresist
  • Fig. 16 shows the process of forming a gate stack structure.
  • a gate dielectric layer 19 may be formed on the entire surface of the device structure, which may be a common gate dielectric layer or a high-k gate dielectric layer, and may have a thickness of l-3 nm.
  • a metal layer (not shown) as a gate conductor may be deposited on the gate dielectric layer 19 to have a thickness of 10-20 nm.
  • a polysilicon layer 20 having a thickness of 20 to 50 nm is deposited on the gate metal layer.
  • a fourth nitride layer 21 having a thickness of 10 to 40 nm is deposited on the polysilicon layer 20.
  • a gate pattern is formed by patterning a third photoresist (not shown), and the fourth nitride layer 21, the polysilicon layer 20, and the gate metal layer are transferred to the gate dielectric by a conventional process, for example, by reactive ion etching Layer 19, thus forming the gate stack structure of Figure 16.
  • the STI is generally higher than the upper surface of the gate dielectric layer 19 or sufficiently close to the upper surface.
  • the meaning of being close enough is that even if the upper surface of the gate dielectric layer 19 is higher than STI, it does not exceed 20 nm.
  • the STI is usually 60 nm or more lower than the upper surface of the gate dielectric layer.
  • a side view 17 along the 1-1 'tangent line shows the process of forming the source and drain regions.
  • source and drain regions (not shown) having a halo and extension structure can be formed by ion implantation as needed to adjust the threshold voltage and prevent source-drain punch-through.
  • a gate spacer different from the STI sidewall is formed on the sidewall of the gate stack structure, and the specific method may be: depositing a thin oxide layer (not shown) serving as an etch stop layer over the entire structure, a thickness of 2 to 5 nm, depositing a fifth nitride layer 22 having a thickness of 10 to 50 nm and passing The fifth nitride layer 22 is reactively etched to form the gate spacers 22 on the gate sidewalls.
  • a side view 18 along 1-1 'tangent line shows the process of etching the semiconductor substrate 10 with the STI spacers 17 and the gate spacers 22 to form the recesses 23 required for the source/drain regions.
  • the width of the first seed layer 24 is preferably 5-20 nm.
  • source-drain ion doping implantation may be further performed on the substrate under the recess.
  • B ions can be doped
  • P or As ions can be doped.
  • a portion of the substrate immediately below the bottom wall of the recess is referred to as a second seed layer 29.
  • a side view 19 along the 1-1 'tangent line shows the process of forming a source/drain region with stress.
  • the stress layer 25 is formed by selective epitaxial growth in the recess 23 to adjust the channel stress to improve device performance. Specifically, the stress layer 25 is epitaxially grown with the first seed layer 24 and the second seed layer 29 at the bottom of the groove 23 as a crystal source.
  • the stressor layer material is SiGe to apply compressive stress to the channel, where the Ge content is 15% to 70%.
  • the source/drain region material is Si: C to apply a tensile stress to the channel, wherein the C content is 0.2% to 2%.
  • the source/drain regions are formed by the first seed layer 24, the second seed layer 29, and the stress layer 25 on the second seed layer. Since the first seed layer 24 also epitaxially grows the crystal as a crystal source, the growth of the stress layer is easier.
  • the side view 21A along the line A-A' and the side view 21B along the line 1-1' form the process of forming the metal silicide 26.
  • the second nitride layer 15 and the fourth nitride layer 21 are removed by reactive ion etching to expose the top of the gate stack, i.e., expose the polysilicon layer 20.
  • a metal silicide 26, such as SiPtNi is formed on the source/drain regions and the polysilicon layer 20 by a conventional method.
  • the following method may be employed: first, a thin layer of NiPt is formed by sputtering, and a silicide SiPtNi is formed by rapid thermal annealing at 300-500 ° C. The selective wet etching then removes the unreacted metal and rapidly thermally annealed again to form a low-resistance silicide 26 which can be used for the metal silicide.
  • the semiconductor device includes: a semiconductor substrate 10; an STI 14, embedded in the semiconductor substrate 10, and forming at least one semiconductor opening region; and a channel region located in the semiconductor opening region; a gate stack including a gate dielectric layer 19 and a gate conductor layer 20 over the channel region; source/drain regions on both sides of the channel region, the source/drain regions including opposite sides of the gate stack, and
  • the STI is adjacent to the first seed layer 24; wherein the upper surface of the STI 14 is higher or closer to the upper surface of the gate dielectric layer 19.
  • the above-mentioned upper surface sufficiently close to the gate dielectric layer can be defined in the embodiment of the present invention as follows: If the upper surface of the gate dielectric layer 19 is higher than the upper surface of the STI 14, the value higher is not more than 20 nm. In the semiconductor device obtained by the prior art, the STI is usually 60 nm or more lower than the upper surface of the gate dielectric layer. This method can effectively avoid stress leakage in the source/drain regions.
  • the gate stack structure preferably further includes a gate metal silicide 26; and a sidewall spacer 22 is provided on the sidewall of the surrounding gate stack structure.
  • the STI spacers 17 are self-aligned to the edges of the STI 14 and are at least partially located within the active region 10', and preferably at least partially within the source/drain regions.
  • the source/drain regions are formed by the first seed layer 24, the second seed layer 29, and the stress layer 25 on the second seed layer.
  • the second seed layer 29 is located at the bottom of the source/drain region, wherein the stress layer 25 is formed by epitaxial growth of the first seed layer 24 and the second seed layer 29.
  • the second seed layer 29 may comprise ions doped in situ, for example, B for a pMOSFET and 8 or 3 for an nMOSFET.
  • the stress layer material is SiGe to apply a compressive stress to the channel, wherein the Ge content is 15% to 70%.
  • the source/drain region material is Si: C to apply a tensile stress to the channel, wherein the C content is 0.2% to 2%.
  • Metal silicides 26 are preferably formed on the source/drain regions and are adjacent to the STI spacers 17 and the gate spacers 22, respectively.
  • the STI spacer 17 may be formed of a combination of any one or more of SiO 2 , Si 3 N 4 , and SiON.
  • the thickness of the first seed layer between the source/drain regions 25 and the STI 14 is 5-20 nm, and such structural features facilitate epitaxial growth of the stress layer.
  • the upper surface of the STI 14 is higher than the upper surface of the gate dielectric layer 19.
  • the upper surface of the STI is higher or closer to the upper surface of the gate dielectric layer, thereby avoiding the outward diffusion of the stress of the source/drain regions, which enhances the channel stress of the device and improves the current carrying. Sub-mobility and thus improved device performance.
  • the manufacturing method of this other embodiment is basically the same as the above embodiment, except that: after the step of forming the source/drain regions having stress, before forming the metal silicide 26, Not only the second nitride layer 15 and the fourth nitride layer 21 are removed by reactive ion etching, the top of the gate stack structure is exposed, that is, the polysilicon layer 20 is exposed; and the STI spacer 17 is also subjected to reactive ion etching.
  • the metal silicide 26 also forms a groove 27 matching the source/drain region 25 on the side close to the original shallow trench isolation spacer 17, see FIG. In a subsequent process, such as the deposition of an interlayer dielectric layer, other insulating layers, the recess 27 will be filled with a dielectric material.
  • the STI 14 and the source/drain regions 25 are separated by a dielectric material 28, see Fig. 23.
  • the dielectric material 28 may comprise a combination of any one or more of SiOF, SiC0H, Si0, SiC0, SiC0N, PSG, and BPSG.
  • the top of the source/drain stress layer 25 is a metal silicide 26, and the dielectric material 28 is between the metal silicide 26 and the STI 14.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)

Description

说 明 书
半导体器件及其制造方法 技术领域
本发明涉及一种半导体器件及其制造方法， 特别地涉及一种
M0SFET (金属氧化物半导体场效应晶体管） 及其制造方法， 其中， 该 M0SFET具有增强的源 /漏应力层以及自对准浅沟槽隔离 （STI ) 侧墙。 背景技术
过去数十年间， 集成电路的发展几乎严格遵循着由 Intel创始人 之一戈登摩尔提出的著名的摩尔定律： 集成电路 （ICs ) 上可容纳的 晶体管数目， 约每 18个月增加一倍， 性能也提升一倍。 这主要是由 IC 尺寸持续缩小 （scal ing— down ) 来实现的， 特别是在数字电路中最 常使用的 M0SFET的特征尺寸， 也即沟道长度或者栅极间距 （pitch ) 不断缩减， 与集成工艺、 小尺寸封装、 可测试性设计等等技术一起使 得同一晶圆上可制造的 IC数目剧增， 从而使得均摊到单颗封装测试后 的 IC上的制造成本锐减。
在集成电路的制造中， 不同的晶体管之间需进行隔离。 目前普遍 采用的是延伸到衬底中的浅沟槽隔离 （Shal low Trench Isolation, STI ) ， 该结构同样也有利于普通 CMOS的制备。
参见附图 1A， 显示了一个现有的 M0SFET结构。 该 M0SFET的制造过 程主要包括： 在硅衬底 1上掩模刻蚀形成沟槽， 淀积沟槽氧化层形成 STI 2 , 淀积栅介质层 3和栅电极层 4， 刻蚀形成栅堆叠结构以及源 /漏 凹槽， 注入形成源极 5和漏极 6， 外延生长应力层 7， 应力层 7将为沟道 区 8提供应力以提高载流子的迁移率从而增大饱和电流。 然而， 由于 在形成 STI后整个器件结构又经历了数次处理， 例如侵蚀性的清洗、 刻蚀形成栅极堆叠结构， 这些过程中对介电材料 （氧化物、 氮化物、 氮氧化物等） 起作用的溶液、 离子同样作用于 STI中的氧化物， 因此 将如图 1B所示， 最后形成的 STI 2的顶部低于应力层 7的顶部， 从而使 得应力从 STI 2与应力层 7的侧向界面上也即图 1B两箭头所指处释放出 去， 造成了应力层能够为沟道区两侧提供的应力减小， 使得载流子改 善达不到预期目标， 大大影响了器件的性能。 因此， 需要一种能有效地防止应力丢失从而改善器件性能的新结 构以及制造这种结构的方法。 发明内容
本发明通过提供一种自对准浅沟槽隔离侧墙的 M0SFET及其制造 方法来实现上述目的。
根据本发明的一个方面， 提供了一种半导体器件， 包括： 半导体 衬底； STI , 嵌于半导体衬底中， 且形成至少一个半导体开口区； 沟 道区， 位于半导体开口区内； 栅堆叠， 包括栅介质层和栅极导体层， 位于沟道区上方； 源 /漏区， 位于沟道区的两侧， 源 /漏区包括相对分 布于栅堆叠的两侧、 且与 STI邻接的第一晶种层； 其中， STI的上表面 高于或足够接近于栅介质层的上表面。
上述的足够接近于栅介质层的上表面， 在本发明的实施例中， 可 以限定为： 如果所述栅介质层上表面比 STI的上表面高， 高出的值不 超过 20nm 。 采用这样的结构能够有效避免源 /漏区的应力外泄。
根据本发明的另一方面， 还提供了一种制造半导体器件的方法， 包括： 提供半导体衬底； 在半导体衬底上形成 STI， STI形成至少一个 半导体开口区； 在 STI的上方形成氮化物层以保护 STI ; 在半导体开口 区内形成栅堆叠和以及栅堆叠两侧的源 /漏区， 所述栅堆叠包括栅介 质层和栅极导体层， 源 /漏区包括相对分布于栅堆叠的两侧、 且与 STI 邻接的第一晶种层； 去除 STI上方的氮化物层； 其中， 去除所述氮化 物层后， 所述浅沟槽隔离的上表面高于或足够接近于所述栅介质层的 上表面。 。 由于在工艺过程中， 在 STI上方的氮化物层中进行了保护， 因为最后形成的 STI的高度高于或足够接近于栅介质层的上表面。 上 述的足够接近于栅介质层的上表面， 在本发明的实施例中， 可以限定 为： 如果所述栅介质层上表面比 STI的上表面高， 高出的值不超过 20nm 。 采用这样的方法能够有效避免源 /漏区的应力外泄。
本发明的实施例半导体器件及其制造方法， 由于 STI的上表面高 于或足够接近于源 /漏区的上表面， 因此能够将源 /漏区限制于 STI形 成的开口区内， 有效提高沟道区两侧的应力， 从而提高载流子的迁移 率， 改善半导体器件的性能。
尤其对于源 /漏区上带有应力层的半导体结构， 则本发明的实施 例能够有效防止应力释放到开口区之外。
本发明所述目的， 以及在此未列出的其他目的， 在本申请独立权 利要求的范围内得以满足。 本发明的实施例限定在独立权利要求中。 附图说明
图 1A、 IB 为现有技术的具有应力层和浅沟槽隔离的 M0SFET器件 结构；
图 2显示了依次包括衬底、 垫氧化层、 氮化物层和光致抗蚀剂的 初始结构的顶视图；
图 3A-3B显示了在衬底上依次形成垫氧化层、 第一氮化物层和第 一光致抗蚀剂的过程；
图 4A、 4B 显示了图案化并刻蚀形成浅沟槽的过程；
图 5A、 5B 显示了淀积并平坦化浅沟槽隔离层的过程；
图 6A、 6B显示了回刻浅沟槽隔离层并淀积第二氮化物层的过程; 图 7A、 7B 显示了淀积并平坦化多晶硅层直至第二氮化物层的过 程；
图 8A、 8B 显示了选择性蚀刻第二氮化物层的过程；
图 9A、 9B 显示了去除多晶硅层和垫氧化层的过程；
图 10A、 10B 显示了淀积浅沟槽隔离侧墙的过程；
图 11显示了包含有源区和氮化物层的中间结构的顶视图； 图 12 显示了图案化第二光致抗蚀剂、 去除有源区内的第二氮化 物层后的沿 1 Γ方向的图 11结构；
图 13显示了待刻蚀侧墙结构的顶视图；
图 14A— 14B 显示了刻蚀未被第二光致抗蚀剂覆盖的第二氮化物 层、 浅沟槽隔离侧墙的过程；
图 15 显示了去除第二光致抗蚀剂后形成栅介质层的过程； 图 16 显示了形成栅堆叠结构的过程；
图 17-19 显示了形成源漏区的过程；
图 20显示了待形成金属硅化物的结构的顶视图；
图 21A— 21B 显示了形成金属硅化物的过程并显示了最终形成的 新结构器件；
图 22、 23 显示了根据本发明另一个实施例得到的半导体器件的 结构。 具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方 案的特征及其技术效果， 公开了具有增强的源 /漏应力层以及自对准 浅沟槽隔离 （STI )边缘保护层的新型 M0SFET器件结构及其制造方法。 需要指出的是， 类似的附图标记表示类似的结构， 本申请中所用的术 语 "第一" 、 "第二" 、 "上" 、 "下"等等可用于修饰各种器件结 构。 这些修饰除非特别说明并非暗示所修饰器件结构的空间、 次序或 层级关系。
现参见图 2以及图 3A-3B, 为在传统的半导体衬底上制造 M0SFET的 准备工序， 显示了在衬底上依次形成垫氧化层、 第一氮化物层和第一 光致抗蚀剂的过程。 其中图 2为顶视图， 图 3A为图 2所示结构沿 A-A'切 线的侧视图， 图 3B为图 2所示结构沿 1-1'切线的侧视图。
首先， 在衬底 10上形成垫氧化层 （pad oxide ) 11。 例如是通过 APCVD、 LPCVD、 PECVD等传统工艺， 也可以使用热氧化来实现。 控制 原料流速、 温度、 气压等参数从而获得预期厚度的性质优良的垫氧化 层 11， 其厚度在本实施例中为 10至 40nm， 优选为 20 nm。 衬底 10可以 是体硅 ( bulk Si ) 或绝缘体上硅 ( Sil icon On Insulator, SOI ) ， 也可以是恰当的其他半导体化合物材料， 例如 GaAs等 III-V族化合物 半导体材料。 当衬底 10为 Si材料时， 制得的垫氧化层 11为氧化硅。
接着， 在垫氧化层 11上形成第一氮化物层 12。 可以通过传统的淀 积工艺制得， 同样可以控制淀积参数来得到性质优良、 均勾平坦的第 一氮化物层 12，其厚度在本实施例中为 30至 150nm，优选为 60至 120nm， 更优选为 90nm。 对于 Si衬底， 制得的氮化物层为氮化硅。 垫氧化层 11 可用于在刻蚀及其它处理中保护下面的衬底结构。 第一氮化物层 12在 后续的刻蚀形成 STI过程中用作掩模层。
然后， 图案化 STI。 在第一氮化物层 12上涂敷第一光致抗蚀剂 13， 在一定温度下前烘， 随后用 STI结构所需的掩模图形来曝光、 显影， 再次高温处理后在第一氮化物层 12上形成了覆盖有源区从而在周边 留下对应于 STI的多个开口的固化的第一光致抗蚀剂图形。 参见图 2， 中心区域为第一光致抗蚀剂 13， 周边区域为俯视看到的衬底 10/垫氧 化层 11/第一氮化物层 12的叠层结构。
参见图 4A、 4B, 显示了图案化并刻蚀形成浅沟槽的过程， 其中图 4A为图 3A对应结构刻蚀并去胶后的沿图 2的 A-A'切线的侧视图， 图 4B 为图 3B对应结构刻蚀并去胶后的沿图 2的 1-1 '切线的侧视图。以下类似 的， 若未特别说明， 则某图 A对应于 A-A'切线的侧视图， 某图 B对应于 1-1 '切线的侧视图。
接着刻蚀浅沟槽。 通过传统工艺形成 STI结构， 由于器件尺寸小 结构复杂， 为了控制器件结构的精度， 尤其是 STI垂直度以避免有源 区过刻蚀， 因此通常采用各向异性的干法刻蚀， 在本实施例中优选使 用反应离子刻蚀 （RIE ) ， 刻蚀气体的种类和流量可以依据待刻蚀材 料种类和器件结构而合理地调节。 参见图 4A和图 4B， 在 STI区域完全 刻蚀垫氧化层 11和第一氮化物层 12， 露出衬底 10， 并继续深入衬底 10 以形成沟槽。深入衬底 10的沟槽深度 HI定义为从沟槽下表面至衬底 10 上表面 （也即衬底 10与垫氧化层 11之间界面） 的距离， 其中在本实施 例中 HI为 100至 500nm， 优选为 150至 350nm。
然后， 去除第一光致抗蚀剂 13， 采用本领域公知的方法。
参见图 5A、 5B， 显示了淀积并平坦化浅沟槽隔离层的过程。 在这 个过程中， 首先在浅沟槽中淀积氧化物 14。 与形成垫氧化层类似， 可 以通过传统工艺来形成 STI 14， STI 14一般采用 Si02。 优选地， 在淀 积氧化物 14后， 使用化学机械抛光 （CMP ) 来平坦化 STI氧化物 14的上 表面，直至第一氮化物层 12的顶部露出，此时第一氮化物层 12用作 CMP 的停止层。
图 6A、 6B显示了回刻浅沟槽隔离层并淀积第二氮化物层的过程。 接着， 回刻 （etch back ) STI氧化物 14。 使用与刻蚀形成 STI沟 槽类似的工艺， 对 STI氧化物 14进行刻蚀， 使得 STI氧化物 14的上表面 低于第一氮化物层 12的上表面但高于半导体衬底 10， 形成多个凹槽。
然后， 形成第二氮化物层 15。 通过例如是高密度等离子体化学气 相淀积 （HDPCVD ) 等方法， 在整个器件上表面形成第二氮化物层 15。 高密度等离子体化学气相淀积能够使得在第一氮化物层 12侧壁上形 成的第二氮化物层 15的侧壁厚度要小于在第一氮化物层 12顶部以及 STI氧化物 14顶部形成的第二氮化物层 15的厚度。 本实施例中， 第二 氮化物层 15形成在第一氮化物层 12侧壁上的厚度为 7至 10nm， 形成在 第一氮化物层 12顶部的厚度为 20至 30nm。
图 7A、 7B显示了淀积并平坦化多晶硅层 16直至第二氮化物层的过 程。 具体地， 可以通过传统的 CVD方法或其他方法在整个器件表面淀 积多晶硅， 然后进行 CMP直至到达第二氮化物层 15的上表面， 于是仅 在 STI沟槽上方留下多晶硅层 16。
图 8A、 8B显示了选择性蚀刻第二氮化物层 15的过程。 通过反应离 子刻蚀 （RIE ) 对氮化物层进行选择性刻蚀， 选择反应离子以及刻蚀 条件使得刻蚀氮化物的速度超过刻蚀多晶硅以及氧化物的速度， 因此 使得浅沟槽隔离 14形成的开口区内第二氮化物层 15以及第一氮化物 层 12被完全刻蚀， 仅留下多晶硅层 16下方剩余的第二氮化物层 15， 且 暴露出垫氧化层 11。
由于第二氮化物层 15在第一氮化物层 12的侧壁上的厚度小于在 第一氮化物层 12的顶部的厚度，因此在这个刻蚀步骤中，不会将 STI 14 上方的氮化物刻蚀掉。 由于 STI 14上方的氮化物能够对 STI进行保护， 因此最终形成的 STI的表面不容易被后续的清洗或刻蚀等工艺破坏。
图 9A、 9B显示了去除多晶硅层 16和垫氧化层 11的过程。 可以通过 各向同性的干法刻蚀或湿法刻蚀来去除第二氮化物层 15上方的多晶 硅以及比第二氮化物 15低的垫氧化层 11。 最终形成了图 9A、 9B中所示 的结构。
由于 STI 14的上方有氮化物层保护， 因此在后续的工艺中， 将大 大减小清洗、 刻蚀等工艺对 STI 14的腐蚀， 以使 STI保持适当的高度。
图 10A、 图 10B显示了形成 STI侧墙 17的过程。 首先通过例如淀积 来形成一层薄的氧化层 （图中未示出） ， 厚度为 2至 5nm， 用作稍后的 通过反应离子刻蚀形成 STI侧墙工艺中所需要的刻蚀停止层。 接着通 过传统工艺来淀积第三氮化物层， 其厚度为 5至 30nm。 随后通过反应 离子刻蚀第三氮化物层从而在 STI 14的侧壁上以及至少部分地在有源 区 10'上形成 STI 侧墙 17。 STI 侧墙 17自对准于 STI的边缘且环绕该开 口内壁， 因此可以避免因为光刻板对准偏差而引起的图案变形。 如图 10A、 10B中衬底 10中的虚线部分所示， 为有源区 10'。
可选地， 可以去除沟道区中的 STI侧墙 17。
参见图 11、 12 , 显示了图案化第二光致抗蚀剂 18以便去除有源区 内的第二氮化物层 15的过程。 图 11为顶视图， 灰色部分代表第二氮化 物层 15以及 STI侧墙 17， 中心的有源区 10'与 STI 侧墙 17有交叠； 图 12 为图 11沿 1 Γ方向的侧视图。 与形成第一光致抗蚀剂 13类似， 在图 11 灰色区域上涂敷第二光致抗蚀剂 18，在一定温度下前烘，随后来曝光、 显影， 再次高温处理后， 在第二氮化物层 15、 STI侧墙 17以及部分半 导体衬底 10上留下第二光致抗蚀剂 18， 如图 12所示。
图 13、 14A-14B显示了刻蚀未被第二光致抗蚀剂 18覆盖的第二氮 化物层 15、 STI侧墙 17的过程。 采用传统方法刻蚀氮化物， 由于图 13 所示顶视图中 A-A，方向上没有覆盖第二光致抗蚀剂 18， 因此如图 14A 所示， 在该方向上， STI氧化物 14的顶部暴露， STI侧墙 17也被去除， 半导体衬底 10完全暴露； 而由于图 13中 1-1，方向上部分覆盖有第二光 致抗蚀剂 18， 因此形成图 14B所示的结构， 仍保留部分第二氮化物层 15、 部分 STI侧墙 17。
沿 1-1'切线的侧视图 15显示了去除第二光致抗蚀剂后形成栅介质 层的过程， 图 16形成栅堆叠结构的过程。
具体地， 首先在整个器件结构表面上形成栅介质层 19， 可以是普 通栅介质层或高 K栅介质层， 厚度可以为 l-3nm。 可以在栅介质层 19上 淀积作为栅极导体的金属层 （未示出） ， 厚度可以为 10-20nm。 在栅 极金属层上淀积厚度为 20-50nm的多晶硅层 20。 在多晶硅层 20上淀积 厚度为 10-40nm的第四氮化物层 21。 随后， 通过图案化第三光致抗蚀 剂 （未示出） 形成栅极图案， 通过传统工艺， 例如通过反应离子刻蚀 第四氮化物层 21、 多晶硅层 20以及栅极金属层直至栅介质层 19， 因此 形成了图 16中的栅极堆叠结构。
通过本发明实施例得到的半导体器件中， STI—般能高于栅介质 层 19的上表面， 或者足够接近该上表面。 足够接近的含义是， 即使栅 介质层 19的上表面高于 STI , 也不超过 20nm。 而采用现有技术得到的 半导体器件， 通常 STI比栅介质层的上表面低 60nm以上。
沿 1-1 '切线的侧视图 17显示了形成源漏区的过程。 首先， 根据需 要可以通过离子注入来形成具有暈环 （halo ) 和延伸 （extension ) 结构的源漏区 （未示出） ， 以便调节阈值电压以及防止源漏穿通。 然 后， 在栅堆叠结构的侧壁上形成区别于 STI侧墙的栅极侧墙， 具体的 方法可以为： 在整个结构上淀积用作刻蚀停止层的薄氧化层 （未示 出） ， 厚度为 2至 5nm， 淀积厚度为 10至 50nm的第五氮化物层 22并通过 反应离子刻蚀第五氮化物层 22从而在栅极侧壁上形成栅极侧墙 22。 沿 1-1 '切线的侧视图 18显示了以 STI侧墙 17、栅极侧墙 22为界刻蚀 半导体衬底 10从而形成源 /漏区所需的凹槽 23的过程。 通过反应离子 刻蚀源 /漏区上的衬底材料， 由于源 /漏区上方两侧具有 STI侧墙 17以 及栅极侧墙 22， 因此可以调节反应离子刻蚀的参数从而控制衬底硅和 氮化物侧墙之间的选择比， 从而在衬底上留下图 15所示的凹槽 23。 从 图 15中可见， 由于 STI侧墙 17的存在， 凹槽 23与 STI 14之间有一定的 间隙， 这个间隙构成了后面形成源 /漏应力层的第一晶种层 （Seed Layer) 24, 该第一晶种层 24的宽度优选为 5- 20nm。
可选地， 可以进一步对凹槽下方的衬底进行源漏离子掺杂注入。 例如， 对于 pM0SFET， 可以掺杂 B离子， 对于 nM0SFET， 可以掺杂 P或 As 离子。在这里，把凹槽的底壁下紧邻的一部分衬底叫做第二晶种层 29。
沿 1-1 '切线的侧视图 19显示了形成具有应力的源 /漏区的过程。在 凹槽 23内通过选择性外延生长形成应力层 25以调节沟道应力从而提 高器件性能。 具体地， 以第一晶种层 24以及位于所述凹槽 23底部的第 二晶种层 29作为晶源外延生长应力层 25。 对于 pMOSFET而言， 应力层 材料为 SiGe以向沟道施加压应力， 其中 Ge含量为 15 %至 70 %。 对于 nMOSFET而言， 源 /漏区材料为 Si : C以向沟道施加拉应力， 其中 C含量 为 0. 2 %至 2 %。 源 /漏区由第一晶种层 24、 第二晶种层 29以及第二晶 种层上的应力层 25形成。 由于第一晶种层 24也作为晶源外延生长晶 体， 因此应力层的生长更为容易。
顶视图 20、 沿 A-A'切线的侧视图 21A以及沿 1-1 '切线的侧视图 21B 形成金属硅化物 26的过程。 通过反应离子刻蚀去除第二氮化物层 15以 及第四氮化物层 21， 暴露出栅堆叠的顶部， 也即暴露出多晶硅层 20。 随后使用传统方法在源 /漏区以及多晶硅层 20上形成金属硅化物 26， 例如 SiPtNi , 可以采用如下方法： 先溅射形成薄层 NiPt , 300-500°C 下快速热退火形成硅化物 SiPtNi , 随后选择性湿法刻蚀去除未反应的 金属， 再次快速热退火， 形成低阻态的硅化物 26， 可以用于金属硅化 物。
至此形成了根据本发明一个实施例的半导体器件， 结构如图 21B 所示。 该半导体器件包括： 半导体衬底 10 ; STI 14， 嵌于半导体衬底 10中， 且形成至少一个半导体开口区； 沟道区，位于半导体开口区内； 栅堆叠， 包括栅介质层 19和栅极导体层 20， 位于沟道区上方； 源 /漏 区， 位于沟道区的两侧， 源 /漏区包括相对分布于栅堆叠的两侧、 且 与 STI邻接的第一晶种层 24; 其中， STI 14的上表面高于或足够接近 于栅介质层 19的上表面。
上述的足够接近于栅介质层的上表面， 在本发明的实施例中， 可 以限定为： 如果栅介质层 19上表面比 STI 14的上表面高， 高出的值不 超过 20nm。 而采用现有技术得到的半导体器件， 通常 STI比栅介质层 的上表面低 60nm以上。 采用这样的方法能够有效避免源 /漏区的应力 外泄。
其中， 栅堆叠结构优选还包括栅极金属硅化物 26 ; 环绕栅堆叠结 构侧壁有栅极侧墙 22。
优选地， STI侧墙 17自对准于 STI 14的边缘且至少部分地位于有 源区 10'内， 并且优选至少部分位于源 /漏区内。
源 /漏区由第一晶种层 24、 第二晶种层 29以及第二晶种层上的应 力层 25形成。 其中第二晶种层 29位于源 /漏区的底部， 其中， 应力层 25由第一晶种层 24和第二晶种层 29外延生长形成。 优选地， 第二晶种 层 29可以包含原位掺杂的离子，例如，对于 pMOSFET为 B，对于 nMOSFET 为八3或？。 优选地， 对于 pMOSFET而言， 应力层材料为 SiGe以向沟道施 加压应力， 其中 Ge含量为 15 %至 70 %。 对于 nMOSFET而言， 源 /漏区材 料为 Si : C以向沟道施加拉应力， 其中 C含量为 0. 2 %至 2 %。
源 /漏区上优选形成有金属硅化物 26， 并分别与 STI侧墙 17以及栅 极侧墙 22相邻。 STI侧墙 17可以由 Si02、 Si3N4、 SiON中的任一种或多 种的组合形成。
优选地， 第一晶种层在源 /漏区 25与 STI 14之间的厚度为 5-20nm， 这样的结构特征有利于应力层的外延生长。
优选地， STI 14的上表面高于栅介质层 19的上表面。
本发明的实施例中， STI的上表面高于或足够接近于栅介质层的 上表面， 从而避免了源 /漏区的应力向外扩散， 这增强了器件的沟道 应力、 提高了载流子迁移率并因此提升了器件性能。
图 22、 23显示了根据本发明的另一实施例的得到的半导体器件。 该另一实施例的制造方法基本与上述实施例相同， 不同之处在于： 在 上述形成具有应力的源 /漏区的步骤之后， 在形成金属硅化物 26之前， 通过反应离子刻蚀不仅去除第二氮化物层 15以及第四氮化物层 21， 暴 露出栅堆叠结构的顶部， 也即暴露出多晶硅层 20 ; 同时还将 STI侧墙 17进行反应离子刻蚀， 使得 STI 14的侧壁上没有氮化物侧墙， 此时由 于反应刻蚀离子也同样作用于源 /漏区应力层 25， 因此在去除了 STI侧 墙 17后同时在源 /漏区 25的靠近原 STI侧墙 17所在的一侧形成凹槽 27。 因此在随后的金属硅化物 26形成过程中， 金属硅化物 26也同样在靠近 原浅沟槽隔离侧墙 17所在的一侧形成与源 /漏区 25匹配的凹槽 27， 参 照图 22。 在后续的工艺中， 例如淀积层间介质层、 其它绝缘层的过程 中， 该凹槽 27将会填上介质材料。
因此在本发明的一个实施例中， 优选地， 在第一晶种层 24上方， STI 14与源 /漏区 25之间通过介质材料 28隔离， 参照图 23。 介质材料 28可以包括 SiOF、 SiC0H、 Si0、 SiC0、 SiC0N、 PSG以及 BPSG中的任一 种或多种的组合。
优选地， 源 /漏区应力层 25的顶部为金属硅化物 26， 则介质材料 28位于金属硅化物 26和 STI 14之间。
尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人 员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变 和等价方式。 此外， 由所公开的教导可做出许多可能适于特定情形或 材料的修改而不脱离本发明范围。 因此， 本发明的目的不在于限定在 作为用于实现本发明的最佳实施方式而公开的特定实施例， 而所公开 的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims

权 利 要 求 书
1. 一种半导体器件， 包括：
半导体衬底；
浅沟槽隔离， 嵌于所述半导体衬底中， 且形成至少一个半导体开 口区；
沟道区， 位于所述半导体开口区内；
栅堆叠， 包括栅介质层和栅极导体层， 位于所述沟道区上方； 源 /漏区， 位于所述沟道区的两侧， 所述源 /漏区包括相对分布于 所述栅堆叠的两侧、 且与所述浅沟槽隔离邻接的第一晶种层；
其中， 所述浅沟槽隔离的上表面高于或足够接近于所述栅介质层 的上表面。
2. 根据权利要求 1所述的半导体器件， 其中， 在所述第一晶种层 上方， 所述浅沟槽隔离与源 /漏区之间通过介质材料隔离。
3.根据权利要求 2所述的半导体器件， 所述介质材料包括 SiOF、 SiC0H、 Si0、 SiC0、 SiC0N、 PSG以及 BPSG中的任一种或多种的组合。
4. 根据权利要求 2所述的半导体器件， 所述源 /漏区的顶部为金 属硅化物， 则所述介质材料位于所述金属硅化物和浅沟槽隔离之间。
5.根据权利要求 1所述的半导体器件， 其中， 在所述第一晶种层 的上方有浅沟槽隔离侧墙， 所述浅沟槽隔离侧墙自对准于所述浅沟槽 隔离的侧壁， 且至少部分位于所述源 /漏区内。
6.根据权利要求 5所述的半导体器件， 所述浅沟槽隔离侧墙由 Si02、 Si3N4、 SiON中的任一种或多种的组合形成。
7.根据权利要求 1所述的半导体器件， 所述第一晶种层的厚度为 5_20nm。
8.根据权利要求 1至 7中任一项所述的半导体器件， 所述源 /漏区 进一步包括应力层和第二晶种层， 所述应力层位于所述栅堆叠与第一 晶种层之间， 所述第二晶种层位于应力层的底部。
9. 根据权利要求 8所述的半导体器件， 对于 pMOSFET, 所述应力 层包括外延生长的 SiGe , 对于 nMOSFET, 所述应力层包括外延生长的 Si : C o
10. 一种制造如权利要求 1所述的半导体器件的方法， 包括： 提供半导体衬底； 在所述半导体衬底上形成浅沟槽隔离， 所述浅沟槽隔离形成至少 一个半导体开口区；
在所述浅沟槽隔离的上方形成氮化物层以保护所述浅沟槽隔离； 在所述半导体开口区内形成栅堆叠和以及所述栅堆叠两侧的源 / 漏区， 所述栅堆叠包括栅介质层和栅极导体层， 所述源 /漏区包括相 对分布于所述栅堆叠的两侧、 且与所述浅沟槽隔离邻接的第一晶种 层；
去除所述浅沟槽隔离上方的氮化物层；
其中， 去除所述氮化物层后， 所述浅沟槽隔离的上表面高于或足 够接近于所述栅介质层的上表面。
11. 根据权利要求 10所述的方法， 其中， 在所述半导体衬底上形 成浅沟槽隔离， 包括：
在所述半导体衬底上形成垫氧化层；
在所述垫氧化层上形成第一氮化物层；
刻蚀预形成浅沟槽隔离位置处的所述垫氧化层、 第一氮化物层以 及半导体衬底， 以形成浅沟槽隔离凹槽；
在所述浅沟槽隔离凹槽中形成介质材料；
进行平坦化处理至所述第一氮化物层的顶部露出。
12. 根据权利要求 11所述的方法， 其中， 所述氮化物层包括第二 氮化物层， 则在所述浅沟槽隔离的上方形成氮化物层包括：
对所述浅沟槽隔离进行回刻至所述第一氮化物层的上表面下方； 在所述第一氮化物层上形成第二氮化物层；
在所述第二氮化物层上形成多晶硅层；
对所述多晶硅进行平坦化处理至所述第二氮化物层的顶部； 利用光刻胶掩膜覆盖所述浅沟槽隔离上方的多晶硅层， 并对所述 开口区中的第一氮化物层和第二氮化物层进行刻蚀至所述垫氧化层 露出；
去除所述多晶硅层。
13. 根据权利要求 12所述的方法， 其中， 形成第二氮化物层的方 法为高密度等离子体淀积。
14. 根据权利要求 10至 13中任一项所述的方法， 在形成栅堆叠和 以及所述栅堆叠两侧的源 /漏区之前， 进一步包括： 自对准所述浅沟槽隔离的侧壁形成浅沟槽隔离侧墙； 所述浅沟槽 隔离侧墙至少一部分位于所述源 /漏区内。
15. 根据权利要求 14所述的方法， 形成浅沟槽隔离侧墙包括： 淀积氧化物层和第三氮化物层；
选择性刻蚀所述第三氮化物层和氧化物层以在所述浅沟槽隔离 的侧壁形成浅沟槽隔离侧墙。
16. 根据权利要求 14所述的方法， 其中， 形成栅堆叠包括： 在所述开口区内形成栅介质层；
在所述栅介质层上形成栅极导体层；
对所述栅极导体层进行刻蚀以形成栅堆叠；
环绕所述栅堆叠形成栅极侧墙。
17. 根据权利要求 15所述的方法， 其中， 形成源 /漏区包括： 以所述栅极侧墙和浅沟槽隔离侧墙为界， 向下刻蚀所述栅介质层 和半导体衬底， 以形成源 /漏凹槽；
以所述源 /漏凹槽靠近所述浅沟槽隔离的侧壁为第一晶种层， 以 所述源 /漏凹槽的底部为第二晶种层， 外延形成应力层。
18. 根据权利要求 17所述的方法， 其中， 对 pMOSFET , 应力层为 SiGe , 对 nMOSFET, 应力层为 Si : C。
19. 根据权利要求 14所述的方法， 在形成所述浅沟槽隔离侧墙之 后， 进一步包括：
在所述栅堆叠的宽度方向上， 将与浅沟槽隔离相邻的浅沟槽隔离 侧墙去除。
20. 根据权利要求 14所述的方法，在形成源 /漏区后，进一步包括: 将所述浅沟槽隔离侧墙去除。
PCT/CN2011/075127 2010-09-29 2011-06-01 半导体器件及其制造方法 WO2012041071A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/379,081 US20120261759A1 (en) 2010-09-29 2011-06-01 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201010299028.1 2010-09-29
CN201010299028.1A CN102437183B (zh) 2010-09-29 2010-09-29 半导体器件及其制造方法

Publications (1)

Publication Number Publication Date
WO2012041071A1 true WO2012041071A1 (zh) 2012-04-05

Family

ID=45891883

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2011/075127 WO2012041071A1 (zh) 2010-09-29 2011-06-01 半导体器件及其制造方法

Country Status (3)

Country Link
US (1) US20120261759A1 (zh)
CN (1) CN102437183B (zh)
WO (1) WO2012041071A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8546219B2 (en) * 2011-10-13 2013-10-01 International Business Machines Corporation Reducing performance variation of narrow channel devices
US20140065819A1 (en) * 2012-09-03 2014-03-06 Intermolecular, Inc. Methods and Systems for Low Resistance Contact Formation
CN103779224A (zh) * 2012-10-23 2014-05-07 中国科学院微电子研究所 Mosfet的制造方法
CN103811347B (zh) * 2012-11-13 2018-03-06 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
US9853154B2 (en) * 2014-01-24 2017-12-26 Taiwan Semiconductor Manufacturing Company Ltd. Embedded source or drain region of transistor with downward tapered region under facet region
KR20150105866A (ko) * 2014-03-10 2015-09-18 삼성전자주식회사 스트레서를 갖는 반도체 소자 및 그 형성 방법
CN107180868A (zh) * 2016-03-11 2017-09-19 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6239472B1 (en) * 1998-09-01 2001-05-29 Philips Electronics North America Corp. MOSFET structure having improved source/drain junction performance
US20080006884A1 (en) * 2006-05-24 2008-01-10 Atsushi Yagishita Semiconductor device and method of manufacturing the same
CN101369598A (zh) * 2007-08-15 2009-02-18 台湾积体电路制造股份有限公司 半导体结构

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5817560A (en) * 1996-09-12 1998-10-06 Advanced Micro Devices, Inc. Ultra short trench transistors and process for making same
JP3519662B2 (ja) * 2000-03-14 2004-04-19 松下電器産業株式会社 半導体装置及びその製造方法
JP2001319978A (ja) * 2000-05-01 2001-11-16 Toshiba Corp 半導体装置及びその製造方法
DE10052208C2 (de) * 2000-10-20 2002-11-28 Advanced Micro Devices Inc Verfahren zur Herstellung eines Feldeffekttransistors mittels einer Justiertechnologie auf der Grundlage von Seitenwandabstandselementen
FR2821483B1 (fr) * 2001-02-28 2004-07-09 St Microelectronics Sa Procede de fabrication d'un transistor a grille isolee et a architecture du type substrat sur isolant, et transistor correspondant
DE10246718A1 (de) * 2002-10-07 2004-04-22 Infineon Technologies Ag Feldeffekttransistor mit lokaler Source-/Drainisolation sowie zugehöriges Herstellungsverfahren
US6828630B2 (en) * 2003-01-07 2004-12-07 International Business Machines Corporation CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture
US7285466B2 (en) * 2003-08-05 2007-10-23 Samsung Electronics Co., Ltd. Methods of forming metal oxide semiconductor (MOS) transistors having three dimensional channels
US7075150B2 (en) * 2003-12-02 2006-07-11 International Business Machines Corporation Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique
KR100729923B1 (ko) * 2005-03-31 2007-06-18 주식회사 하이닉스반도체 스텝 ｓｔｉ 프로파일을 이용한 낸드 플래쉬 메모리 소자의트랜지스터 형성방법
US7525160B2 (en) * 2005-12-27 2009-04-28 Intel Corporation Multigate device with recessed strain regions
US7772071B2 (en) * 2006-05-17 2010-08-10 Chartered Semiconductor Manufacturing Ltd. Strained channel transistor and method of fabrication thereof
US7482656B2 (en) * 2006-06-01 2009-01-27 International Business Machines Corporation Method and structure to form self-aligned selective-SOI
JP2007335594A (ja) * 2006-06-14 2007-12-27 Renesas Technology Corp 半導体装置およびその製造方法
US7485544B2 (en) * 2006-08-02 2009-02-03 Micron Technology, Inc. Strained semiconductor, devices and systems and methods of formation
US20080157200A1 (en) * 2006-12-27 2008-07-03 International Business Machines Corporation Stress liner surrounded facetless embedded stressor mosfet
US8536619B2 (en) * 2007-02-05 2013-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Strained MOS device and methods for forming the same
US7759199B2 (en) * 2007-09-19 2010-07-20 Asm America, Inc. Stressor for engineered strain on channel
EP2217670A4 (en) * 2007-10-31 2011-07-13 3M Innovative Properties Co COMPOSITION, METHOD AND METHOD FOR POLISHING A WAFER
JP2009152394A (ja) * 2007-12-20 2009-07-09 Toshiba Corp 半導体装置及びその製造方法
US20100032759A1 (en) * 2008-08-11 2010-02-11 International Business Machines Corporation self-aligned soi schottky body tie employing sidewall silicidation
US8030173B2 (en) * 2009-05-29 2011-10-04 Freescale Semiconductor, Inc. Silicon nitride hardstop encapsulation layer for STI region
CN102456739A (zh) * 2010-10-28 2012-05-16 中国科学院微电子研究所 半导体结构及其形成方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6239472B1 (en) * 1998-09-01 2001-05-29 Philips Electronics North America Corp. MOSFET structure having improved source/drain junction performance
US20080006884A1 (en) * 2006-05-24 2008-01-10 Atsushi Yagishita Semiconductor device and method of manufacturing the same
CN101369598A (zh) * 2007-08-15 2009-02-18 台湾积体电路制造股份有限公司 半导体结构

Also Published As

Publication number Publication date
CN102437183B (zh) 2015-02-25
CN102437183A (zh) 2012-05-02
US20120261759A1 (en) 2012-10-18

Similar Documents

Publication Publication Date Title
US8106456B2 (en) SOI transistors having an embedded extension region to improve extension resistance and channel strain characteristics
JP4982958B2 (ja) 半導体装置とその製造方法
JP4744812B2 (ja) 上昇されたソース／ドレーン構造を有するｍｏｓトランジスタ及びこの製造方法
US8236640B2 (en) Method of fabricating a semiconductor device having gate finger elements extended over a plurality of isolation regions formed in the source and drain regions
US7122410B2 (en) Polysilicon line having a metal silicide region enabling linewidth scaling including forming a second metal silicide region on the substrate
KR100639679B1 (ko) 매립 절연막을 구비하는 트랜지스터의 제조방법 및 그에의하여 제조된 트랜지스터
WO2012041071A1 (zh) 半导体器件及其制造方法
JP2003017710A (ja) ２重ゲート／２重チャネルｍｏｓｆｅｔ
WO2012041064A1 (zh) 一种半导体结构及其制造方法
WO2011147062A1 (zh) 半导体结构及其制造方法
WO2014063381A1 (zh) Mosfet的制造方法
US9660030B2 (en) Replacement gate electrode with a self-aligned dielectric spacer
JP4134001B2 (ja) 半導体装置の製造方法
JP2008500721A (ja) 平面デュアルゲート半導体装置
JP5286416B2 (ja) 半導体装置およびその製造方法
JP2007317796A (ja) 半導体装置および半導体装置の製造方法
JP2005332993A (ja) 半導体装置および半導体装置の製造方法
JP2009111046A (ja) 半導体装置および半導体装置の製造方法
US6884669B2 (en) Hatted polysilicon gate structure for improving salicide performance and method of forming the same
JP2009117621A (ja) 半導体装置及びその製造方法
JP2000049348A (ja) エレベ―テッドソ―ス・ドレイン構造を有する半導体装置及びその製造方法
KR100549006B1 (ko) 완전한 실리사이드 게이트를 갖는 모스 트랜지스터 제조방법
US6798028B2 (en) Field effect transistor with reduced gate delay and method of fabricating the same
JP2007173356A (ja) 半導体装置およびその製造方法
US6727151B2 (en) Method to fabricate elevated source/drain structures in MOS transistors

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13379081

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11827967

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11827967

Country of ref document: EP

Kind code of ref document: A1