CN102832133B - 在体硅上制备独立双栅FinFET的方法 - Google Patents

在体硅上制备独立双栅FinFET的方法 Download PDF

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CN102832133B
CN102832133B CN201210313475.7A CN201210313475A CN102832133B CN 102832133 B CN102832133 B CN 102832133B CN 201210313475 A CN201210313475 A CN 201210313475A CN 102832133 B CN102832133 B CN 102832133B
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silicon
source
silicon nitride
finfet
grid
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CN102832133A (zh
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黄如
樊捷闻
许晓燕
李佳
王润声
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Peking University
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Peking University
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Priority to PCT/CN2012/082797 priority patent/WO2014032361A1/zh
Priority to US14/006,219 priority patent/US9478641B2/en
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Abstract

本发明公开了一种在体硅上制备独立双栅FinFET的方法，主要的工艺流程包括：形成源漏和连接源漏的细条状的图形结构；形成氧化隔离层；形成栅结构和源漏结构；形成金属接触和金属互联。通过采用此方法可以在体硅片上很容易的形成独立双栅FinFET，而且整个工艺流程完全与常规硅基超大规模集成电路制造技术兼容，具有简单、方便、周期短的特点，大大节省了硅片的成本。且采用本发明制备形成的独立双栅FinFET场效应晶体管，能够很好的抑制短沟道效应，并通过独立双栅器件特有的多阈值特点进一步降低器件的功耗。

Description

在体硅上制备独立双栅FinFET的方法
技术领域
本发明涉及一种湿法腐蚀制备场效应晶体管的方法，属于超大规模集成电路制造技术领域。
背景技术
当今半导体制造业在摩尔定律的指导下迅速发展，不断地提高集成电路的性能和集成密度，同时尽可能的减小集成电路的功耗。因此，制备高性能，低功耗的超短沟器件将成为未来半导体制造业的焦点。当进入到22纳米技术节点以后，传统平面场效应晶体管的泄漏电流不断增加，以及日益严重的短沟道效应，漏致势垒降低（DIBL）效应，不能很好的适应半导体制造的发展。为了克服上述一系列问题，一大批新结构半导体器件开始崭露头角，如DoubleGate FET，FinFET，Tri-Gate FET，Gate-all-around(GAA)Nanowire(NW)FET等，逐渐引起广泛的关注。通过多栅结构，能够很好的加强栅对于沟道的控制能力，使得电场线难以从漏端直接穿过沟道到达源端，这样就能大幅度的改善漏致势垒降低效应，减小泄漏电流，并且很好的抑制短沟道效应。正是由于栅结构导致良好的栅控能力，沟道区域不需要像传统平面场效应晶体管一样进行重掺杂来抑制短沟道效应，轻掺杂沟道区域的优势在于减小了散射带来的迁移率的下降，从而使多栅结构器件的迁移率得到大幅度改善。因此，FinFET作为一种新结构器件，将是一个很有潜力的能够替代传统平面场效应晶体管的选择。
Hasimoto等人在1998年的IEDM会议上提出了“folded-channel MOSFETs”的概念。1999年，Heang等人在IEDM会议上公布50nm以下沟道长度的FinFET。这是FinFET第一次采用传统硅工艺，被成功的集成在衬底上。
Hu等人的U.S.Pat.No.6413802中揭开了FinFET的结构，以及制备FinFET的工艺。在SOI衬底上最容易形成FinFET，工艺相对简单，只需要在SOI衬底的顶硅层上光刻刻蚀出Fin条形状，然后再经过一系列栅工艺，源漏工艺以及后端的介质层和金属互联就可以形成FinFET。但是它的缺点是：（1）工艺成本太高，SOI衬底相当昂贵；（2）需要进行源漏抬升技术，否则源漏的扩展电阻过大导致开态电流过小，器件性能较差；（3）没有体引出，这样就无法通过衬底偏置效应调节阈值电压。在体硅衬底上形成FinFET，避免了源漏扩展电阻过大的问题，同时也使得体端能够加载电压，获得衬底偏置效应，从而可以更加容易的把阈值电压调整到一个更加合适的值。但是它的缺点是：（1）工艺相对复杂，对工艺的控制要求更高，因为需要对FinFET增加一层氧化隔离层，抑制底部平面晶体管的开启，减小泄漏电流；（2）尽管增加了氧化隔离层，但是由于存在除Fin条以外的另外一条从源到漏的电流路径，栅控能力并没有SOI陈地上制备的器件来的出色，导致在超短沟器件中泄漏电流导致的功耗仍然较大。
发明内容
本发明的目的在于提供与常规硅基超大规模集成电路制造技术兼容的在体硅上制备独立双栅FinFET方法。
本发明通过如下技术方案予以实现：一种在体硅上制备独立双栅FinFET方法，包括如下步骤：
a)形成源漏和连接源漏的细条状的图形结构
该步骤主要目的是利用电子束光刻在硬掩膜上形成源漏和连接源漏的细条状图形结构，利用电子束光刻可以使形成的细条状结构宽度20-40纳米左右。
i.在硅衬底上淀积氧化硅、氮化硅作为硬掩膜；
ii通过一次电子束光刻，刻蚀氮化硅、氧化硅工艺，在硬掩膜上形成源漏和连接源漏的细条状的图形结构；
iii.去掉电子束光刻胶；
iv.刻蚀硅工艺，将硬掩膜上的图形结构转移到硅材料上；
b)形成氧化隔离层
该步骤主要目的是在Fin条下面和Fin条两侧衬底表面形成氧化层，使得这层氧化隔离层能够起到抑制了衬底平面晶体管的开启，防止电流从源端通过衬底到达漏端的作用。从而降低泄露电流，降低器件的功耗。
i.淀积一层新的氮化硅；
ii利用各项异性干法刻蚀刻蚀新的氮化硅，在Fin条两侧形成氮化硅侧墙；
iii.利用各项异性干法刻蚀刻蚀Fin条两侧裸露出来的硅衬底；
iv.通过湿法氧化在Fin条下面和Fin条两侧衬底表面形成氧化层；
c)制备栅结构和源漏结构
该步骤主要目的是形成栅结构，其中栅结构需要用电子束光刻来定义，这主要是因为电子束光刻能容易的将栅线条宽度控制在22纳米左右，这是我们需要的沟道长度。而且CMP化学机械抛光使得Fin条两侧的栅结果分离，相互独立，从而得到独立双栅结构的FinFET。
i.湿法腐蚀去掉氮化硅侧墙和氮化硅硬掩膜；
ii热氧化生长一层很薄的栅氧化层；
iii.淀积一层多晶硅作为栅材料；
iv.CMP化学机械抛光，使多晶硅平坦化，并且停止在Fin条顶部氧化硅硬掩膜表面；
v.通过电子束光刻，刻蚀多晶硅栅材料，形成多晶硅栅线条，Fin条两侧的栅线条不连接在一起，相互独立；
vi.通过离子增强化学气相淀积以及回刻，形成氧化硅侧墙；
vii进行离子注入和高温退火，形成源漏结构；
d)形成金属接触和金属互联
该步骤主要目的是引出源漏端和栅端，方便测试和形成大规模电路结构。本发明具有如下技术效果：
首先，在体硅衬底上制备器件大大节省了硅片的成本；其次，利用一种简单的新工艺克服了在体硅衬底上制备FinFET工艺复杂，工艺控制要求高的困难，而整个工艺流程完全与常规硅基超大规模集成电路制造技术兼容；最后，此方法制备形成的独立双栅FinFET场效应晶体管，能够很好的抑制短沟道效应，并通过独立双栅器件特有的多阈值特点进一步降低器件的功耗。这主要有两个原因：一是因为Fin条下面和Fin条两侧衬底表面形成氧化层起到隔离作用，抑制了衬底寄生平面晶体管的开启，防止电流从源端通过衬底到达漏端；二是因为独立双栅结构可以很容易的进行阈值调节，多阈值器件能够在保持高性能的同时进一步降低功耗。
附图说明
图1-12是本发明提出的在体硅上制备独立双栅FinFET方法的工艺流程示意图。工艺流程的简要说明如下：图1为淀积氧化硅氮化硅薄膜作为硬掩膜以后的结构示意图；图2为进行电子束光刻Fin条图形，并通过各项异性干法刻蚀将图形转移到硅衬底上之后的结构示意图；图3为淀积氮化硅刻蚀氮化硅，形成氮化硅侧墙之后的结构示意图；图4为各项异性干法刻蚀硅衬底，使Fin条底下的硅材料裸露出来，以便进行接下来的氧化工艺；图5为通过氧化工艺在Fin条底部形成氧化隔离层之后的结构示意图；图6为图5结构中AA方向上的截面示意图；图7为去掉氮化硅层以后的结构示意图；图8为图7结构中AA方向上的截面示意图；图9为经过栅氧化层淀积，栅材料淀积以及后续的CMP工艺之后的结构示意图；图10为进行电子束光刻栅线条图形，并通过各项异性干法刻蚀将图形转移之后的结构示意图；图11为图10结构中AA方向上的截面示意图；图12为进行侧墙工艺以及源漏注入、退火工艺之后的最终器件结构示意图；
图中：1—硅；2—氧化硅；3—氮化硅；4—多晶硅。
具体实施方式
下面结合附图和具体实施例对本发明进行详细说明，具体给出一实现本发明提出的在体硅上制备独立双栅FinFET的工艺方案，但不以任何方式限制本发明的范围。
根据下列步骤制备Fin条宽度约为20纳米，沟道长度约为32纳米的n型独立双栅FinFET：
1.在硅衬底上低压化学气相沉积氧化硅
2.在氧化硅上低压化学气相沉积氮化硅如图1所示，淀积的氧化硅和氮化硅作为硬掩膜；
3.光学光刻、定义Fin条，在硬掩膜上形成源漏和连接源漏的细条状的图形结构；
4.各项异性干法刻蚀氮化硅；
5.各向异性干法刻蚀氧化硅；
6.各向异性干法刻蚀硅衬底，如图2所示，将硬掩膜上的图形结构转移到硅材料上；
7.在硅衬底上低压化学气相沉积氮化硅
8.各向异性干法刻蚀氮化硅，形成侧墙，如图3所示；
9.各项异性干法刻蚀硅衬底，使Fin条底下的硅材料裸露出来，如图4所示；
10.湿氧氧化在在Fin条下面和Fin条两侧衬底表面形成氧化隔离层，如图5所示；
11.各向同性湿法腐蚀氮化硅，如图7所示；
12.热氧化生长氧化硅，作为栅氧化层；
13.低压化学气相沉积多晶硅作为栅材料；
14.CMP化学机械研磨将多晶硅平坦化，停止在氧化硅硬掩膜层上，如图9所示；
15.电子束光刻定义栅细线条，栅条的宽度为32纳米；
16.各项异性干法刻蚀多晶硅，形成栅细线条，如图10所示，Fin条两侧的栅线条不连接在一起，相互独立；
17.低压化学气相沉积氧化硅作为侧墙材料；
18.各向异性干法刻蚀氧化层，形成侧墙；
19.源漏离子注入，注As，注入能量为50keV，注入剂量为4e15cm-2；
20.RTP退火，1050度，5秒，在氮气氛围下，如图12所示，形成源漏结构；
21.形成金属接触和金属互联，引出源漏端和栅端，形成大规模电路结构。
最后需要注意的是，公布实施方式的目的在于帮助进一步理解本发明，但是本领域的技术人员可以理解：在不脱离本发明及所附的权利要求的精神和范围内，各种替换和修改都是可能的。因此，本发明不应局限于实施例所公开的内容，本发明要求保护的范围以权利要求书界定的范围为准。

Claims (3)

1.一种在体硅上制备独立双栅FinFET的方法，包括如下步骤：
a)形成源漏和连接源漏的细条状的图形结构
i.在硅衬底上淀积氧化硅、氮化硅作为硬掩膜；
ii.通过一次电子束光刻，刻蚀氮化硅、氧化硅工艺，在硬掩膜上形成源漏和连接源漏的细条状的图形结构；
iii.去掉电子束光刻胶；
iv.刻蚀硅工艺，将硬掩膜上的图形结构转移到硅材料上；
b)形成氧化隔离层
i.淀积一层新的氮化硅；
ii.利用各向异性干法刻蚀刻蚀新的氮化硅，在Fin条两侧形成氮化硅侧墙；
iii.利用各向异性干法刻蚀刻蚀Fin条两侧裸露出来的硅衬底；
iv.通过湿法氧化在Fin条下面和Fin条两侧衬底表面形成氧化层；
c)形成栅结构和源漏结构
i.湿法腐蚀去掉氮化硅侧墙和氮化硅硬掩膜；
ii.热氧化生长一层栅氧化层；
iii.淀积一层多晶硅作为栅材料；
iv.CMP化学机械抛光，使多晶硅平坦化，并且停止在Fin条顶部氧化硅硬掩膜表面；
v.通过电子束光刻，刻蚀多晶硅栅材料，形成多晶硅栅线条，Fin条两侧的栅线条不连接在一起，相互独立；
vi.通过离子增强化学气相淀积以及回刻，形成氧化硅侧墙；
vii.进行离子注入和高温退火，形成源漏结构。
2.如权利要求1所述的在体硅上制备独立双栅FinFET的方法，其特征在于：所述步骤c)中，栅氧化层和多晶硅栅材料是High-k栅介质和金属栅材料。
3.如权利要求1所述的在体硅上制备独立双栅FinFET的方法，其特征在于：所述步骤b)中，生长的氧化隔离层完全隔离或者部分隔离Fin条与衬底的连接。
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