CN116632006A - 一种纵向堆叠的栅极自对准反相器集成电路结构 - Google Patents

一种纵向堆叠的栅极自对准反相器集成电路结构 Download PDF

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CN116632006A
CN116632006A CN202310686181.7A CN202310686181A CN116632006A CN 116632006 A CN116632006 A CN 116632006A CN 202310686181 A CN202310686181 A CN 202310686181A CN 116632006 A CN116632006 A CN 116632006A
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pmos
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廖永波
徐丰和
李平
万旭
牛耀都
袁丕根
宋健强
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University of Electronic Science and Technology of China
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Abstract

本发明公开了一种纵向堆叠的栅极自对准反相器集成电路结构，涉及微电子技术和集成电路(IC)领域。基于与传统集成电路堆叠技术的不同，本发明提出一种具有高集成度的垂直围栅器件的堆叠结构，该堆叠结构将反相器的NMOS与PMOS在纵向进行堆叠，NMOS和PMOS的漏极连接在一起，极大的提高了IC集成度，节约芯片面积。此外，该结构采用了栅极对准的方式，该结构栅极区域仅包裹沟道区或沟道区及与其相邻的轻掺杂漂移区，能够极大减小了栅极与重掺杂源漏区域间的寄生电容，使器件频率特性提高。

Description

一种纵向堆叠的栅极自对准反相器集成电路结构
技术领域
本发明涉及微电子技术和集成电路领域。
背景技术
从摩尔定律[1]提出开始，硅基集成电路的发展一直遵循按比例缩小原则[2]。但随着集成电路技术的发展，硅器件尺寸的日益减小，近年来，等比例缩小原则开始面临严峻的挑战，这是由于器件在极小尺寸下，晶体管漏电流升高带来的热效应极大地削减了器件的性能，导致芯片的栅控能力大幅下降。因此，许多科研工作者开始考虑从其他角度改进集成电路，从而延续摩尔定律。
在本发明之前的HVTFET(异质结垂直沟道场效应晶体管)和新型纳米墙NWaFET结构[3-5]，采用纵向设计方案，极大提高了器件的集成度，并通过沟道区重掺杂漂移区轻掺杂的组合结构抑制DIBL效应。HVT以及NWaFET结构通过采用沟道重掺杂的方式，实现了Lch进一步的下降。其比现有的FINFET[6]、GAA[7]具有更短沟道长度Lch，且集成度更高；所以具有更好的特性，由于其占用芯片面积很小，从而在芯片领域具广泛应用前景。
CMOS反相器作为构成数字集成电路最基础的功能单元和数字电子系统中最为典型的器件，具有十分重要的作用。CMOS反相器，它具有较大的噪声容限、极高的输入电阻、极低的静态功耗以及对噪声和干扰不敏感等优点，因此广泛应用于数字集成电路中，是几乎所有数字集成电路设计的核心。
本文提出的一种纵向堆叠的栅极自对准反相器集成电路结构，采用纵向堆叠的方式，将反相器的NMOS与PMOS在纵向进行堆叠，NMOS和PMOS的漏极连接在一起，极大的提高了集成度。此外，该结构采用了栅极对准的方式，该结构栅极区域仅包裹沟道区或沟道区及与其相邻的轻掺杂漂移区，能够极大减小了栅极与重掺杂源漏区域间的寄生电容，使器件频率特性提高。在原理上，本发明仍然沿用了HVTFET和NWaFET结构通过沟道区重掺杂漂移区轻掺杂的组合结构抑制DIBL效应的方法。
参考文献
[1].Moore,Gordon E."Cramming more components onto integratedcircuits".Electronics.Retrieved 2016-07-01.
[2].Thompson S,Packan P,Bohr M.MOS scaling:transistor challenges forthe 21st century.Intel Technology Journal,1998；pp 1-18.
[3].廖永波,李平,唐瑞枫,等.一种新型数字门集成电路的结构[P].中国，发明专利，申请号：CN111048579.1.2020.
[4].李平，唐瑞枫，廖永波等.一种新型DRAM结构及实现方法[P].中国，发明专利，申请号：CN202110252584.1.2021.
[5].廖永波，刘金铭，李平等.一种高集成度纳米墙集成电路结构[P].中国，发明
专利，申请号：CN202210413345.4.2022.
[6].Chenming Hu,Lee W C,Kedzierski J,et al.FinFET-a self-aligneddouble-gate MOSFET scalable to 20nm[J].IEEE Transactions on Electron Devices,2000,
47(12):2320-2325.
[7].J.P.Colinge,M.H.Gao,A.Romano,H.Maes,C.Claeys.Silicon-on-insulator
“gate-all-around”MOS device[C].1990IEEE SOS/SOI TechnologyConference.
Proceedings.Key West,FL,USA:IEEE,1990:137-138..
发明内容
本发明技术方案1为一种纵向堆叠的栅极自对准反相器集成电路结构，如图1所示。在该结构最下方为一个P-Well硅单晶半导体区域101，在该P-Well硅单晶半导体区域101上部形成有NMOS器件的N+型源极区域102；在该N+型源极区域102上方有P型沟道半导体区103；在该P型沟道半导体区103上方是N-型漏极区域104；在该N-型漏极区域104上方是N+型漏极区域105；在NMOS漏极区域105的上方是PMOS器件的P+型漏极区域106；在该P+型漏极区域106上方有P-型漏极区域107；在该P-型漏极区域107上方是N型沟道半导体区108；在该N型沟道半导体区108上方是N+型源极区域109；所述N+型源极区域102包括上部和下部，下部宽于上部，下部的下表面和侧面被P-Well 101包围，在上述NMOS的N+型源极区域102、P型沟道区103、N-型漏极区域104、N+型漏极区域105和PMOS的P+型漏极区域106、P-型漏极区域107、N型沟道区108、P+型源极区域109的侧面设置有沟槽；沟槽的下表面低于NMOS的N+型源极区域102和P型沟道区域103的界面或与之持平；沟槽内填充有栅电极112、栅电极113和绝缘栅介质111；栅电极112的下表面低于PMOS的N型沟道区域108和P-漏极区域107的界面或与之持平，栅电极112的上表面高于PMOS的N型沟道区域108和P+源极区域109的界面或与之持平；栅电极113的下表面低于NMOS的P型沟道区域103和N+源极区域102的界面或与之持平，栅电极113的上表面高于NMOS的P型沟道区域103和N-型漏极区域104的界面或与之持平。栅电极112和113由重掺杂多晶或耐熔金属硅化物或耐熔金属或他们的组合体构成。绝缘栅介质111用于隔离栅电极112、栅电极113和其他半导体区。PMOS和NMOS的共漏电极114、NMOS的源电极115设置于NMOS的N+源极区域102、P型沟道半导体区103、N-漏极区域104、N+漏极区域105和PMOS的P+漏极区域106、P-漏极区域107、N型沟道半导体区108、P+源极区域109的侧面。PMOS和NMOS的漏电极114与NMOS的N+漏极区域105接触，该接触面低于NMOS的N+漏极区域105和PMOS的P+漏极区域106的界面，高于NMOS的N+漏极区域105的下表面；NMOS源电极115与其N+源极区域102接触，该接触面低于NMOS的P型沟道区域103和N+漏极区域102的界面，高于N+源极区域102的下表面。绝缘材料110使得PMOS和NMOS的共漏电极114、NMOS源电极115与NMOS的N+源极区域102、P型沟道半导体区103、N-漏极区域104、N+漏极区域105和PMOS的P+漏极区域106、P-漏极区域107、N型沟道半导体区108、P+源极区域109隔离。
本发明技术方案2为一种纵向堆叠的栅极自对准反相器集成电路结构，如图2所示。在该结构最下方为一个N-Well硅单晶半导体区域201，在该N-Well硅单晶半导体区域201上部形成有PMOS器件的P+型源极区域202；在该P+型源极区域202上方有N型沟道半导体区203；在该N型沟道半导体区203上方是P-型漏极区域204；在该P-型漏极区域204上方是P+型漏极区域205；在PMOS漏极区域205的上方是NMOS器件的N+型漏极区域206；在该N+型漏极区域206上方有漏极区域207；在该N-型漏极区域207上方是P型沟道半导体区208；在该P型沟道半导体区208上方是P+型半导体源极区域209；所述P+源极区域202包括上部和下部，下部宽于上部，下部的下表面和侧面被N-Well 201包围，在上述PMOS的P+源极区域202、N型沟道半导体区203、P-漏极区域204、P+漏极区域205和NMOS的N+漏极区域206、N-漏极区域207、P型沟道半导体区208、N+源极区域209的侧面设置有沟槽；沟槽的下表面低于PMOS的P+源极区域202和N型沟道区203的界面或与之持平；沟槽内填充有栅电极112、栅电极113和绝缘栅介质111；栅电极112的下表面低于NMOS的P型沟道区域208和N-漏极区域207的界面或与之持平，栅电极112的上表面高于NMOS的P型沟道区域208和N+源极区域209的界面或与之持平；栅电极113的下表面低于PMOS的N型沟道区域203和P+源极区域202的界面或与之持平，栅电极113的上表面高于PMOS的N型沟道区域203和P-漏极区域204的界面或与之持平。栅电极112和113由重掺杂多晶或耐熔金属硅化物或耐熔金属或他们的组合体构成。绝缘栅介质111用于隔离栅电极112、栅电极113和其他半导体区。NMOS和PMOS的共漏电极114、PMOS的源电极115设置于PMOS的P+源极区域202、N型沟道半导体区203、P-漏极区域204、P+漏极区域205和NMOS的N+漏极区域206、N-漏极区域207、P型沟道半导体区208、N+源极区域209的侧面。NMOS和PMOS的漏电极114与PMOS的P+漏极区域205接触，该接触面低于PMOS的P+漏极区域205和NMOS的N+漏极区域206的界面，高于PMOS的P+漏极区域205的下表面；PMOS源电极115与其P+源极区域202接触，该接触面低于PMOS的N型沟道区域203和P+源极区域202的界面，高于P+源极区域202的下表面。绝缘材料110使得NMOS和PMOS的共漏电极114、PMOS的源电极115与PMOS的P+源极区域202、N型沟道半导体区203、P-漏极区域204、P+漏极区域205和NMOS的N+漏极区域206、N-漏极区域207、P型沟道半导体区208、N+源极区域209隔离。
进一步的，所述P型沟道半导体区(103,208)的厚度小于12nm。
进一步的，所述P型沟道半导体区(103,208)的掺杂浓度比N-漏极区域(104,207)高2个数量级以上。
进一步的，所述N型沟道半导体区(108,203)的厚度小于12nm。
进一步的，所述N型沟道半导体区(108,203)的掺杂浓度比P-漏极区域(107,204)高2个数量级以上。
进一步的，所述栅电极(112,113)设置于半导体区的一个侧面的全部区域、或半导体区的一个侧面的局部区域，如图5(a)所示。
进一步的，所述栅电极(112,113)设置于半导体区的两个侧面的全部区域、或半导体区的一个侧面的全部区域及另一个侧面的局部区域，如图5(b)所示。
进一步的，所述栅电极(112,113)设置于半导体区的三个侧面全部区域的、或半导体区的两个侧面的全部区域及另一个侧面的局部区域，如图5(c)所示。
进一步的，所述栅电极(112,113)设置于半导体区的四个侧面的全部区域、或半导体区的三个侧面的全部区域及最后一个侧面的局部区域，如图5(d)所示。
进一步的，所有层厚度范围在1nm-100nm之间，掺杂浓度范围为1e14cm-3-1e20 cm-3。
进一步的，当沟道半导体区(103,108,203,208)、重掺杂漏区(105,106,205,206)、半导体衬底或阱(101,201)为单晶硅时，所述轻掺杂漏区(104,107,204,207)为窄禁带赝晶半导体材料(如SiGe赝晶)；当沟道半导体区(103,108,203,208)、重掺杂漏区(105,106,205,206)、半导体衬底或阱(101,201)为宽禁带单晶半导体材料(如SiC单晶或GaN单晶)时，所述轻掺杂漏区(104,107,204,207))为赝晶Si半导体材料。在轻掺杂漏区使用赝晶可以在沟道半导体(104,108,204,208)中引入应力，增加载流子的迁移率。进一步的，当沟道半导体区(103,108,203,208)、重掺杂漏区(105,106,205,206)、半导体衬底或阱(101,201)为单晶硅时，所述重掺杂源区(102,202)为单晶Si或窄禁带单晶半导体材料,重掺杂源区(109,209)为多晶Ge、多晶SiGe、多晶TWS(碲镉汞)、多晶InP、多晶InSb等窄禁带半导体多晶材料，或上述材料的组合；
当沟道半导体区(103,108,203,208)、重掺杂漏区(105,106,205,206)、半导体衬底或阱(101,201)为宽禁带单晶半导体材料(如SiC单晶或GaN单晶)时，所述重掺杂源区(102,202)为单晶Si半导体材料,重掺杂源区(109,209)为多晶Si半导体材料。若重掺杂源区(109,209)采用窄禁带赝晶半导体材料，由于晶格失配产生应力，致使其厚度必须很薄，源区金属合金时可能穿透赝晶源区，造成器件失效。重掺杂源区采用多晶材料，没有晶格失配的问题，故其厚度可以较厚，从而避免了赝晶带来的问题。
本发明提出的一种纵向堆叠的栅极自对准反相器集成电路结构，将反相器的NMOS和PMOS在垂直方向堆叠，采用本发明结构可以显著提高了IC的集成度。此外，本发明并用了栅极对准的方式，栅极区域仅包裹沟道区或沟道区及与其相邻的轻掺杂漂移区。该结构栅极区域仅包裹沟道区或沟道区及与其相邻的轻掺杂漂移区，极大减小了栅极与重掺杂源漏区域间的寄生电容，显著提高了器件的频率特性。在原理上，本发明仍然沿用了HVT和NWaFET结构通过沟道区重掺杂漂移区轻掺杂的组合结构抑制DIBL效应的方法。
附图说明
图1为本发明一种纵向堆叠的栅极自对准反相器集成电路结构上方PMOS下方NMOS单元的斜视剖视图。
图2为本发明一种纵向堆叠的栅极自对准反相器集成电路结构上方NMOS下方PMOS单元的斜视剖视图。
图3为本发明一种纵向堆叠的栅极自对准反相器集成电路结构上方PMOS下方NMOS单元俯视图。
图4为本发明一种纵向堆叠的栅极自对准反相器集成电路结构上方NMOS下方PMOS单元俯视图。
图5为本发明一种纵向堆叠的栅极自对准反相器集成电路结构单元槽栅电极112和槽栅电极113形成不同栅宽(Wch)单元的俯视图。
图6为CMOS反相器的原理图。
图7为采用本发明构成的反相器实际结构图。
具体实施方式
实施例1：一种纵向堆叠的栅极自对准反相器集成电路结构
为了能清楚的展现本发明一种纵向堆叠的栅极自对准反相器集成电路结构，本实施例展示了实际反相器的电极引接方法。如图6所示，是一种基本的CMOS反相器原理图，PMOS的源极接VCC，NMOS的源极接GND，PMOS和NMOS的栅极共同作为输入Vin，漏极共同作为输出Vout。
如图7所示，为采用本发明结构组成的CMOS反相器PMOS的源极接VCC，NMOS的源极接GND，PMOS和NMOS的栅极共同作为输入Vin，漏极共同作为输出Vout，与图6原理图相对应。

Claims (9)

1.一种纵向堆叠的栅极自对准反相器集成电路结构，其特征在于，在该结构最下方为一个P-Well硅单晶半导体区域101，在该P-Well硅单晶半导体区域101上部形成有NMOS器件的N+型源极区域102；在该N+型源极区域102上方有P型沟道半导体区103；在该P型沟道半导体区103上方是N-型漏极区域104；在该N-型漏极区域104上方是N+型漏极区域105；在NMOS漏极区域105的上方是PMOS器件的P+型漏极区域106；在该P+型漏极区域106上方有P-型漏极区域107；在该P-型漏极区域107上方是N型沟道半导体区108；在该N型沟道半导体区108上方是N+型源极区域109；所述N+型源极区域102包括上部和下部，下部宽于上部，下部的下表面和侧面被P-Well 101包围，在上述NMOS的N+型源极区域102、P型沟道区103、N-型漏极区域104、N+型漏极区域105和PMOS的P+型漏极区域106、P-型漏极区域107、N型沟道区108、P+型源极区域109的侧面设置有沟槽；沟槽的下表面低于NMOS的N+型源极区域102和P型沟道区域103的界面或与之持平；沟槽内填充有栅电极112、栅电极113和绝缘栅介质111；栅电极112的下表面低于PMOS的N型沟道区域108和P-漏极区域107的界面或与之持平，栅电极112的上表面高于PMOS的N型沟道区域108和P+源极区域109的界面或与之持平；栅电极113的下表面低于NMOS的P型沟道区域103和N+源极区域102的界面或与之持平，栅电极113的上表面高于NMOS的P型沟道区域103和N-型漏极区域104的界面或与之持平。栅电极112和113由重掺杂多晶或耐熔金属硅化物或耐熔金属或他们的组合体构成。绝缘栅介质111用于隔离栅电极112、栅电极113和其他半导体区。PMOS和NMOS的共漏电极114、NMOS的源电极115设置于NMOS的N+源极区域102、P型沟道半导体区103、N-漏极区域104、N+漏极区域105和PMOS的P+漏极区域106、P-漏极区域107、N型沟道半导体区108、P+源极区域109的侧面。PMOS和NMOS的漏电极114与NMOS的N+漏极区域105接触，该接触面低于NMOS的N+漏极区域105和PMOS的P+漏极区域106的界面，高于NMOS的N+漏极区域105的下表面；NMOS源电极115与其N+源极区域102接触，该接触面低于NMOS的P型沟道区域103和N+漏极区域102的界面，高于N+源极区域102的下表面。绝缘材料110使得PMOS和NMOS的共漏电极114、NMOS源电极115与NMOS的N+源极区域102、P型沟道半导体区103、N-漏极区域104、N+漏极区域105和PMOS的P+漏极区域106、P-漏极区域107、N型沟道半导体区108、P+源极区域109隔离。
2.如权利要求1所述的一种纵向堆叠的栅极自对准反相器集成电路结构，其特征在于，NMOS的P型沟道半导体区103的厚度小于12nm，PMOS的N型沟道半导体区108的厚度小于12nm。
3.如权利要求1所述的一种纵向堆叠的栅极自对准反相器集成电路结构，其特征在于，NMOS的P型沟道半导体区103的掺杂浓度比N-漏极区域104高2个数量级以上，PMOS的N型沟道半导体区108的掺杂浓度比P-漏极区域107高2个数量级以上。
4.一种纵向堆叠的栅极自对准反相器集成电路结构，其特征在于，在该结构最下方为一个N-Well硅单晶半导体区域201，在该N-Well硅单晶半导体区域201上部形成有PMOS器件的P+型源极区域202；在该P+型源极区域202上方有N型沟道半导体区203；在该N型沟道半导体区203上方是P-型漏极区域204；在该P-型漏极区域204上方是P+型漏极区域205；在PMOS漏极区域205的上方是NMOS器件的N+型漏极区域206；在该N+型漏极区域206上方有漏极区域207；在该N-型漏极区域207上方是P型沟道半导体区208；在该P型沟道半导体区208上方是P+型半导体源极区域209；所述P+源极区域202包括上部和下部，下部宽于上部，下部的下表面和侧面被N-Well 201包围，在上述PMOS的P+源极区域202、N型沟道半导体区203、P-漏极区域204、P+漏极区域205和NMOS的N+漏极区域206、N-漏极区域207、P型沟道半导体区208、N+源极区域209的侧面设置有沟槽；沟槽的下表面低于PMOS的P+源极区域202和N型沟道区203的界面或与之持平；沟槽内填充有栅电极112、栅电极113和绝缘栅介质111；栅电极112的下表面低于NMOS的P型沟道区域208和N-漏极区域207的界面或与之持平，栅电极112的上表面高于NMOS的P型沟道区域208和N+源极区域209的界面或与之持平；栅电极113的下表面低于PMOS的N型沟道区域203和P+源极区域202的界面或与之持平，栅电极113的上表面高于PMOS的N型沟道区域203和P-漏极区域204的界面或与之持平。栅电极112和113由重掺杂多晶或耐熔金属硅化物或耐熔金属或他们的组合体构成。绝缘栅介质111用于隔离栅电极112、栅电极113和其他半导体区。NMOS和PMOS的共漏电极114、PMOS的源电极115设置于PMOS的P+源极区域202、N型沟道半导体区203、P-漏极区域204、P+漏极区域205和NMOS的N+漏极区域206、N-漏极区域207、P型沟道半导体区208、N+源极区域209的侧面。NMOS和PMOS的漏电极114与PMOS的P+漏极区域205接触，该接触面低于PMOS的P+漏极区域205和NMOS的N+漏极区域206的界面，高于PMOS的P+漏极区域205的下表面；PMOS源电极115与其P+源极区域202接触，该接触面低于PMOS的N型沟道区域203和P+源极区域202的界面，高于P+源极区域202的下表面。绝缘材料110使得NMOS和PMOS的共漏电极114、PMOS的源电极115与PMOS的P+源极区域202、N型沟道半导体区203、P-漏极区域204、P+漏极区域205和NMOS的N+漏极区域206、N-漏极区域207、P型沟道半导体区208、N+源极区域209隔离。
5.如权利要求4所述的一种纵向堆叠的栅极自对准反相器集成电路结构，其特征在于，PMOS的N型沟道半导体区203的厚度小于12nm，NMOS的P型沟道半导体区208的厚度小于12nm。
6.如权利要求4所述的一种纵向堆叠的栅极自对准反相器集成电路结构，其特征在于，PMOS的N型沟道半导体区203的掺杂浓度比P-漏极区域204高2个数量级以上，NMOS的P型沟道半导体区208的掺杂浓度比N-漏极区域207高2个数量级以上。
7.如权利要求1-6所述的任意一种纵向堆叠的栅极自对准反相器集成电路结构，当沟道半导体区(103,108,203,208)、重掺杂漏区(105,106,205,206)、半导体衬底或阱(101,201)为单晶硅时，所述轻掺杂漏区(104,107,204,207)为窄禁带赝晶半导体材料(如SiGe赝晶)，所述重掺杂源区(102,202)为单晶Si或窄禁带单晶半导体材料,重掺杂源区(109,209)为多晶Ge、多晶SiGe、多晶TWS(碲镉汞)、多晶InP、多晶InSb等窄禁带半导体多晶材料，或上述材料的组合；当沟道半导体区(103,108,203,208)、重掺杂漏区(105,106,205,206)、半导体衬底或阱(101,201)为宽禁带单晶半导体材料(如SiC单晶或GaN单晶)时，所述轻掺杂漏区(104,107,204,207)为赝晶Si半导体材料，所述重掺杂源区(102,202)为单晶Si半导体材料,重掺杂源区(109,209)为多晶Si半导体材料。
8.如权利要求1-6所述的任意一种纵向堆叠的栅极自对准反相器集成电路结构，其特征在于，所有层厚度的范围在1nm-100nm之间，掺杂浓度范围为1e14cm-3-1e20 cm-3。
9.如权利要求1-6所述的任意一种纵向堆叠的栅极自对准反相器集成电路结构，其特征在于，所述栅电极(112,113)设置于半导体区的一个侧面的全部区域、或半导体区的一个侧面的局部区域；进一步的，所述栅电极(112,113)设置于半导体区的两个侧面的全部区域、或半导体区的一个侧面的全部区域及另一个侧面的局部区域；进一步的，所述栅电极(112,113)设置于半导体区的三个侧面全部区域的、或半导体区的两个侧面的全部区域及与另一个侧面的局部区域；进一步的，所述栅电极(112,113)设置于半导体区的四个侧面的全部区域、或半导体区的三个侧面的全部区域及最后一个侧面的局部区域。
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