CN116705796A - 一种纵向堆叠的栅极自对准hvtfet集成电路结构 - Google Patents

一种纵向堆叠的栅极自对准hvtfet集成电路结构 Download PDF

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CN116705796A
CN116705796A CN202310686176.6A CN202310686176A CN116705796A CN 116705796 A CN116705796 A CN 116705796A CN 202310686176 A CN202310686176 A CN 202310686176A CN 116705796 A CN116705796 A CN 116705796A
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drain region
drain
nmos
pmos
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廖永波
徐丰和
李平
牛耀都
宋健强
袁丕根
万旭
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University of Electronic Science and Technology of China
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Abstract

本发明公开了一种纵向堆叠的栅极自对准HVTFET集成电路结构，涉及微电子技术和集成电路(IC)领域。本发明一种纵向堆叠的栅极自对准HVTFET集成电路结构，该堆叠结构将NMOS与PMOS在垂直方向上堆叠，在器件之间有SiO2隔离，使得堆叠的器件可以单独使用。该结构能够提高IC集成度，节约芯片面积。此外，该堆叠结构同时采用了栅极对准的方式，本发明结构的栅极区域仅包裹沟道区或沟道区及与其相邻的轻掺杂漂移区，能够极大减小了栅极与重掺杂源漏区域间的寄生电容，使器件频率特性提高。

Description

一种纵向堆叠的栅极自对准HVTFET集成电路结构
技术领域
本发明涉及微电子技术和集成电路领域。
背景技术
近年来，集成电路技术快速发展，从摩尔定律[1]提出开始，集成电路的发展一直遵循按比例缩小原则[2]。随着器件尺寸的日益减小，等比例缩小原则开始面临严峻的挑战，这是由于器件在极小尺寸下，晶体管漏电流升高带来的热效应极大地削减了器件的性能，导致芯片的栅控能力大幅下降。因此，许多科研工作者开始考虑从其他角度改进集成电路，从而延续摩尔定律。
FinFET，即鳍式场效应晶体管，该项技术由加州大学伯克利分校的胡正明教授于2000年正式发表论文提出[3]。FinFET的主要特点是，沟道区域是一个被栅极包裹的鳍状半导体，沿源漏方向的鳍的长度，为沟道长度。与传统的平面CMOS相比，FinFET的半环栅鳍形结构增加了栅极对沟道的控制面积，使得栅控能力大大增强，从而可以有效抑制短沟效应，减小亚阈值漏电流。TSMC于2018年开始，正式量产7nm工艺节点的芯片，最近几年开发出5nm、3nm工艺。
虽然FinFET在CMOS工艺中已经具备许多的优点，但在5nm节点以后其将面临一系列的挑战：例如栅极距和金属截距进一步缩小，亚阈值斜率增加意味着亚阈区摆幅增大而栅漏电流很大，以及鳍高度的增加将导致寄生电容增。为此多家公司提出了环绕式栅极(Gate-All-Around)晶体管结构[4]。其栅极和源漏不再维持鳍形的样子，而是柱体结构垂直穿过栅极，因此栅极可以从四面包裹沟道，延续了FinFET立体结构的思路，从而最大程度地实现栅极对沟道区的控制，更好控制短沟道及DIBL等效应，实现更大的功耗和面积优势。根据IRDS给出的数据，5nm FINFET的栅长实际为18nm，后续的工艺节点下，沟道长度Lch也很难按比例缩小，直至2028年，Lch缩小到9.6nm，此后，Lch将不再能缩小。
在本发明之前的HVTFET(异质结垂直沟道场效应晶体管)和新型纳米墙NWaFET结构[5-7]，采用纵向设计方案，极大提高了器件的集成度，并通过沟道区重掺杂漂移区轻掺杂的组合结构抑制DIBL效应。HVT以及NWaFET结构通过采用沟道重掺杂的方式，实现了Lch进一步的下降。其比现有的FINFET、GAA、VGAA具有更短沟道长度Lch，且集成度更高。
本文提出的一种纵向堆叠的栅极自对准HVTFET集成电路结构，堆叠结构将NMOS与PMOS在垂直方向上堆叠，在器件之间有SiO2隔离，使得堆叠的器件可以单独使用。该结构能够提高IC集成度，节约芯片面积。此外，该堆叠结构采用了栅极对准的方式，该结构栅极区域仅包裹沟道区或沟道区及与其相邻的轻掺杂漂移区，能够极大减小了栅极与重掺杂源漏区域间的寄生电容，使器件频率特性提高。在原理上，本发明仍然沿用了HVTFET和NWaFET结构通过沟道区重掺杂漂移区轻掺杂的组合结构抑制DIBL效应的方法。
参考文献
[1].Moore,Gordon E."Cramming more components onto integratedcircuits".Electronics.Retrieved 2016-07-01.
[2].Thompson S,Packan P,Bohr M.MOS scaling:transistor challenges forthe 21st century.Intel Technology Journal,1998；pp 1-18.
[3].Chenming Hu,Lee W C,Kedzierski J,et al.FinFET-a self-aligneddouble-gate MOSFET scalable to 20nm[J].IEEE Transactions on Electron Devices,2000,47(12):2320-2325.
[4].J.P.Colinge,M.H.Gao,A.Romano,H.Maes,C.Claeys.Silicon-on-insulator“gate-all-around”MOS device[C].1990IEEE SOS/SOI TechnologyConference.Proceedings.Key West,FL,USA:IEEE,1990:137-138..
[5].廖永波,李平,唐瑞枫,等.一种新型数字门集成电路的结构[P].中国，发明专利，申请号：CN111048579.1.2020.
[6].李平，唐瑞枫，廖永波等.一种新型DRAM结构及实现方法[P].中国，发明专利，申请号：CN202110252584.1.2021.
[7].廖永波，刘金铭，李平等.一种高集成度纳米墙集成电路结构[P].中国，发明专利，申请号：CN202210413345.4.2022.
发明内容
本发明技术方案1为一种纵向堆叠的栅极自对准HVTFET集成电路结构，如图1所示。在该结构最下方为一个P-Well硅单晶半导体区域101，在该P-Well硅单晶半导体区域101上部形成有NMOS器件的N+漏极区域102；在该N+漏极区域102上方有漏极区域103；在该N-漏极区域103上方是P型沟道半导体区104；在该P型沟道半导体区104上方是N+半导体源极区域105；在NMOS源极区域105的上方是一层SiO2隔离层111；在隔离层111的上方是一层N+型半导体区域106；在该N+型区域106的上方是PMOS器件的P+漏极区域107；在该P+漏极区域107上方有P-漏极区域108；在该P-漏极区域108上方是N型沟道半导体区109；在该N型沟道半导体区109上方是N+半导体源极区域110；所述N+漏极区域102包括上部和下部，下部宽于上部，下部的下表面和侧面被P-Well 101包围，在上述NMOS的N+漏极区域102、N-漏极区域103、P型沟道半导体区104、N+源极区域105、SiO2隔离层111、N+型半导体区域106和PMOS的P+漏极区域107、P-漏极区域108、N型沟道半导体区109、P+源极区域110的侧面设置有沟槽；沟槽的下表面低于NMOS的N+漏极区域102和N-漏极区域103的界面或与之持平；沟槽内填充有栅电极114、栅电极115和绝缘栅介质112；栅电极114的下表面低于PMOS的N型沟道区域109和P-漏极区域108的界面或与之持平，栅电极114的上表面高于PMOS的N型沟道区域109和P+源极区域110的界面或与之持平；栅电极115的下表面低于NMOS的P型沟道区域104和N-漏极区域103的界面或与之持平，栅电极115的上表面高于NMOS的P型沟道区域104和N+源极区域105的界面或与之持平。栅电极114和115由重掺杂多晶或耐熔金属硅化物或耐熔金属或他们的组合体构成。绝缘栅介质112用于隔离栅电极114、栅电极115和其他半导体区。PMOS漏电极116、NMOS的源电极117和漏电极118设置于NMOS的N+漏极区域102、N-漏极区域103、P型沟道半导体区104、N+源极区域105、SiO2隔离层111、N+型半导体区域106和PMOS的P+漏极区域107、P-漏极区域108、N型沟道半导体区109、P+源极区域110的侧面。PMOS漏电极116与其P+漏极区域107接触，该接触面低于PMOS的P+漏极区域107和P-漏极区域108的界面，高于P+漏极区域107的下表面；NMOS源电极117与其N+源极区域105接触，该接触面低于NMOS的N+源极区域105和SiO2隔离层111的界面，高于NMOS的N+源极区域105的下表面；NMOS漏电极118与其N+漏极区域102接触，该接触面低于NMOS的N-漏极区域103和N+漏极区域102的界面，高于N+漏极区域102的下表面。绝缘材料112使得PMOS漏电极116、NMOS源电极117、NMOS漏电极118与NMOS的N+漏极区域102、N-漏极区域103、P型沟道半导体区104、N+源极区域105、SiO2隔离层111、N+型半导体区域106和PMOS的P+漏极区域107、P-漏极区域108、N型沟道半导体区109、P+源极区域110隔离。
本发明技术方案2为一种纵向堆叠的栅极自对准HVTFET集成电路结构，如图2所示。在该结构最下方为一个P-Well硅单晶半导体区域101，在该P-Well硅单晶半导体区域101上部形成有NMOS器件的N+半导体源极区域105；在该N+源极区域105上方有P型沟道半导体区104；在该P型沟道半导体区104上方是漏极区域103；在该漏极区域103上方是N+漏极区域102；在NMOS漏极区域102的上方是一层SiO2隔离层111；在隔离层111的上方是一层N+型半导体区域106；在该N+型区域106的上方是PMOS器件的P+漏极区域107；在该P+漏极区域107上方有P-漏极区域108；在该P-漏极区域108上方是N型沟道半导体区109；在该N型沟道半导体区109上方是N+半导体源极区域110；所述N+源极区域105包括上部和下部，下部宽于上部，下部的下表面和侧面被P-Well 101包围，在上述NMOS的N+源极区域105、P型沟道半导体区104、N-漏极区域103、N+漏极区域102、SiO2隔离层111、N+型半导体区域106和PMOS的P+漏极区域107、P-漏极区域108、N型沟道半导体区109、P+源极区域110的侧面设置有沟槽；沟槽的下表面低于NMOS的N+源极区域105和P型沟道区域104的界面或与之持平；沟槽内填充有栅电极114、栅电极115和绝缘栅介质112；栅电极114的下表面低于PMOS的N型沟道区域109和P-漏极区域108的界面或与之持平，栅电极114的上表面高于PMOS的N型沟道区域109和P+源极区域110的界面或与之持平；栅电极115的下表面低于NMOS的P型沟道区域104和N+源极区域105的界面或与之持平，栅电极115的上表面高于NMOS的P型沟道区域104和N-漏极区域104的界面或与之持平。栅电极114和115由重掺杂多晶或耐熔金属硅化物或耐熔金属或他们的组合体构成。绝缘栅介质112用于隔离栅电极114、栅电极115和其他半导体区。PMOS漏电极116、NMOS的漏电极117和源电极118设置于NMOS的N+源极区域105、P型沟道半导体区104、N-漏极区域103、N+漏极区域102、SiO2隔离层111、N+型半导体区域106和PMOS的P+漏极区域107、P-漏极区域108、N型沟道半导体区109、P+源极区域110的侧面。PMOS漏电极116与其P+漏极区域107接触，该接触面低于PMOS的P+漏极区域107和P-漏极区域108的界面，高于P+漏极区域107的下表面；NMOS漏电极117与其N+漏极区域102接触，该接触面低于NMOS的N+漏极区域102和SiO2隔离层的界面，高于N+漏极区域102的下表面NMOS源电极118与其N+源极区域105接触，该接触面低于NMOS的N+源极区域105和P型沟道区域104的界面，高于NMOS的N+源极区域105的下表面。绝缘材料112使得PMOS漏电极116、NMOS漏电极117、NMOS源电极118与NMOS的N+源极区域105、P型沟道半导体区104、N-漏极区域103、N+漏极区域102、SiO2隔离层111、N+型半导体区域106和PMOS的P+漏极区域107、P-漏极区域108、N型沟道半导体区109、P+源极区域110隔离。
本发明技术方案3为一种纵向堆叠的栅极自对准HVTFET集成电路结构，如图3所示。在该结构最下方为一个N-Well硅单晶半导体区域201，在该N-Well硅单晶半导体区域201上部形成有PMOS器件的P+漏极区域202；在该P+漏极区域202上方有P-漏极区域203；在该P-漏极区域203上方是N型沟道半导体区204；在该N型沟道半导体区204上方是P+半导体源极区域205；在PMOS源极区域205的上方是一层SiO2隔离层111；在隔离层111的上方是一层P+型半导体区域206；在该P+型区域206的上方是NMOS器件的硅单晶N+漏极区域207；在该N+漏极区域207上方有N-漏极区域208；在该N-漏极区域208上方是P型沟道半导体区209；在该P型沟道半导体区209上方是N+半导体源极区域210；所述P+漏极区域202包括上部和下部，下部宽于上部，下部的下表面和侧面被N-Well 201包围，在上述PMOS的P+漏极区域202、P-漏极区域203、N型沟道半导体区204、P+源极区域205、SiO2隔离层111、P型半导体区域206和NMOS的N+漏极区域207、N-漏极区域208、P型沟道半导体区209、N+源极区域210的侧面设置有沟槽；沟槽的下表面低于PMOS的P+漏极区域202和P-漏极区域203的界面或与之持平；沟槽内填充有栅电极114、栅电极115和绝缘栅介质112；栅电极114的下表面低于NMOS的P型沟道区域209和N-漏极区域208的界面或与之持平，栅电极114的上表面高于NMOS的P型沟道区域209和N+源极区域210的界面或与之持平；栅电极115的下表面低于PMOS的N型沟道区域204和P-漏极区域203的界面或与之持平，栅电极115的上表面高于PMOS的N型沟道区域204和P+源极区域205的界面或与之持平。栅电极114和115由重掺杂多晶或耐熔金属硅化物或耐熔金属或他们的组合体构成。绝缘栅介质112用于隔离栅电极114、栅电极115和其他半导体区。NMOS漏电极116、PMOS的源电极117和漏电极118设置于PMOS的P+漏极区域202、P-漏极区域203、N型沟道半导体区204、P+源极区域205、SiO2隔离层111、P+型半导体区域206和NMOS的N+漏极区域207、N-漏极区域208、P型沟道半导体区209、N+源极区域210的侧面。NMOS漏电极116与其N+漏极区域207接触，该接触面低于NMOS的N+漏极区域207和N-漏极区域208的界面，高于N+漏极区域207的下表面；PMOS源电极117与其P+源极区域205接触，该接触面低于PMOS的P+源极区域205和SiO2隔离层111的界面，高于PMOS的P+源极区域205的下表面；PMOS漏电极118与其P+漏极区域202接触，该接触面低于PMOS的P-漏极区域203和P+漏极区域202的界面，高于P+漏极区域202的下表面。绝缘材料112使得NMOS漏电极116、PMOS源电极117、PMOS漏电极118与PMOS的P+漏极区域202、P-漏极区域203、N型沟道半导体区204、P+源极区域205、SiO2隔离层111、P+型半导体区域206和NMOS的N+漏极区域207、N-漏极区域208、P型沟道半导体区209、N+源极区域210隔离。
本发明技术方案4为一种纵向堆叠的栅极自对准HVTFET集成电路结构，如图4所示。在该结构最下方为一个N-Well硅单晶半导体区域201，在该N-Well硅单晶半导体区域201上部形成有PMOS器件的P+源极区域205；在该P+源极区域205上方有N型沟道半导体区204；在该N型沟道半导体区204上方是P-漏极区域203；在该P-漏极区域203上方是P+漏极区域202；在PMOS漏极区域202的上方是一层SiO2隔离层111；在隔离层111的上方是一层P+型半导体区域206；在该P+型区域206的上方是NMOS器件的硅单晶N+漏极区域207；在该N+漏极区域207上方有N-漏极区域208；在该N-漏极区域208上方是P型沟道半导体区209；在该P型沟道半导体区209上方是N+半导体源极区域210；所述P+漏极区域202包括上部和下部，下部宽于上部，下部的下表面和侧面被N-Well 201包围，在上述PMOS的P+源极区域205、N型沟道半导体区204、P-漏极区域203、P+漏极区域202、SiO2隔离层111、P型半导体区域206和NMOS的N+漏极区域207、N-漏极区域208、P型沟道半导体区209、N+源极区域210的侧面设置有沟槽；沟槽的下表面低于PMOS的P+源极区域205和N型沟道半导体区204的界面或与之持平；沟槽内填充有栅电极114、栅电极115和绝缘栅介质112；栅电极114的下表面低于NMOS的P型沟道区域209和N-漏极区域208的界面或与之持平，栅电极114的上表面高于NMOS的P型沟道区域209和N+源极区域210的界面或与之持平；栅电极115的下表面低于PMOS的N型沟道区域204和P+源极区域205的界面或与之持平，栅电极115的上表面高于N型沟道区域204和P-漏极区域203的界面或与之持平。栅电极114和115由重掺杂多晶或耐熔金属硅化物或耐熔金属或他们的组合体构成。绝缘栅介质112用于隔离栅电极114、栅电极115和其他半导体区。NMOS漏电极116、PMOS的漏电极117和源电极118设置于PMOS的P+源极区域205、N型沟道半导体区204、P-漏极区域203、P+漏极区域202、SiO2隔离层111、P型半导体区域206和NMOS的N+漏极区域207、N-漏极区域208、P型沟道半导体区209、N+源极区域210的侧面。NMOS漏电极116与其N+漏极区域207接触，该接触面低于NMOS的N+漏极区域207和N-漏极区域208的界面，高于N+漏极区域207的下表面；PMOS漏电极117与其P+漏极区域202接触，该接触面低于PMOS的P+漏极区域202和SiO2隔离层111的界面，高于PMOS的P+漏极区域202的下表面；PMOS源电极118与其P+源极区域205接触，该接触面低于PMOS的P+源极区域205和N型沟道区域204的界面，高于P+源极区域205的下表面。绝缘材料112使得NMOS漏电极116、PMOS漏电极117、PMOS源电极118与P+源极区域205、N型沟道半导体区204、P-漏极区域203、P+漏极区域202、SiO2隔离层111、P型半导体区域206和NMOS的N+漏极区域207、N-漏极区域208、P型沟道半导体区209、N+源极区域210隔离。
进一步的，所述P型沟道半导体区(104,209)的厚度小于12nm。
进一步的，所述P型沟道半导体区(104,209)的掺杂浓度比N-漏极区域(103,208)高2个数量级以上。
进一步的，所述N型沟道半导体区(109,204)的厚度小于12nm。
进一步的，所述N型沟道半导体区(109,204)的掺杂浓度比P-漏极区域(108,203)高2个数量级以上。
进一步的，所述栅电极(114,115)设置于半导体区的一个侧面的全部区域、或半导体区的一个侧面的局部区域，如图7(a)所示。
进一步的，所述栅电极(114,115)设置于半导体区的两个侧面的全部区域、或半导体区的一个侧面的全部区域及另一个侧面的局部区域，如图7(b)所示。
进一步的，所述栅电极(114,115)设置于半导体区的三个侧面全部区域的、或半导体区的两个侧面的全部区域及另一个侧面的局部区域，如图7(c)所示。
进一步的，所述栅电极(114,115)设置于半导体区的四个侧面的全部区域、或半导体区的三个侧面的全部区域及最后一个侧面的局部区域，如图7(d)所示。
进一步的，所有层厚度的范围在1nm-100nm之间，掺杂浓度范围1e14cm-3-1e20 cm-3。
进一步的，当沟道半导体区(104,109,204,209)、重掺杂漏区(102,107,202,207)、半导体衬底或阱(101,201)为单晶硅时，所述轻掺杂漏区(103,108,203,208)为窄禁带赝晶半导体材料(如SiGe赝晶)；当沟道半导体区(104,109,204,209)、重掺杂漏区(102,107,202,207)、半导体衬底或阱(101,201)为宽禁带单晶半导体材料(如SiC单晶或GaN单晶)时，所述轻掺杂漏区(103,108,203,208为赝晶Si半导体材料。在轻掺杂漏区使用赝晶可以在沟道半导体(104,108,204,208)中引入应力，增加载流子的迁移率。
进一步的，当沟道半导体区(104,109,204,209)、重掺杂漏区(102,107,202,207)、半导体衬底或阱(101,201)为单晶硅时，所述重掺杂源区(105,205)为单晶Si或窄禁带单晶半导体材料，重掺杂源区(110,210)为多晶Ge、多晶SiGe、多晶TWS(碲镉汞)、多晶InP、多晶InSb等窄禁带半导体多晶材料，或上述材料的组合；当沟道半导体区(104,109,204,209)、重掺杂漏区(102,107,202,207)、半导体衬底或阱(101,201)为宽禁带单晶半导体材料(如SiC单晶或GaN单晶)时，所述重掺杂源区(105,205)为单晶Si半导体材料，重掺杂源区(110,210)为多晶Si半导体材料。若重掺杂源区(110,210)采用窄禁带赝晶半导体材料，由于晶格失配产生应力，致使其厚度必须很薄，源区金属合金时可能穿透赝晶源区，造成器件失效。重掺杂源区采用多晶材料，没有晶格失配的问题，故其厚度可以较厚，从而避免了赝晶带来的问题。
本发明提出的一种纵向堆叠的栅极自对准HVTFET集成电路结构，将NMOS和PMOS在垂直方向堆叠，在器件之间有SiO2隔离，采用本发明结构可以显著提高了IC的集成度，节约芯片面积。此外，本发明并用了栅极对准的方式，栅极区域仅包裹沟道区或沟道区及与其相邻的轻掺杂漂移区。该结构栅极区域仅包裹沟道区或沟道区及与其相邻的轻掺杂漂移区，极大减小了栅极与重掺杂源漏区域间的寄生电容，显著提高了器件的频率特性。在原理上，本发明仍然沿用了HVT和NWaFET结构通过沟道区重掺杂漂移区轻掺杂的组合结构抑制DIBL效应的方法。
附图说明
图1为本发明一种纵向堆叠的栅极自对准HVTFET集成电路结构，上方NMOS、下方PMOS(从上至下为源区、沟道区、漏区)单元的斜视剖视图。
图2为本发明一种纵向堆叠的栅极自对准HVTFET集成电路结构，上方NMOS、下方PMOS(从上至下为漏区、沟道区、源区)单元的斜视剖视图。
图3为本发明一种纵向堆叠的栅极自对准HVTFET集成电路结构，上方PMOS、下方NMOS(从上至下为源区、沟道区、漏区)单元的斜视剖视图。
图4为本发明一种纵向堆叠的栅极自对准HVTFET集成电路结构，上方PMOS、下方NMOS(从上至下为漏区、沟道区、源区)单元的斜视剖视图。
图5为本发明一种纵向堆叠的栅极自对准HVTFET集成电路结构上方NMOS下方PMOS单元俯视图。
图6为本发明一种纵向堆叠的栅极自对准HVTFET集成电路结构上方PMOS下方NMOS单元俯视图。
图7为本发明一种纵向堆叠的栅极自对准HVTFET集成电路结构单元槽栅电极112和槽栅电极113形成不同栅宽(Wch)单元的俯视图。
图8为本发明一种纵向堆叠的栅极自对准HVTFET集成电路结构单元的一种工艺流程，实现了技术方案1所述的结构。
具体实施方式
实施例1：为清晰理解本发明一种纵向堆叠的栅极自对准HVTFET集成电路结构，本实施例具体介绍实现技术方案1所述结构的工艺流程。
第一步，如图8(a)所示，为一个P型衬底；
第二步，如图8(b)所示，在P型衬底上外延生长一层N+型半导体区域和一层N-型半导体区域；
第三步，如图8(c)所示，刻蚀栅槽，沉积SiO2，通过化学机械抛光(CMP)进行平坦化处理；
第四步，如图8(d)所示，外延生长一层P型半导体区域，栅槽区域SiO2上方不会生长；
第五步，如图8(e)所示，沉积一层薄SiO2层后，再沉积多晶硅，之后通过化学机械抛光(CMP)进行平坦化处理；
第六步，如图8(f)所示，外延生长一层N+型半导体区域，栅槽区域多晶硅上方不会生长；
第七步，如图8(g)所示，沉积SiO2，通过化学机械抛光(CMP)进行平坦化处理；
第八步，如图8(h)所示，再N+区域深注入一层氧离子，再进行退火，在N+半导体区域将形成一层SiO2；
第九步，如图8(i)所示，外延生长一层P+型半导体区域和P-型半导体区域，栅槽区域SiO2上方不会生长；
第十步，如图8(j)所示，沉积SiO2，通过化学机械抛光(CMP)进行平坦化处理；
第十一步，如图8(k)所示，外延生长一层N型半导体区域，栅槽区域SiO2上方不会生长；
第十二步，如图8(l)所示，沉积一层薄SiO2层后，再沉积多晶硅，之后通过化学机械抛光(CMP)进行平坦化处理；
第十三步，如图8(m)所示，外延生长一层P+型半导体区域，栅槽区域多晶硅上方不会生长；
第十四步，如图8(n)所示，沉积SiO2，通过化学机械抛光(CMP)进行平坦化处理；
第十五步，如图8(o)所示，刻槽，填充绝缘物，在绝缘物中开孔，填充金属引出电极。

Claims (11)

1.一种纵向堆叠的栅极自对准HVTFET集成电路结构，其特征在于，在该结构最下方为一个P-Well硅单晶半导体区域101，在该P-Well硅单晶半导体区域101上部形成有NMOS器件的硅单晶N+漏极区域102；在该N+漏极区域102上方有N-硅单晶或窄禁带赝晶漏极区域103；在该N-漏极区域103上方是P型沟道半导体区104；在该P型沟道半导体区104上方是N+硅单晶或窄禁带单晶半导体源极区域105；在NMOS源极区域105的上方是一层SiO2隔离层111；在隔离层111的上方是一层N+型半导体区域106；在该N+型区域106的上方是PMOS器件的硅单晶P+漏极区域107；在该P+漏极区域107上方有P-硅单晶或窄禁带赝晶漏极区域108；在该P-漏极区域108上方是N型沟道半导体区109；在该N型沟道半导体区109上方是N+硅单晶或窄禁带单晶半导体源极区域110；所述N+漏极区域102包括上部和下部，下部宽于上部，下部的下表面和侧面被P-Well 101包围，在上述NMOS的N+漏极区域102、N-漏极区域103、P型沟道半导体区104、N+源极区域105、SiO2隔离层111、N+型半导体区域106和PMOS的P+漏极区域107、P-漏极区域108、N型沟道半导体区109、P+源极区域110的侧面设置有沟槽；沟槽的下表面低于NMOS的N+漏极区域102和N-漏极区域103的界面或与之持平；沟槽内填充有栅电极114、栅电极115和绝缘栅介质112；栅电极114的下表面低于PMOS的N沟道区域109和P-漏极区域108的界面或与之持平，栅电极114的上表面高于PMOS的N沟道区域109和P+源极区域110的界面或与之持平；栅电极115的下表面低于NMOS的P沟道区域104和N-漏极区域103的界面或与之持平，栅电极115的上表面高于NMOS的P沟道区域104和N+源极区域105的界面或与之持平。栅电极114和115由重掺杂多晶或耐熔金属硅化物或耐熔金属或他们的组合体构成。绝缘栅介质112用于隔离栅电极114、栅电极115和其他半导体区。PMOS漏电极116、NMOS的源电极117和漏电极118设置于NMOS的N+漏极区域102、N-漏极区域103、P型沟道半导体区104、N+源极区域105、SiO2隔离层111、N+型半导体区域106和PMOS的P+漏极区域107、P-漏极区域108、N型沟道半导体区109、P+源极区域110的侧面。PMOS漏电极116与其P+漏极区域107接触，该接触面低于PMOS的P+漏极区域107和P-漏极区域108的界面，高于P+漏极区域107的下表面；NMOS源电极117与其N+源极区域105接触，该接触面低于NMOS的N+源极区域105和SiO2隔离层111的界面，高于NMOS的N+源极区域105的下表面；NMOS漏电极118与其N+漏极区域102接触，该接触面低于NMOS的N-漏极区域103和N+漏极区域102的界面，高于N+漏极区域102的下表面。绝缘材料112使得PMOS漏电极116、NMOS源电极117、NMOS漏电极118与NMOS的N+漏极区域102、N-漏极区域103、P型沟道半导体区104、N+源极区域105、SiO2隔离层111、N+型半导体区域106和PMOS的P+漏极区域107、P-漏极区域108、N型沟道半导体区109、P+源极区域110隔离。
2.一种纵向堆叠的栅极自对准HVTFET集成电路结构，其特征在于，在该结构最下方为一个P-Well硅单晶半导体区域101，在该P-Well硅单晶半导体区域101上部形成有NMOS器件的N+半导体源极区域105；在该N+源极区域105上方有P型沟道半导体区104；在该P型沟道半导体区104上方是漏极区域103；在该漏极区域103上方是N+漏极区域102；在NMOS漏极区域102的上方是一层SiO2隔离层111；在隔离层111的上方是一层N+型半导体区域106；在该N+型区域106的上方是PMOS器件的P+漏极区域107；在该P+漏极区域107上方有P-漏极区域108；在该P-漏极区域108上方是N型沟道半导体区109；在该N型沟道半导体区109上方是N+半导体源极区域110；所述N+源极区域105包括上部和下部，下部宽于上部，下部的下表面和侧面被P-Well 101包围，在上述NMOS的N+源极区域105、P型沟道半导体区104、N-漏极区域103、N+漏极区域102、SiO2隔离层111、N+型半导体区域106和PMOS的P+漏极区域107、P-漏极区域108、N型沟道半导体区109、P+源极区域110的侧面设置有沟槽；沟槽的下表面低于NMOS的N+源极区域105和P沟道区域104的界面或与之持平；沟槽内填充有栅电极114、栅电极115和绝缘栅介质112；栅电极114的下表面低于PMOS的N沟道区域109和P-漏极区域108的界面或与之持平，栅电极114的上表面高于PMOS的N沟道区域109和P+源极区域110的界面或与之持平；栅电极115的下表面低于NMOS的P沟道区域104和N+源极区域105的界面或与之持平，栅电极115的上表面高于NMOS的P沟道区域104和N-漏极区域104的界面或与之持平。栅电极114和115由重掺杂多晶或耐熔金属硅化物或耐熔金属或他们的组合体构成。绝缘栅介质112用于隔离栅电极114、栅电极115和其他半导体区。PMOS漏电极116、NMOS的漏电极117和源电极118设置于NMOS的N+源极区域105、P型沟道半导体区104、N-漏极区域103、N+漏极区域102、SiO2隔离层111、N+型半导体区域106和PMOS的P+漏极区域107、P-漏极区域108、N型沟道半导体区109、P+源极区域110的侧面。PMOS漏电极116与其P+漏极区域107接触，该接触面低于PMOS的P+漏极区域107和P-漏极区域108的界面，高于P+漏极区域107的下表面；NMOS漏电极117与其N+漏极区域102接触，该接触面低于NMOS的N+漏极区域102和SiO2隔离层的界面，高于N+漏极区域102的下表面NMOS源电极118与其N+源极区域105接触，该接触面低于NMOS的N+源极区域105和P沟道区域104的界面，高于NMOS的N+源极区域105的下表面。绝缘材料112使得PMOS漏电极116、NMOS漏电极117、NMOS源电极118与NMOS的N+源极区域105、P型沟道半导体区104、N-漏极区域103、N+漏极区域102、SiO2隔离层111、N+型半导体区域106和PMOS的P+漏极区域107、P-漏极区域108、N型沟道半导体区109、P+源极区域110隔离。
3.如权利要求1-2所述的任意一种纵向堆叠的栅极自对准HVTFET集成电路结构，其特征在于，NMOS的P型沟道半导体区104的厚度小于12nm，PMOS的N型沟道半导体区109的厚度小于12nm。
4.如权利要求1-2所述的任意一种纵向堆叠的栅极自对准HVTFET集成电路结构，其特征在于，NMOS的P型沟道半导体区104的掺杂浓度比N-漏极区域103高2个数量级以上，PMOS的N型沟道半导体区109的掺杂浓度比P-漏极区域108高2个数量级以上。
5.一种纵向堆叠的栅极自对准HVTFET集成电路结构，其特征在于，在该结构最下方为一个N-Well硅单晶半导体区域201，在该N-Well硅单晶半导体区域201上部形成有PMOS器件的P+漏极区域202；在该P+漏极区域202上方有P-漏极区域203；在该P-漏极区域203上方是N型沟道半导体区204；在该N型沟道半导体区204上方是P+半导体源极区域205；在PMOS源极区域205的上方是一层SiO2隔离层111；在隔离层111的上方是一层P+型半导体区域206；在该P+型区域206的上方是NMOS器件的硅单晶N+漏极区域207；在该N+漏极区域207上方有N-漏极区域208；在该N-漏极区域208上方是P型沟道半导体区209；在该P型沟道半导体区209上方是N+半导体源极区域210；所述P+漏极区域202包括上部和下部，下部宽于上部，下部的下表面和侧面被N-Well201包围，在上述PMOS的P+漏极区域202、P-漏极区域203、N型沟道半导体区204、P+源极区域205、SiO2隔离层111、P型半导体区域206和NMOS的N+漏极区域207、N-漏极区域208、P型沟道半导体区209、N+源极区域210的侧面设置有沟槽；沟槽的下表面低于PMOS的P+漏极区域202和P-漏极区域203的界面或与之持平；沟槽内填充有栅电极114、栅电极115和绝缘栅介质112；栅电极114的下表面低于NMOS的P沟道区域209和N-漏极区域208的界面或与之持平，栅电极114的上表面高于NMOS的P沟道区域209和N+源极区域210的界面或与之持平；栅电极115的下表面低于PMOS的N沟道区域204和P-漏极区域203的界面或与之持平，栅电极115的上表面高于PMOS的N沟道区域204和P+源极区域205的界面或与之持平。栅电极114和115由重掺杂多晶或耐熔金属硅化物或耐熔金属或他们的组合体构成。绝缘栅介质112用于隔离栅电极114、栅电极115和其他半导体区。NMOS漏电极116、PMOS的源电极117和漏电极118设置于PMOS的P+漏极区域202、P-漏极区域203、N型沟道半导体区204、P+源极区域205、SiO2隔离层111、P+型半导体区域206和NMOS的N+漏极区域207、N-漏极区域208、P型沟道半导体区209、N+源极区域210的侧面。NMOS漏电极116与其N+漏极区域207接触，该接触面低于NMOS的N+漏极区域207和N-漏极区域208的界面，高于N+漏极区域207的下表面；PMOS源电极117与其P+源极区域205接触，该接触面低于PMOS的P+源极区域205和SiO2隔离层111的界面，高于PMOS的P+源极区域205的下表面；PMOS漏电极118与其P+漏极区域202接触，该接触面低于PMOS的P-漏极区域203和P+漏极区域202的界面，高于P+漏极区域202的下表面。绝缘材料112使得NMOS漏电极116、PMOS源电极117、PMOS漏电极118与PMOS的P+漏极区域202、P-漏极区域203、N型沟道半导体区204、P+源极区域205、SiO2隔离层111、P+型半导体区域206和NMOS的N+漏极区域207、N-漏极区域208、P型沟道半导体区209、N+源极区域210隔离。
6.一种纵向堆叠的栅极自对准HVTFET集成电路结构，其特征在于，在该结构最下方为一个N-Well硅单晶半导体区域201，在该N-Well硅单晶半导体区域201上部形成有PMOS器件的P+源极区域205；在该P+源极区域205上方有N型沟道半导体区204；在该N型沟道半导体区204上方是P-漏极区域203；在该P-漏极区域203上方是P+漏极区域202；在PMOS漏极区域202的上方是一层SiO2隔离层111；在隔离层111的上方是一层P+型半导体区域206；在该P+型区域206的上方是NMOS器件的硅单晶N+漏极区域207；在该N+漏极区域207上方有N-漏极区域208；在该N-漏极区域208上方是P型沟道半导体区209；在该P型沟道半导体区209上方是N+半导体源极区域210；所述P+漏极区域202包括上部和下部，下部宽于上部，下部的下表面和侧面被N-Well 201包围，在上述PMOS的P+源极区域205、N型沟道半导体区204、P-漏极区域203、P+漏极区域202、SiO2隔离层111、P型半导体区域206和NMOS的N+漏极区域207、N-漏极区域208、P型沟道半导体区209、N+源极区域210的侧面设置有沟槽；沟槽的下表面低于PMOS的P+源极区域205和N型沟道半导体区204的界面或与之持平；沟槽内填充有栅电极114、栅电极115和绝缘栅介质112；栅电极114的下表面低于NMOS的P沟道区域209和N-漏极区域208的界面或与之持平，栅电极114的上表面高于NMOS的P沟道区域209和N+源极区域210的界面或与之持平；栅电极115的下表面低于PMOS的N沟道区域204和P+源极区域205的界面或与之持平，栅电极115的上表面高于N沟道区域204和P-漏极区域203的界面或与之持平。栅电极114和115由重掺杂多晶或耐熔金属硅化物或耐熔金属或他们的组合体构成。绝缘栅介质112用于隔离栅电极114、栅电极115和其他半导体区。NMOS漏电极116、PMOS的漏电极117和源电极118设置于PMOS的P+源极区域205、N型沟道半导体区204、P-漏极区域203、P+漏极区域202、SiO2隔离层111、P型半导体区域206和NMOS的N+漏极区域207、N-漏极区域208、P型沟道半导体区209、N+源极区域210的侧面。NMOS漏电极116与其N+漏极区域207接触，该接触面低于NMOS的N+漏极区域207和N-漏极区域208的界面，高于N+漏极区域207的下表面；PMOS漏电极117与其P+漏极区域202接触，该接触面低于PMOS的P+漏极区域202和SiO2隔离层111的界面，高于PMOS的P+漏极区域202的下表面；PMOS源电极118与其P+源极区域205接触，该接触面低于PMOS的P+源极区域205和N沟道区域204的界面，高于P+源极区域205的下表面。绝缘材料112使得NMOS漏电极116、PMOS漏电极117、PMOS源电极118与P+源极区域205、N型沟道半导体区204、P-漏极区域203、P+漏极区域202、SiO2隔离层111、P型半导体区域206和NMOS的N+漏极区域207、N-漏极区域208、P型沟道半导体区209、N+源极区域210隔离。
7.如权利要求5-6所述的任意一种纵向堆叠的栅极自对准HVTFET集成电路结构，其特征在于，PMOS的N型沟道半导体区204的厚度小于12nm，NMOS的P型沟道半导体区209的厚度小于12nm。
8.如权利要求5-6所述的任意一种纵向堆叠的栅极自对准HVTFET集成电路结构，其特征在于，PMOS的N型沟道半导体区204的掺杂浓度比P-漏极区域203高2个数量级以上，NMOS的P型沟道半导体区209的掺杂浓度比N-漏极区域208高2个数量级以上。
9.如权利要求1-8所述的任意一种纵向堆叠的栅极自对准HVTFET集成电路结构，当沟道半导体区(104,109,204,209)、重掺杂漏区(102,107,202,207)、半导体衬底或阱(101,201)为单晶硅时，所述轻掺杂漏区(103,108,203,208)为窄禁带赝晶半导体材料(如SiGe赝晶)，所述重掺杂源区(105,205)为单晶Si或窄禁带单晶半导体材料,重掺杂源区(110,210)为多晶Ge、多晶SiGe、多晶TWS(碲镉汞)、多晶InP、多晶InSb等窄禁带半导体多晶材料，或上述材料的组合；当沟道半导体区(104,109,204,209)、重掺杂漏区(102,107,202,207)、半导体衬底或阱(101,201)为宽禁带单晶半导体材料(如SiC单晶或GaN单晶)时，所述轻掺杂漏区(103,108,203,208)为赝晶Si半导体材料，所述重掺杂源区(105,205)为单晶Si半导体材料,重掺杂源区(110,210)为多晶Si半导体材料。
10.如权利要求1-8所述的任意一种纵向堆叠的栅极自对准HVTFET集成电路结构，其特征在于，所有层厚度的范围在1nm-100nm之间，掺杂浓度范围为1e14cm-3-1e20 cm-3。
11.如权利要求1-8所述的任意一种纵向堆叠的栅极自对准HVTFET集成电路结构，其特征在于，所述栅电极(114,115)设置于半导体区的一个侧面的全部区域、或半导体区的一个侧面的局部区域；进一步的，所述栅电极(114,115)设置于半导体区的两个侧面的全部区域、或半导体区的一个侧面的全部区域及另一个侧面的局部区域；进一步的，所述栅电极(114,115)设置于半导体区的三个侧面全部区域的、或半导体区的两个侧面的全部区域及与另一个侧面的局部区域；进一步的，所述栅电极(114,115)设置于半导体区的四个侧面的全部区域、或半导体区的三个侧面的全部区域及最后一个侧面的局部区域。
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