WO2013026213A1 - 半导体器件结构及其制作方法 - Google Patents
半导体器件结构及其制作方法 Download PDFInfo
- Publication number
- WO2013026213A1 WO2013026213A1 PCT/CN2011/079040 CN2011079040W WO2013026213A1 WO 2013026213 A1 WO2013026213 A1 WO 2013026213A1 CN 2011079040 W CN2011079040 W CN 2011079040W WO 2013026213 A1 WO2013026213 A1 WO 2013026213A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- gate
- conductive
- dielectric
- layer
- spacer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 125000006850 spacer group Chemical group 0.000 claims description 104
- 238000000034 method Methods 0.000 claims description 61
- 238000002955 isolation Methods 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 21
- 238000005520 cutting process Methods 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000003989 dielectric material Substances 0.000 claims description 11
- 239000011810 insulating material Substances 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims 1
- 238000010292 electrical insulation Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 134
- 239000011229 interlayer Substances 0.000 description 23
- 238000005530 etching Methods 0.000 description 21
- 230000015572 biosynthetic process Effects 0.000 description 11
- 239000004020 conductor Substances 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000012545 processing Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000012876 topography Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- -1 Si 3 N 4 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Definitions
- the present invention relates to the field of semiconductors, and more particularly to a fin-equipped semiconductor device structure and a method of fabricating the same, in which a gate electrode pattern can be formed with high quality. Background technique
- FinFETs FinFETs
- FIG. 1 A perspective view of an example FinFET is shown in FIG.
- the FinFET includes: a bulk Si semiconductor substrate 101; a fin 102 formed on the bulk Si semiconductor substrate 101; a gate electrode 103 intersecting the fin 102, and a gate between the gate electrode 103 and the fin 102 a dielectric layer 104; and an isolation region (such as Si0 2 ) 105.
- a conductive channel is formed in the fin 102, specifically in the three sidewalls (left, right side wall and top wall in the figure) of the fin 102, as shown by the arrow in FIG. Shown. That is, a portion of the fin 102 under the gate electrode 103 serves as a channel region, and a source region and a drain region are respectively located on both sides of the channel region.
- the FinFET is formed on a bulk semiconductor substrate, but the FinFET can also be formed on a substrate of another form such as an SOI (Semiconductor-on-insulator) substrate.
- the FET shown in FIG. 1 is also referred to as a 3-gate FET because it can create a channel on all three sidewalls of the fin 102.
- a 2-gate FET is formed by providing an isolation layer (e.g., nitride) between the top wall of the fin 102 and the gate electrode 103, at which time no channel is created on the top wall of the fin 102.
- FIG. 2 shows a photograph of the topography of the fin 102 and the gate electrode 103 in the actually fabricated FinFET.
- FIG. 3 shows a photograph of the topography of the fin 102 and the gate electrode 103 in the actually fabricated FinFET.
- An object of the present invention is to provide a semiconductor device structure and a method of fabricating the same to overcome the above problems in the prior art.
- a method of fabricating a semiconductor device structure comprising: providing a semiconductor substrate; forming a fin in a first direction on the semiconductor substrate; and crossing the first direction on the semiconductor substrate Forming a gate line in two directions, the gate line intersecting the fin via the gate dielectric layer; forming a dielectric spacer on the gate line; forming a conductive spacer around the outside of the dielectric spacer; and at a predetermined area,
- the device is electrically isolated, the isolated gate line portion forms the gate electrode of the corresponding unit device, and the isolated conductive sidewall portion forms the contact portion of the corresponding unit device.
- a semiconductor device structure comprising: a semiconductor substrate; a plurality of unit devices formed on the semiconductor substrate, each of the unit devices comprising: fins extending in a first direction; a gate electrode extending in a second direction crossing the first direction, the gate electrode intersecting the fin via the gate dielectric layer; a dielectric spacer formed on both sides of the gate electrode; and a conductive formed on an outer side of the dielectric spacer a sidewall, the conductive sidewall spacer being used for a contact portion of the unit device, wherein respective gate electrodes, dielectric spacers, and conductive sidewall spacers of the adjacent unit devices in the second direction are respectively extended by the second direction Forming a gate line, an identical dielectric spacer layer, and a same conductive sidewall layer, the gate line including a first electrical isolation portion in a predetermined region between the adjacent unit devices, the conductive sidewall layer being A predetermined electrical isolation portion is included in the predetermined region between the adjacent unit devices, and the dielectric
- the sidewall material of the dielectric and the conductive spacer does not extend between the opposite gate electrode end faces of the adjacent unit device, so that defects such as holes are not caused due to the presence of the sidewall material at the slit as in the prior art, and Because the minimum electrical isolation distance between devices can be reduced, the integration of the device can be increased, and the manufacturing cost of the integrated circuit can be reduced.
- the contact portion is formed in the form of a side wall, which avoids the difficulty in forming the contact hole in the conventional art.
- the contact portion formed according to the embodiment of the present invention is formed outside the dielectric spacer in a side wall manner so as to be self-aligned with the source/drain regions, and thus can serve as a source/drain region of the semiconductor device and the outside Electrically connected contacts.
- the conductive spacer (lower contact portion) can have the same height as the gate stack by the planarization process. Therefore, it is advantageous for the process of subsequent electrical connection and the like.
- Figure 1 shows a perspective view of an example FinFET
- Figure 2 shows a photograph of the topography of the fin and gate electrode in an actually fabricated FinFET
- Figure 3 shows the formation of fins of a FinFET in a conventional process, where (a) is a top view and (b) is a cross-sectional view taken along line A-A' in (a);
- FIGS. 5-7 show a gate stack pattern of a FinFET in a conventional process, wherein (a) is a top view, (b) is a cross-sectional view along line A-A' in (a);
- FIGS. 9-12 illustrate a fabrication flow of a semiconductor device structure according to the first embodiment of the present invention, wherein (a) is Top view, (b) is a cross-sectional view along line A-A' in (a);
- FIG. 13 to 16 show a fabrication flow of a semiconductor device structure in accordance with a second embodiment of the present invention, wherein (a) is a top view and (b) is a cross-sectional view taken along line A-A' in (a).
- the semiconductor substrate is an SOI substrate including two Si layers 200 and 202 and a SiO 2 layer 201 interposed therebetween.
- the Si layer 202 is etched by using a patterned hard mask layer 203 (e.g., Si 3 N 4 ) as a mask to form fins.
- a patterned hard mask layer 203 e.g., Si 3 N 4
- the semiconductor substrate includes Si in this example and the semiconductor material constituting the fin also includes Si, those skilled in the art will appreciate that the semiconductor substrate and/or fin may comprise any suitable semiconductor material such as Ge, GaN, InP, etc. .
- the SOI substrate is also taken as an example, but the invention is not limited thereto.
- the hard mask layer 203 can be removed, such that a subsequently fabricated gate electrode can be in contact with the three sidewalls of the fin 202 via the gate dielectric layer to form a Tri-Gate FET.
- the hard mask layer 203 can also be retained, such that the subsequently fabricated gate electrode is only in contact with the two sidewalls of the fin 202 via the gate dielectric layer (the top wall is not controlled by the gate electrode due to the presence of the hard mask layer 203 A channel is created) to form a 2-gate FET.
- a gate dielectric layer 203 e.g., a high-k gate dielectric layer
- a gate electrode layer 204 e.g., a metal gate electrode layer
- the gate dielectric layer 203 and the gate electrode layer 204 are patterned to form a final gate stack.
- a semiconductor substrate is shown in a top view, on which a pattern of fins 202 is formed as shown in FIG. 4 (note that FIG. 4 is shown in FIG. 5 ( a part of the structure shown in a), so the two look different, and a gate dielectric layer 203 and a gate electrode layer 204 are formed.
- the gate dielectric layer 203 and the gate electrode layer 204 are not shown in the top view (the same is true in the top views below).
- a photoresist linear pattern 205 corresponding to a gate line pattern to be formed is obtained by applying a photoresist and exposing it with a mask, followed by development.
- the segments in pattern 205 are printed parallel to one another in the same direction, with the same or similar spacing and critical dimensions.
- the slit 206 is formed on the linear pattern 205 by re-exposure and development using the cutting mask. Thereby, the gate patterns corresponding to the respective unit devices in the pattern 205 are caused to be disconnected from each other.
- the photoresist is etched by the photoresist pattern 205 formed with the slit 206, and finally formed into the pattern.
- a gate electrode 204 formed after etching is shown in FIG. It should be noted here that in the example shown in FIG. 7, the gate dielectric layer 203 is not etched. However, those skilled in the art will appreciate that the gate dielectric layer 203 may be further etched after etching the gate electrode layer 204.
- one exposure for forming the gate pattern is divided into two: one exposure linear pattern 205; another exposure slit 206.
- FIG. 8 there is shown a dielectric spacer 207 formed around the gate electrode 204 (in FIG. 8, the sidewall of the uppermost gate electrode and the lowermost gate electrode are not shown for the sake of simplicity). However, it should be noted that if a certain gate electrode 204 terminates at these positions, sidewalls 207, SP, which are formed around the gate electrode 204, are also formed at these locations. Since the slit 206 is present in the gate pattern, the sidewall material also enters the slit 206.
- the incisions in the gate lines can affect the topography of the dielectric spacers. For example, if the slit in the gate line is too small (the distance between the opposite end faces of the gate electrode is too small), the dielectric will form a void at the slit. Such holes may cause short circuits between devices, etc. in subsequent processes. In addition, the morphology of the dielectric sidewall material at the incision can have a significant impact on subsequent CMP process requirements.
- this conventional process requires very precise (gate electrode) end-to-end spacing. This requirement makes the Optical Proximity Correction (OPC) more difficult. Moreover, the design of the cut-off mask becomes challenging.
- OPC Optical Proximity Correction
- an alternative gate process has been employed in order to use a high-k gate dielectric/metal gate structure. The replacement gate process makes this line-and-cut method more complicated.
- the gate and the source/drain contact are formed by forming an interlayer dielectric layer, etching a contact hole in the interlayer dielectric layer, and filling the contact hole with a conductive material.
- etching a contact hole aligned with it on a very small gate and source/drain is a very difficult task.
- the height of the gate and the source/drain are different, so that the etching depth of the contact holes above them is also different, which also causes difficulty in forming the contact portion.
- the slit mask is not immediately formed using the dicing mask, but the gate electrode layer is directly etched using the linear pattern to Parallel gate lines are formed.
- the gate dielectric layer 1003 and the gate electrode layer 1004 are sequentially formed. Then, a photoresist line pattern corresponding to the gate line pattern to be formed is printed, and the line segments in the photoresist line pattern are printed in parallel with each other in the same direction (see the description above in connection with FIG. 5). These parallel segments can have different pitches and/or different widths.
- the dicing pattern is not immediately formed using the dicing mask, but the gate electrode layer is directly etched using the linear pattern to form the parallel gate lines 1004.
- the gate dielectric layer 1003 is also etched so that the gate dielectric layer 1003 is only under the gate line 1004, see Fig. 9(b).
- the gate dielectric layer 1003 may be, for example, a common dielectric material SiO 2 or a high-k gate dielectric material such as Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO. Any one or a combination thereof, or other materials.
- the gate electrode layer 1004 may include, for example, polysilicon or a metal material such as Ti, Co, Ni, Al, W or an alloy thereof or a metal nitride or the like.
- processing can be performed in accordance with a conventional process to form a semiconductor device structure such as a transistor structure.
- a semiconductor device structure such as a transistor structure.
- ion implantation doping to form source/drain, etc.
- sidewall formation e.g., silicidation, etc.
- silicidation e.g., silicidation, etc.
- these specific processes for forming a semiconductor device e.g., ion implantation, silicidation, etc.
- these specific processes for forming a semiconductor device e.g., ion implantation, silicidation, etc.
- the side wall formation according to the present invention will be mainly described.
- a dielectric spacer layer 1005 is formed around the gate line 1004.
- a dielectric spacer can be formed by reactive ion etching by depositing one or more layers of dielectric material, such as SiO 2 , Si 3 N 4 , SiON or other materials, over the entire semiconductor device structure, or a combination of these materials.
- the conductive spacer layer 1006 is formed of a conductive material around the outside of the dielectric spacer layer 1005 formed as described above.
- the conductive spacer layer 1006 is formed on the outer side of the dielectric spacer layer 1005 in the horizontal direction of the figure except that the gate line 1004 is at the end in the vertical direction in the drawing. .
- the dielectric sidewall layer and the conductive sidewall layer may also be formed on both sides of the protruding fin of the device, not shown.
- the dielectric spacer layer and the conductive sidewall layer on both sides of the protruding fin of the device can be selectively removed according to the needs of the device.
- the conductive spacer layer 1006 can be formed as follows. Depositing a layer of conductive material, such as metal, metal nitride, carbon, etc., on the semiconductor substrate; and then selectively etching the deposited conductive material layer to remove portions parallel to the surface of the substrate, Only the portion perpendicular to the surface of the substrate is retained, and thus the conductive spacer layer 1006 is obtained.
- conductive material such as metal, metal nitride, carbon, etc.
- the conductive spacer layer 1006 is self-aligned to the fin regions on both sides of the gate stack, so that it can be used as a contact portion for the source/drain regions to be electrically connected to the outside.
- an interlayer dielectric layer 1007 can be formed on the resultant structure (see Fig. 12).
- Such an interlayer dielectric layer may generally comprise a nitride such as Si 3 N 4 .
- the interlayer dielectric layer is made of a stress-bearing dielectric material.
- the interlayer dielectric layer can be made of a dielectric material with tensile stress; for a PFET, the interlayer dielectric layer can be made of a dielectric material with compressive stress.
- the gate line 1004, the dielectric spacer layer 1005, and the conductive spacer layer 1006 formed as described above are cut at a predetermined area in accordance with the design to achieve electrical isolation between the respective unit devices (
- the interlayer dielectric layer formed is not shown in Fig. 12 (a) for the sake of clarity.
- the cut is made above the passive field between the fins 1002, and the width of the slit (in the vertical direction of the figure) is typically l-10 nm.
- Such cutting can be achieved, for example, by a reactive mask etching or laser cutting etching using a cutting mask.
- a photoresist is first coated on a substrate, and the photoresist is patterned by cutting the mask so that a predetermined region corresponding to the slit to be formed is exposed. Then, the exposed gate lines 1004, the dielectric spacer layer 1005 formed therearound, and the conductive spacer layer 1006 are cut to form a slit 1008.
- the cut gate line 1004 forms an electrically isolated gate electrode; the cut dielectric sidewall layer forms an electrically isolated dielectric spacer; the cut conductive sidewall layer 1006 forms an electrically isolated conductive sidewall, and the conductive sidewall constitutes a corresponding The contact of the device.
- the slit 1008 can then be filled with an additional interlayer dielectric layer.
- the dielectric spacer layer 1005 is not electrically conductive, it does not hinder the inter-cell device. Electrically isolated, the dielectric spacer layer 1005 can not be severed during the cutting process described above. For example, in the case of cutting by reactive ion etching, selective etching may be performed so that the etching does not substantially affect the dielectric spacer layer 1005.
- the semiconductor material (for example, Si) in the gate line 1004 and the conductive material in the conductive sidewall layer 1006 can be made by, for example, injecting oxygen into the slit position (for example, Metal) oxidizes to form an insulating oxide.
- the slit position for example, Metal
- the gate lines 1004 at both ends of the slit position are electrically isolated from each other (equivalent to the effect of "cutting") to form an electrically isolated gate electrode
- the conductive spacer layers 1006 at both ends of the slit position are electrically isolated from each other. (Equivalent to the effect of "cut") to form electrically isolated conductive sidewalls, ie electrically isolated contacts.
- the injected element is not limited to oxygen.
- Those skilled in the art can also appropriately select the injected gas or chemical substance according to the materials of the gate line 1004 and the conductive sidewall layer 1006 to react them to form an insulating material. And thus achieve electrical isolation.
- the interlayer dielectric layer 1007 is formed first, and then the "off” or “isolation” of the gate lines and the conductive sidewall spacers (and the optional dielectric spacer layers) are performed ( In this case, the slits may be filled by other interlayer dielectric layers that are subsequently formed). However, it is also possible to first "cut” or “isolate” the gate lines and the conductive spacer layers (and optional dielectric spacer layers), and then form an interlayer dielectric layer 1007 (in this case, the slits are Interlayer dielectric layer 1007 is filled).
- Fig. 12 (b) is a cross-sectional view showing the structure of a semiconductor device fabricated by the above method.
- the illustrated structure has been subjected to a planarization process such as CMP (Chemical Mechanical Polishing) to expose the tops of the gate electrode 1004, the dielectric spacer 1005, and the conductive spacer 1006, thereby causing the gate stack (including The gate electrode 1004, the dielectric spacer 1005) and the top of the contact are substantially flush, which facilitates the subsequent electrical connection process.
- This planarization treatment may be performed, for example, immediately after the formation of the interlayer dielectric layer 1007, or may be performed after the "cut” or "isolation" described above.
- the semiconductor device is configured with a plurality of unit devices, each of which includes: a fin 1002 formed on a semiconductor substrate extending in a first direction (horizontal direction in the drawing); intersecting with the first direction a gate electrode 1004 extending in a second direction (vertical direction in the drawing), the gate electrode 1004 intersecting the fin 1002 via the gate dielectric layer 1003; a dielectric spacer 1005 formed on both sides of the gate electrode; and outside the dielectric spacer 1005 A conductive spacer 1006 is formed, and the conductive spacer 1006 is used for a contact portion of the unit device.
- the first direction is orthogonal to the second direction.
- the gate electrodes, the dielectric spacers, and the conductive spacers respectively opposed to each other by the adjacent unit devices are respectively formed by the same gate extending in the second direction Polar line, same The dielectric sidewall layer and the same conductive sidewall layer are formed.
- the gate line includes a first electrical isolation at a predetermined area, the conductive sidewall layer including a second electrical isolation at a predetermined area such that adjacent unit devices are electrically isolated from each other.
- the second electrical isolation in the conductive spacer layer may be the same as the first electrical isolation in the gate line.
- Such an electrically isolating portion may include a slit formed by etching, or an insulating material transformed from a gate line material, a conductive sidewall material (for example, an oxide formed by injecting oxygen at a slit position).
- the slit may be filled with a dielectric material, for example, in the case where the interlayer dielectric layer 1007 is first cut and then formed, the material of the interlayer dielectric layer 1007 may be filled in the slit, or the interlayer dielectric layer 1007 may be formed before cutting.
- the material in the slit may be filled with a subsequently formed interlayer dielectric layer.
- the sidewall layer (dielectric sidewall layer and conductive sidewall layer) extends outside the gate line such that at a predetermined region, there is no (dielectric and conductive) sidewall material between the opposite gate electrode ends. This is different from the conventional technique in which a side wall is formed around the gate electrode so that there is a side wall material between the end faces of the gate electrode.
- the method of the present invention can also be compatible with alternative gate processes.
- a replacement gate process is incorporated, i.e., a sacrificial gate line is first formed, and a gate line is replaced instead.
- the parallel gate line patterns are printed first. Etching is performed to form a sacrificial gate line 1004, which is typically formed of polysilicon.
- the dielectric spacer layer 1005 may be formed around the sacrificial gate line 1004 (since the opening is not formed in the sacrificial gate line 1004, so in addition to the end of the sacrificial gate line 1004 in the vertical direction in the figure
- the dielectric spacer layer 1005 is formed on the sacrificial gate lines 1004 on both sides in the horizontal direction in the drawing).
- a conductive spacer layer 1006 can be formed around the outside of the dielectric sidewall layer 1005.
- the conductive spacer layer 1006 can be used as a contact portion for electrically connecting the source/drain regions to the outside as described above.
- an interlayer dielectric layer 1007 may be formed on the resultant structure, and planarized to expose the gate line portion.
- Such an interlayer dielectric layer may generally comprise a nitride such as Si 3 N 4 .
- the interlayer dielectric layer is made of a stress-bearing dielectric material.
- interlayer dielectric The layer may be made of a dielectric material with tensile stress; for a PFET, the interlayer dielectric layer may be made of a dielectric material with compressive stress.
- the sacrificial gate line 1004 and the sacrificial gate dielectric layer 1003 are removed, for example, by etching or the like, thereby forming an opening 1004' between the dielectric spacer layers 1005.
- a replacement gate dielectric layer 1003' eg, a high-k gate dielectric layer
- an alternate gate line 1004" eg, a metal gate electrode
- a planarization process such as CMP may be performed such that the gate line 1004" has the same height as the conductive spacer 1006. This facilitates subsequent processing.
- electrical isolation between the unit devices is effected in a predetermined region by the cut-off mask (see Fig. 12).
- the electrical isolation can be achieved, for example, by cutting off the replacement gate line 1004" and the conductive spacer layer 1006 and the optional dielectric spacer layer 1005 in a predetermined region; or, by performing oxygen implantation in a predetermined region,
- the electrical isolation is achieved by oxidizing a material (eg, a metal gate electrode material) in the gate line 1004" and a conductive material (eg, a metal) in the conductive sidewall layer 1006 to form an insulating oxide.
- the replacement gate processing is performed first, and then the cutting processing is performed.
- the invention is not limited thereto. It is also possible to perform an alternative gate treatment after the cutting process. For example, after forming the conductive spacer layer 1006, an isolation process can be performed immediately to form an electrically isolated gate electrode and an electrically isolated contact portion, followed by a replacement gate process to form a gate.
- an isolation process can be performed immediately to form an electrically isolated gate electrode and an electrically isolated contact portion, followed by a replacement gate process to form a gate.
- the order of the respective steps in the various embodiments of the present invention is not limited to the above embodiments.
- electrical isolation e.g., dicing or oxidation
- electrical isolation step can be performed prior to the formation of the metal interconnects between the devices after the conductive spacers are formed.
- the dielectric spacer layer and the conductive spacer layer are both "I" type spacers, which are different from the "D" type spacer in the first embodiment.
- the advantage of the ⁇ -type side wall is that the height formed is consistent with the gate stack. After the formation of the I-type spacer, no planarization process may be required.
- a person of ordinary skill in the art is aware of various methods of forming an I-type sidewall, which is not DETAILED DESCRIPTION Similarly, a Type I spacer can be applied to the first embodiment. As described above, in the embodiment according to the present invention, after the parallel line pattern is printed on the substrate, it is not as in the prior art.
- the etch is first performed using the printed parallel line pattern to obtain the gate lines, and the semiconductor device structure continues to be formed.
- the mask is electrically isolated from the device, for example by cutting or oxidizing. Therefore, according to the present invention, the gate pattern is further cut or isolated at the end, so that the distance between the tips of the opposing gate electrodes can be made closer.
- the self-aligned source/drain contacts may be formed in the form of sidewalls around the dielectric spacer layers on either side of the gate lines before the gate lines are turned off.
- electrical isolation is performed after the formation of the dielectric spacer layer and the conductive spacer layer to isolate the devices from each other. Therefore, there is no sidewall material between the opposite gate electrode end faces of adjacent unit devices, so that defects such as holes do not occur as in the prior art.
- the conductive spacers (contact portions) between the unit devices are completely disconnected by the slits or the spacers, thereby achieving good electrical insulation between the devices.
- the contact portion is formed in a side wall manner according to an embodiment of the present invention, thereby avoiding the formation of the contact hole in the conventional art. Difficulties.
- contact portions in the form of side walls are self-aligned to the source/drain regions, greatly simplifying the process. According to conventional processes, such self-aligned contacts cannot be formed in the form of conductive sidewalls. This is because in the conventional process, the slit is formed first, and then the sidewall forming process is performed.
- the conductive material can enter the slits, thereby making it impossible for the respective conductive sidewalls of the gates opposite each other to be completely isolated, and thus the respective devices to be in electrical contact with each other.
- the present invention is compatible with alternative gate processes to achieve a variety of process options.
- the planarization process may be performed such that the conductive spacers (contact portions) have the same height as the gate stack. Therefore, it is advantageous for the subsequent process to proceed.
- the advantageous measures in these embodiments are not advantageously used in combination.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1202436.0A GB2503639B (en) | 2011-08-22 | 2011-08-29 | Semiconductor device structure and method for manufacturing the same |
US13/375,692 US8492206B2 (en) | 2011-08-22 | 2011-08-29 | Semiconductor device structure and method for manufacturing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110240932.X | 2011-08-22 | ||
CN201110240932.XA CN102956483B (zh) | 2011-08-22 | 2011-08-22 | 半导体器件结构及其制作方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2013026213A1 true WO2013026213A1 (zh) | 2013-02-28 |
Family
ID=47745862
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2011/079040 WO2013026213A1 (zh) | 2011-08-22 | 2011-08-29 | 半导体器件结构及其制作方法 |
Country Status (3)
Country | Link |
---|---|
CN (1) | CN102956483B (zh) |
GB (1) | GB2503639B (zh) |
WO (1) | WO2013026213A1 (zh) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104795330B (zh) * | 2014-01-20 | 2018-09-04 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
CN104795329B (zh) * | 2014-01-20 | 2018-07-20 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
CN104979199B (zh) * | 2014-04-03 | 2018-06-01 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
CN104979201B (zh) * | 2014-04-03 | 2018-03-06 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
CN105633158B (zh) * | 2015-03-31 | 2019-07-30 | 中国科学院微电子研究所 | 半导体器件制造方法 |
KR102404973B1 (ko) * | 2015-12-07 | 2022-06-02 | 삼성전자주식회사 | 반도체 장치 |
WO2018106233A1 (en) * | 2016-12-07 | 2018-06-14 | Intel Corporation | Integrated circuit device with crenellated metal trace layout |
US10867998B1 (en) | 2017-11-29 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure cutting process and structures formed thereby |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101192605A (zh) * | 2006-11-30 | 2008-06-04 | 国际商业机器公司 | 半导体器件及其制造方法 |
CN100413039C (zh) * | 2003-04-03 | 2008-08-20 | 先进微装置公司 | 形成FinFET装置中的栅极以及薄化该FinFET装置的沟道区中的鳍的方法 |
CN101930980A (zh) * | 2008-12-30 | 2010-12-29 | 海力士半导体有限公司 | 具有鞍鳍形沟道的半导体器件及其制造方法 |
CN102005477A (zh) * | 2009-09-01 | 2011-04-06 | 台湾积体电路制造股份有限公司 | 集成电路、鳍式场效应晶体管及其制造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7323389B2 (en) * | 2005-07-27 | 2008-01-29 | Freescale Semiconductor, Inc. | Method of forming a FINFET structure |
JP2009105195A (ja) * | 2007-10-23 | 2009-05-14 | Elpida Memory Inc | 半導体装置の構造および製造方法 |
-
2011
- 2011-08-22 CN CN201110240932.XA patent/CN102956483B/zh active Active
- 2011-08-29 WO PCT/CN2011/079040 patent/WO2013026213A1/zh active Application Filing
- 2011-08-29 GB GB1202436.0A patent/GB2503639B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100413039C (zh) * | 2003-04-03 | 2008-08-20 | 先进微装置公司 | 形成FinFET装置中的栅极以及薄化该FinFET装置的沟道区中的鳍的方法 |
CN101192605A (zh) * | 2006-11-30 | 2008-06-04 | 国际商业机器公司 | 半导体器件及其制造方法 |
CN101930980A (zh) * | 2008-12-30 | 2010-12-29 | 海力士半导体有限公司 | 具有鞍鳍形沟道的半导体器件及其制造方法 |
CN102005477A (zh) * | 2009-09-01 | 2011-04-06 | 台湾积体电路制造股份有限公司 | 集成电路、鳍式场效应晶体管及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN102956483B (zh) | 2015-06-03 |
GB2503639B (en) | 2016-01-06 |
GB201202436D0 (en) | 2012-03-28 |
CN102956483A (zh) | 2013-03-06 |
GB2503639A (en) | 2014-01-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2013026236A1 (zh) | 半导体器件结构及其制作方法、及半导体鳍制作方法 | |
US10032675B2 (en) | Method for fabricating semiconductor device | |
KR101524945B1 (ko) | 집적회로 구조물 및 그 형성방법 | |
KR101522458B1 (ko) | 핀 요소의 스템 영역을 포함하는 finfet 디바이스를 제조하는 방법 | |
WO2013026213A1 (zh) | 半导体器件结构及其制作方法 | |
US8492206B2 (en) | Semiconductor device structure and method for manufacturing the same | |
KR20190024564A (ko) | 유전체 핀과 스페이서에 의해 제한되는 에피택셜 피처 | |
KR102055810B1 (ko) | 반도체 디바이스를 제조하는 방법 및 반도체 디바이스 | |
US20150054078A1 (en) | Methods of forming gate structures for finfet devices and the resulting smeiconductor products | |
JP2008172082A (ja) | 半導体装置及び半導体装置の製造方法 | |
US9496178B2 (en) | Semiconductor device having fins of different heights and method for manufacturing the same | |
CN106033769B (zh) | 纳米线结构及其制作方法 | |
TW202127664A (zh) | 積體電路裝置 | |
WO2015000204A1 (zh) | FinFET器件及其制作方法 | |
WO2012012922A1 (zh) | 半导体器件结构及其制作方法 | |
US10636793B2 (en) | FINFETs having electrically insulating diffusion break regions therein and methods of forming same | |
WO2014032338A1 (zh) | 半导体结构及其制造方法 | |
WO2014071664A1 (zh) | FinFET及其制造方法 | |
US8729611B2 (en) | Semiconductor device having a plurality of fins with different heights and method for manufacturing the same | |
WO2014106376A1 (zh) | 半导体结构及其制造方法 | |
WO2013029311A1 (zh) | 半导体器件及其制造方法 | |
WO2013033956A1 (zh) | 半导体器件及其制造方法 | |
KR102526325B1 (ko) | 최적화된 게이트 스페이서 및 게이트 단부 유전체를 갖는 게이트 올 어라운드 디바이스 | |
CN102881634B (zh) | 半导体器件结构及其制作方法 | |
US20130292779A1 (en) | Semiconductor device and semiconductor device production process |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 13375692 Country of ref document: US |
|
ENP | Entry into the national phase |
Ref document number: 1202436 Country of ref document: GB Kind code of ref document: A Free format text: PCT FILING DATE = 20110829 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1202436.0 Country of ref document: GB |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 11871189 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 11871189 Country of ref document: EP Kind code of ref document: A1 |