WO2014106376A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

Info

Publication number
WO2014106376A1
WO2014106376A1 PCT/CN2013/080151 CN2013080151W WO2014106376A1 WO 2014106376 A1 WO2014106376 A1 WO 2014106376A1 CN 2013080151 W CN2013080151 W CN 2013080151W WO 2014106376 A1 WO2014106376 A1 WO 2014106376A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
opening
gate line
semiconductor structure
layer
Prior art date
Application number
PCT/CN2013/080151
Other languages
English (en)
French (fr)
Inventor
钟汇才
梁擎擎
杨达
赵超
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to US14/652,956 priority Critical patent/US9397007B2/en
Publication of WO2014106376A1 publication Critical patent/WO2014106376A1/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to the field of semiconductor fabrication, and more particularly to a semiconductor structure and a method of fabricating the same. Background technique
  • FIG. 1 illustrates a portion of a semiconductor structure in which a conventional line-and-cut technique forms a gate.
  • the photoresist layer 11 is first overlaid on the substrate 10 on which the gate material layer is formed, and the photoresist layer 11 is exposed and developed using a mask to perform the photoresist layer 11.
  • the pattern is drawn to draw a line pattern corresponding to the gate line pattern to be formed.
  • the gate layer is etched to form a gate line 12 (the structure formed in FIG. 1 is a structure formed after the gate layer has been etched).
  • FIG. 2 is a cross-sectional view of the semiconductor structure shown in FIG. 1 along the AA direction.
  • the gate lines 12 are arranged on the substrate 10, and the gate lines are planarly covered with the photoresist layer 11.
  • re-exposure is performed using a dicing mask to form an opening 13 on the photoresist layer 11, and the opening 13 exposes the gate line 12.
  • the gate line 12 can be cut by etching the gate line 12 through the opening 13.
  • the photoresist layer 11 has been removed, after the gate line 12 is etched through the opening 13, the photoresist layer 11 is removed, a portion of the gate line 12 is removed, and a slit 16 is formed, and the gate line 12 is formed.
  • the gate 16 is interrupted by the kerf 16 as an electrically isolated gate, such as the electrically isolated gate 14 and gate 15 of FIG.
  • the above prior art processes have the following problems: First, the above processes are highly demanding for lithography, requiring very precise tip-to-tip spacing. In particular, the way in which such gate line patterns are developed toward smaller devices will be very difficult. In order to increase the degree of integration, the preparation of a dicing mask for forming a sufficiently thin slit will be very difficult. In addition, the use of the above techniques in alternative gate and high-k dielectric processes can be more complicated. A side wall double reconstruction map may be required below the 22 nm technology node.
  • the width of the opening 13 in the direction of the gate width can be as small as 30 nm to 50 nm, and thus the width of the slit 16 formed by etching through the opening 13 in the direction of the gate width is also In the range of 30 nm to 50 nm, that is, the distance between the ends of adjacent electrically isolated gates on the same straight line is at least 30 nm.
  • semiconductor manufacturing technology for example, in the 45nm process, in order to achieve higher integration, it is desirable to reduce the distance between the ends of adjacent electrically isolated gates on the same line, but due to technical limitations.
  • the distance between the ends of the gates electrically adjacent to each other on the same straight line cannot be reduced to 30 nm or less, which is a problem to be solved for improving the integration degree.
  • a sidewall surrounding the gate is generally formed on both sides of the electrically isolated gate, and a sidewall 16 is formed between the gates, and a sidewall is formed when the sidewall is formed.
  • the material is deposited on both sides of the grid on the one hand and into the slit 16 on the other hand. Since the slit 16 is very narrow, the sidewall material is likely to form defects such as voids in the slit, which is disadvantageous for subsequent processing of the semiconductor device, particularly when the metal plug is subsequently formed, and is easily short-circuited therein, and if the gate is a dummy gate, then This void also causes a short circuit between the gates when the replacement gate is subsequently formed. This reduces the performance and stability due to the semiconductor device. Summary of the invention
  • An object of the present invention is to provide a semiconductor structure and a method of fabricating the same that avoids the occurrence of defects in forming a gate of a semiconductor structure, thereby facilitating further subsequent processing of the semiconductor device.
  • the present invention provides a method of fabricating a semiconductor structure, the method comprising: a) forming a gate line extending in a direction on a substrate;
  • the present invention also provides a semiconductor structure including:
  • a gate line extending in a direction is formed on the substrate, and sidewalls are formed on both sides of the gate line;
  • the method of fabricating a semiconductor structure provided by the present invention reduces the distance between the openings and the walls in the gate width direction by forming an additional layer on the inner wall of the opening of the photoresist layer. It is also possible to reduce the distance between the ends of the adjacent electrically isolated gates on the same line without the need to make a very thin cut mask. Therefore, the area is saved and the integration of the semiconductor device is improved.
  • the semiconductor structure and the manufacturing method thereof provided by the present invention do not form a slit on the gate line as compared with the existing line-and-cut dual patterning technique, but use ion implantation.
  • An insulating layer is formed in the direction of the gate length to form an electrically isolated gate, substantially without physically cutting the gate line, while leaving a complete gate line. Such a process does not form a defect in the prior art, facilitates subsequent processing, and ensures the quality of the semiconductor device.
  • FIG. 4 are schematic top plan views of the semiconductor structure in various stages in the process of forming a gate of a semiconductor structure in the prior art
  • FIG. 5 is a flow diagram of one embodiment of a method provided in accordance with the present invention.
  • FIG. 6 to 22 are flowcharts according to FIG. 5 according to an embodiment of the present invention.
  • FIG. 23 to FIG. 25 are schematic diagrams showing respective structures of various stages of fabrication of the semiconductor structure during formation of sidewall spacers and source/drain regions in accordance with another embodiment of the present invention.
  • the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. Embodiments such that the first and second features may not be in direct contact.
  • a schematic diagram of a layer structure in accordance with an embodiment of the present invention is shown in the accompanying drawings. These figures are not drawn to scale, and some details are exaggerated for clarity and some details may be omitted. The various regions, the shapes of the layers, and the relative sizes and positional relationships between the figures are merely exemplary and are not drawn to actual scale, and may in practice be due to manufacturing tolerances or technical limitations. Deviations, and those skilled in the art can additionally design regions/layers having different shapes, sizes, and relative positions according to actual needs. The embodiment will be described.
  • FIG. 5 is a flow chart of a specific embodiment of a method according to the present invention, the method comprising:
  • Step S101 forming a gate line extending in a direction on the substrate
  • Step S102 forming a photoresist layer covering the semiconductor structure, and patterning the photoresist layer An opening across the gate line;
  • Step S103 reducing the opening by forming a self-assembling copolymer in the opening
  • Step S104 cutting the gate line through the opening to insulate the gate line at the opening.
  • step S101 is performed to form a gate line 210 extending in one direction on the substrate 100.
  • 6 to 9 are schematic diagrams showing the various structures of the semiconductor structure in the process of forming the gate line 210 in accordance with the method of fabricating the semiconductor structure of the present invention.
  • the substrate 100 may include a silicon substrate (e.g., a silicon wafer).
  • the substrate 100 can include various doping configurations in accordance with design requirements well known in the art (e.g., a P-type substrate or an N-type substrate).
  • the substrate 100 in other embodiments may also include other basic semiconductors such as germanium.
  • the substrate 100 may comprise a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide or indium phosphide.
  • the thickness of the substrate 100 may be, but not limited to, about several hundred micrometers, for example, may range from 400 ⁇ m to 800 ⁇ m.
  • the substrate 100 may be made of bulk silicon or silicon-on-insulator (SOI). .
  • SOI silicon-on-insulator
  • a shallow trench isolation structure may be formed in advance on the substrate, and the shallow trench isolation structure divides the surface of the substrate into independent active regions.
  • the material of the photoresist layer 201 may be an olefinic monomer material, a material containing an azide quinone compound or a polyethylene laurate material, and of course, a suitable material may be selected according to specific manufacturing needs.
  • the gate line 210 extending in one direction is obtained by patterning and etching the photoresist on the gate stack layer 200.
  • the photoresist layer 300 is first exposed and developed using a mask to expose the gate stack layer 200 to draw a line pattern corresponding to the pattern of the gate lines 210 to be formed, as shown in FIG.
  • the gate stack layer 200 is then further etched to form the gate lines 210, and the photoresist layer 201 is removed, as shown in FIG.
  • the gate stack includes a structure in which a gate dielectric layer and a gate material layer on the gate dielectric layer are stacked, the gate dielectric layer being in the gate stack
  • the material of the gate dielectric layer may be a thermal oxide layer, including silicon oxide or silicon oxynitride, or a high-k dielectric such as HfD 2 , HfSiO, HfSiON, HfTaO, HffiO, HfZrO, One of A1 2 0 3 , La 2 0 3 , Zr0 2 , or LaAlO, or a combination thereof, having a thickness of between 1 nm and 4 nm; and the gate material layer may be Poly-Si, Ti, Co, Ni, Al, W , alloys, metal silicides or combinations thereof.
  • the gate material layer is a multi-layer structure, for example, a gate metal layer and a gate electrode layer are stacked, wherein the gate metal layer may be made of TaC, TiN, TaTbN, TaErN, or the like.
  • the gate metal layer may be made of TaC, TiN, TaTbN, TaErN, or the like.
  • One or a combination of TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa, and a thickness thereof is between 5 nm and 20 nm
  • the material of the gate electrode layer 203 may be Poly-Si, and the thickness thereof is between 20 nm and 80 nm.
  • the gate stack may further include at least one dielectric layer covering the gate material layer to protect other structures of the underlying gate stack. Referring to FIG.
  • FIG. 9 a schematic diagram of a semiconductor structure shown in FIG. 8 is a cross-sectional structural view of a plan view of the semiconductor structure shown in FIG. 9 taken along line BB. It can be seen in Fig. 9 that the gate lines 210 extend in the up and down direction and are arranged in parallel at equal intervals. In other embodiments, the size, direction of extension, and spacing of the gate lines can be determined by the design needs of the semiconductor device.
  • the underlying active regions 110 and shallow trench isolation structures 120 are exposed.
  • source/drain regions may be formed in the active region 110 at this time.
  • Forming the source and drain regions may include first forming source/drain extension regions on both sides of the gate lines, and then forming sidewall spacers on the sidewalls of the gate lines, and finally forming source and drain regions on both sides of the sidewall spacers. Methods of forming source/drain extensions, sidewalls, and source/drain regions are well known in the art and will not be described herein.
  • the source and drain regions and the side walls are not formed here at this time, which will be described below.
  • step S102 is performed to form a photoresist layer 300 covering the semiconductor structure, and the photoresist layer 300 is patterned to form an opening 310 across the gate line.
  • the photoresist layer 300 material may be an olefinic monomer material, a material containing an azide quinone compound, or a polyethylene laurate material.
  • a photoresist layer 300 is formed over the entire semiconductor structure, that is, the gate line 210 and the substrate 100 on both sides thereof.
  • the above meaning of "covering” is:
  • the photoresist layer 300 directly covers the gate line 210 and the substrate 100 on both sides thereof; in other embodiments, according to manufacturing requirements, Other structures covering the gate line 210 and the substrate 100 on both sides thereof have been formed, such as an epitaxial strained layer, so that the photoresist layer 300 directly covers the epitaxial strained layer. Therefore, there may be other structures between the photoresist layer 300 and the gate lines 210 and the substrate 100, and it is only necessary to satisfy the photoresist layer 300 on the gate lines 210 and the substrate 100 for patterning.
  • an opening 310 across the gate line is formed on the photoresist layer 300.
  • the openings 310 expose the gate lines 210.
  • the opening 310 shown in FIG. 12 exposes a plurality of gate lines 210, so that the positions at which the plurality of gate lines 210 are cut off in the subsequent processing are on the same straight line.
  • the opening 310 may be Only exposed One gate line 210, the position of the opening 310 shown in Figure 12 is merely exemplary.
  • the opening 310 is generally formed over the shallow trench isolation structure 120 if the design requirements are met, such an arrangement helps to save area. , to improve integration.
  • the distance between the opposite walls of the opening 310 is less than 50 nm, which also contributes to saving area and improving integration.
  • step S103 is performed to narrow the opening by forming a self-assembling copolymer in the opening.
  • FIG. 13 is a partial enlarged view of the opening 310 in the region 400 shown in FIG. 12, where W1 represents The distance between the opposite walls of the opening 310 in the direction of the gate width.
  • W1 represents The distance between the opposite walls of the opening 310 in the direction of the gate width.
  • the size of the opening 310 is limited by the level of technology, for example,
  • FIG. 14 is a schematic structural view after the formation of the additional layer 320 on the inner wall of the opening 310 shown in FIG.
  • the material of the photolithography layer 300 is selected from a photoresist, so that the material of the inner wall of the opening 310 is also a photoresist, and a self-assembled copolymer material can be grown on the photoresist on the inner wall of the opening 310.
  • the self-assembled copolymer that is grown forms an additive layer 320, that is, the additive layer 320 is a self-assembled copolymer layer 320.
  • the description of the growth of the self-assembled copolymer material on the photoresist layer can be referred to as "Self-Assembling Materials for Lithographic".
  • the distance between the opening 310 and the two walls in the gate width direction becomes W2, W2 ⁇ Wlfact
  • W2 is less than 30 nm, such as less than 20 nm, or even less than 10 nm. Therefore, after the inner wall of the opening 310 covers the self-assembled copolymer layer 320, the opening 310 in the gate width direction The distance between the opposite walls is further reduced.
  • the inner wall of the opening 310 covers the self-assembled copolymer layer 320, so that the area of the exposed gate line 210 is smaller than before the self-assembled copolymer layer 320 is not formed.
  • the distance between the openings and the opposite walls in the gate width direction is reduced, that is, the ends of adjacent electrically isolated gates on the same line are reduced. The distance between the parts thus saves area and improves the integration of semiconductor devices.
  • step S104 is performed to cut the gate line through the opening to insulate the gate line at the opening.
  • ions are implanted into the gate line 210 through the opening 310 in the present embodiment to insulate the gate line 210 at the opening 310.
  • the gate lines can also be severed at opening 310 by etching, laser ablation, or the like.
  • ion implantation is performed through the opening 310 to cause the exposed gate line 210 to react to form the insulating layer 230.
  • the insulating layer 230 cuts off the gate line 210 along the gate length direction, so that the gate line 210 forms an electrically isolated gate. pole.
  • ion implantation is performed through opening 310, which is typically oxygen ion implantation.
  • the exposed gate line 210 is oxidized using oxygen ion implantation, and the oxide generated by oxidation of the gate line 210 is insulated.
  • the insulating layer 230 has been formed. Taking oxygen ion implantation as an example, the insulating layer 230 is composed of an oxide formed by the reaction of the exposed gate line 210 with the oxygen ions, such as silicon oxide. , metal oxide, etc. (depending on the material of the gate stack).
  • the photoresist layer 300 may be removed to facilitate subsequent processing.
  • the insulating layer 230 cuts off the gate lines 210 along the gate length direction, so that the gate lines 210 form electrically isolated gates, such as 18 electrically isolated gate 211 and gate 212.
  • the opening 310 exposes not only a plurality of gate lines 210 but also a portion of the substrate 100. However, since the position of the opening is generally above the shallow trench isolation structure, the implanted oxygen ions do not oxidize the active region.
  • FIG. 19 is a cross-sectional structural view of the semiconductor structure shown in FIG. 18 along the CC direction.
  • the electric field can be used to control the energy of the oxygen ions.
  • the exposed gate lines 210 are all oxidized from the outer surface to the center to form the insulating layer 230.
  • the insulating layer 230 is on the cross section of the gate line 210, and completely isolates the original one gate line 210 into two segments, that is, the originally conductive gate line 210 is exposed due to oxidation of oxygen ions.
  • the part is broken, but the shape of the complete gate line 210 is preserved, and the physical shape of the gate line 210 does not need to be broken, nor does it form a physics. Incision in the sense, this is different from the prior art.
  • the semiconductor structure may be subsequently processed.
  • side walls 220 surrounding the gate lines 210 are formed on both sides of the gate lines 210, and the sidewall spacers 220 may be nitrided. Silicon, silicon oxide, silicon oxynitride, silicon carbide, and/or other suitable materials are formed.
  • the side wall 220 may have a multi-layered structure.
  • the spacer 220 may be formed by a deposition-etching process having a thickness ranging from about 10 nm to about 100 nm.
  • 20 is a cross-sectional structural view of the semiconductor structure shown in FIG. 21 in the DD direction. Referring to FIG.
  • the sidewall spacers 220 are formed on both sides of the gate line 210, that is, on both sides of the gate electrode 211 or the gate electrode 212. Protection gate. Source and drain extensions can be formed on both sides of the gate before forming the sidewalls. Source and drain regions may be formed outside the sidewalls after the sidewalls are formed, and are not described herein.
  • At least one strain layer 400 covering the gate lines 210, the sidewall spacers 220, and the substrate 100 may be formed, which is used to increase stress to enhance The performance of the semiconductor device is shown in FIG.
  • the sidewall spacer 220 and the at least one strain layer 400 may be formed first, and then the insulating layer 230 is formed. That is, the step of forming the insulating layer 230 can be performed last.
  • a pattern composed of the gate lines 210 as shown in FIG. 10 is formed first, and then the semiconductor structure shown in FIG. 23 is formed, that is, a source-drain extension region and a sidewall spacer are formed on both sides of the gate line 210. 220 and source and drain areas.
  • Figure 24 is a cross-sectional view of the semiconductor structure shown in Figure 23 taken along the line E-E.
  • At least one strain layer 400 covering the gate line 210, the sidewall spacers 220, and the substrate 100 may be formed as shown in FIG.
  • a process step of forming the insulating layer 230 is then performed.
  • the method for forming the sidewall spacers 220 and the strain layer 400 can be referred to the description of the relevant portions in the foregoing specific embodiments.
  • the method for forming the insulating layer 230 can also refer to the foregoing specific implementation manner, and it should be noted that
  • the strained layer 400 covers the gate line 210, and thus in some embodiments, the opening 310 formed on the photoresist layer 300 exposes the strained layer 400 of the gate line 210. Accordingly, it is necessary to adjust the energy and dose of oxygen ion implantation to pass through the strained layer 400 and completely oxidize the underlying gate line 210.
  • the step of forming the insulating layer 230 may be performed after the sidewall spacer 220 is formed, and may be performed after both the sidewall spacer 220 and the strain layer 400 are formed (generally, the strain layer 400 is formed on the sidewall spacer 220). It can also be formed before the formation of the side wall 220 and the strained layer 400, so that the degree of freedom in the manufacturing steps is high and can be arranged into various manufacturing processes. It should be noted, however, that the step of forming the insulating layer 230 (ie, forming the electrically isolated gate) should be in contact with the source/drain regions. Before touching the plug.
  • the method may include the steps of: forming at least one dielectric layer covering the gate lines, the sidewall spacers, and the source/drain regions (if the semiconductor structure has formed the strain layer 400, the at least one The dielectric layer covers the strained layer 400), and the contact plug embedded in the at least one dielectric layer is electrically connected to the source/drain region 100, and/or the gate.
  • the at least one dielectric layer may be formed on the substrate 100 by chemical vapor deposition (CVD), high density plasma CVD or other suitable methods, and the material thereof includes SiO 2 , carbon doped SiO 2 , BPSG.
  • the material of the contact plug may be any one of W, Al, TiAl alloy or a combination thereof.
  • the semiconductor structure and the manufacturing method thereof provided by the present invention do not form a slit on the gate line as compared with the existing line-and-cut dual patterning technique, but use ion implantation in the direction of the gate length.
  • An insulating layer is formed thereon to form an electrically isolated gate without damaging the physical shape of the gate line 210, nor forming a physical cut, but retaining the complete gate line 210.
  • the process of the present invention does not cause defects in the prior art, facilitates subsequent processing, and ensures the quality of the semiconductor device.
  • the formation of the insulating layer 230 is not limited by the formation of the sidewall spacer 220 and the strain layer 400, so that the degree of freedom in the manufacturing steps is high, and it can be arranged into a plurality of manufacturing processes, which can satisfy more application scenarios.
  • FIG. 21 is a schematic top plan view of a specific embodiment of a semiconductor structure provided by the present invention.
  • the semiconductor structure includes:
  • a gate line 210 extending in one direction is formed on the substrate, and sidewalls 220 are formed on both sides of the gate line;
  • the insulating region 230 isolating the gate line 210 from the adjacent gate line 210 in the direction, wherein the width of the insulating region 230 in the direction is less than 30 nm, preferably less than 20 nm, more preferably less than 10nm.
  • the substrate 100 comprises a silicon substrate (eg, a wafer).
  • the substrate 100 can include various doping configurations in accordance with design requirements known in the art, such as a P-type substrate or an N-type substrate. Other real
  • the substrate 100 in the embodiment may also include other basic semiconductors such as germanium.
  • the substrate 100 may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide or indium phosphide.
  • the thickness of the substrate 100 can be, but is not limited to, about a few hundred microns, for example, it can range from 400 ⁇ m to 800 ⁇ m.
  • a shallow trench isolation structure 120 may be formed on the substrate 100, and the shallow trench isolation structure 120 divides the surface of the substrate 100 into separate active regions 110.
  • the gate line 210 is a gate stack including a structure in which a gate dielectric layer and a gate material layer on the gate dielectric layer are stacked, the gate dielectric layer being in the gate stack
  • the material of the gate dielectric layer may be a thermal oxide layer, including silicon oxide, silicon oxynitride, or a high germanium medium such as Hf0 2 , HfSiO, HfSiON, HfTaO, HffiO, HfZrO, One of A1 2 0 3 , La 2 0 3 , Zr0 2 , or LaAlO, or a combination thereof, having a thickness of between 1 nm and 4 nm; and the gate material layer may be Poly-Si, Ti, Co, Ni, Al, W , alloys, metal silicides or combinations thereof.
  • the gate material layer is a multi-layer structure, for example, a gate metal layer and a gate electrode layer are stacked, wherein the gate metal layer may be made of TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN.
  • the gate metal layer may be made of TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN.
  • MoSiN, RuTa x , NiTa or the like the thickness of which is between 5 nm and 20 nm
  • the material of the gate electrode layer 203 may be Poly-Si, and the thickness thereof is between 20 nm and 80 nm.
  • the gate stack may further include at least one dielectric layer covering the gate material layer to protect other structures of the underlying gate stack. The size of the gate lines and the spacing between them are determined by the design requirements of the semiconductor device. Generally, the gate lines are arranged in parallel.
  • sidewall spacers 220 are formed on both sides of the gate line and surround the gate lines.
  • the spacer 220 may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and/or other suitable materials.
  • the side wall 220 may have a multi-layered structure.
  • the spacer 220 may be formed by a deposition-etch process having a thickness ranging from about 10 nm to 100 nm.
  • Source/drain regions may be formed in the active region 120 of the substrate 100. Typically, source/drain regions are formed after the gate lines 210 are formed.
  • the insulating layer 230 cuts off the gate lines 210 along the gate length direction, so that the gate lines 210 form electrically isolated gates such as the gate electrodes 211 and the gate electrodes 212 and the like.
  • the gate 211 and the gate 212 are on the same gate line 210, and both are disconnected by the insulating layer 230 to form electrical isolation.
  • the material of the insulating layer 230 is an oxide of a material (ie, a material of a gate line) of the gate stack formed, such as an insulating material such as silicon oxide or metal oxide, which is different from the material of the sidewall spacer 220. This differs from the prior art in that the side wall material is used to isolate the ends of the phase gates.
  • the insulating layer 230 is formed on the shallow trench isolation structure 120 Above, this helps save area and increase integration.
  • the thickness of the insulating layer 230 is less than 50 nm, for example, 10 nm in the gate width direction.
  • the insulating layer 230 is formed by an ion implantation method, for example, oxygen ions are implanted.
  • FIG. 20 is a cross-sectional structural view of the semiconductor structure shown in FIG. 21 along the DD direction. As shown, the gate line 210 is cut by the insulating layer 230. Form electrical isolation.
  • the semiconductor structure further includes at least one strain layer 400 covering the gate line 210, the sidewall spacers 220, and the source/drain regions for providing stress to enhance the semiconductor.
  • the performance of the device is not limited to, the semiconductor substrate, the semiconductor substrate, the semiconductor substrate, or the semiconductor substrate.
  • the semiconductor structure further includes at least one dielectric layer covering the gate lines, the sidewall spacers, and the source/drain regions (if the semiconductor structure has formed the strain layer 400, the at least one dielectric layer The layer covers the strained layer 400), and the contact plug embedded in the at least one dielectric layer is electrically connected to the source/drain region 100, and/or the gate.
  • the material of the at least one dielectric layer comprises SiO 2 , carbon doped SiO 2 , BPSG (borophosphosilicate glass), PSG (phosphorus silicate glass), USG (undoped silicon glass), silicon oxynitride, low k material Or a combination thereof.
  • the material of the contact plug may be any one of W, Al, TiAl alloy or a combination thereof.
  • semiconductor structure provided by the above specific embodiment may be included in the same semiconductor device, and other semiconductor structures may also be included.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

提供一种半导体结构的制造方法,该方法包括:a)在衬底(100)上形成在一方向上延伸的栅极线(210);b)形成覆盖半导体结构的光刻胶层(300),对该光刻胶层(201)构图形成跨所述栅极线(210)的开口(310);c)通过在开口(310)内形成自组装共聚物,将所述开口(310)缩小;d)通过所述开口(310)切断所述栅极线(210)中,使所述栅极线(210)在开口(310)处绝缘。通过在光刻胶层(300)的开口(310)的内壁上形成增加层(320),减小了在栅宽方向上所述开口相对两壁之间的距离,即减小了同一直线上相邻电隔离的栅极的端部之间的距离,因此节约了面积,提高了半导体器件的集成度。还提供了一种根据上述方法形成的半导体结构。

Description

半导体结构及其制造方法
[0001】本申请要求了 2013年 1月 6日提交的、 申请号为 201210543567.4、 发明 名称为"半导体结构及其制造方法"的中国专利申请的优先权, 其全部内容通 过引用结合在本申请中。 技术领域
[0002]本发明涉及半导体的制造领域,尤其涉及一种半导体结构及其制造方 法。 背景技术
[0003]随着半导体结构制造技术的发展, 具有更高性能和更强功能的集成电 路要求更大的元件密度, 而且各个部件、 元件之间或各个元件自身的尺寸、 大小和空间也需要进一步缩小, 在半导体结构的制造过程中, 光刻技术面临 了更高的要求和挑战。 特别是在静态随机访问存储器芯片的制造中, 为了形 成半导体结构中的栅极, 通常采用线条成形和切断( line-and-cut )双重图形 化技术。 下面结合图 1至图 4说明现有技术中这种技术的应用。
[0004] 图 1示出了现有的 line-and-cut技术形成栅极的半导体结构的一部分。 如图 1所示, 首先在其上形成了栅极材料层的衬底 10上覆盖光刻胶层 11 , 并 使用掩模对光刻胶层 11进行曝光并显影以对光刻胶层 11进行构图,绘制出与 将要形成的栅极线图案对应的线形图案。接下来对栅极层进行刻蚀形成栅极 线 12 (图 1中形成的结构是已经对栅极层进行刻蚀后形成的结构 )。参考图 2, 图 2是图 1示出的半导体结构沿 A-A方向的剖视图, 栅极线 12排列于衬底 10之 上, 栅极线上平面覆盖光刻胶层 11。 接下来, 参考图 3 , 利用切断掩模进行 再次曝光, 在光刻胶层 11上形成开口 13 , 开口 13暴露了栅极线 12。 通过开口 13刻蚀栅极线 12 , 可以将栅极线 12截断。 参考图 4, 已移除光刻胶层 11 , 通 过开口 13刻蚀栅极线 12后, 除去光刻胶层 11 , 栅极线 12的一部分被移除, 形 成切口 16, 而栅极线 12被切口 16截断为电隔离的栅极, 例如图 4中电隔离的 栅极 14和栅极 15。 [0005]上述的现有技术工艺存在以下问题: 首先, 上述工艺对光刻技术的要 求很高, 需要非常精确的尖端到尖端间距。 特别是随着向更小的器件发展这 种栅极线条构图的方式将非常困难。 为了提高集成度, 用于形成足够细的切 口的切断掩模的制备将会非常困难。 另外, 上述技术在替代栅和高 k介质工 艺中的使用会更为复杂。 对于 22nm技术节点以下可能需要侧墙双重构图。
[0006】例如, 现有技术中由于技术条件限制, 开口 13沿栅宽的方向上的宽度 最小能达到 30nm 〜 50nm, 因此通过开口 13刻蚀形成的切口 16沿栅宽的方向 上的宽度也在 30nm 〜 50nm的范围内, 即同一直线上相邻电隔离的栅极的端 部之间的距离最小为 30nm。 随着半导体制造技术的进一步发展, 例如 45nm 工艺中, 想要达到更高的集成度, 就希望减小同一直线上相邻电隔离的栅极 的端部之间的距离, 但由于技术条件限制, 现有技术中无法将同一直线上相 邻电隔离的栅极的端部之间的距离减小为 30nm以下,这是提高集成度所需解 决的问题。
[0007]此外, 在后续的工艺中, 通常要在所述电隔离的栅极两侧形成环绕所 述栅极的侧墙, 由于栅极之间存在切口 16, 在形成侧墙时, 侧墙材料一方面 沉积在所述栅极的两侧,另一方面也会进入切口 16内。由于切口 16非常狭窄, 因此侧墙材料在切口中容易形成空洞等缺陷, 不利于半导体器件的后续加 工, 特别是后续形成金属塞时容易在此短路, 另外如果栅极是伪栅极的话则 在后续形成替代栅时此空洞也使栅极之间发生短路等问题。这降低了由于半 导体器件的性能和稳定性。 发明内容
[0008]本发明的目的在于提供一种半导体结构及其制造方法, 以避免在形成 半导体结构的栅极时出现缺陷, 从而有利于该半导体器件的进一步后续加 工。
[0009】一方面, 本发明提供了一种半导体结构的制造方法, 该方法包括: a ) 在衬底上形成在一方向上延伸的栅极线;
b ) 形成覆盖半导体结构的光刻胶层, 对该光刻胶层构图形成跨所述栅 极线的开口; C ) 通过在开口内形成自组装共聚物, 将所述开口缩小;
d ) 通过所述开口切断所述栅极线中, 使所述栅极线在开口处绝缘。
[0010】相应地, 本发明还提供了一种半导体结构, 该半导体结构包括:
[0011]衬底;
[0012]在一方向上延伸的栅极线, 形成在所述衬底之上, 栅极线的两侧形成 有侧墙;
[0013】绝缘区, 在所述方向上将栅极线与相邻的栅极线隔离, 其中所述绝缘 区在所述方向上的宽度小于 30nm。
[0014]本发明提供的半导体结构的制造方法通过在光刻胶层的开口的内壁 上形成增加层, 减小了在栅宽方向上所述开口相对两壁之间的距离。 在不需 要制作线条非常细小的切断掩模的情况下,也可以减小同一直线上相邻电隔 离的栅极的端部之间的距离。因此节约了面积,提高了半导体器件的集成度。
[0015]另夕卜, 本发明提供的半导体结构及其制造方法与现有的 line-and-cut双 重图形化技术相比, 并不在栅极线上形成切口, 而是采用离子注入的方法在 栅长的方向上形成绝缘层, 以形成电隔离的栅极, 实质上并未物理切断所述 栅极线, 而保留了完整的栅极线。 这样的处理不会形成现有技术中的缺陷, 方便后续加工, 保证了半导体器件的质量。 附图说明
[0016]通过阅读参照以下附图所作的对非限制性实施例所作的详细描述, 本 发明的其它特征、 目的和优点将会变得更明显:
[0017] 图 1至图 4是现有技术中形成半导体结构的栅极的过程中该半导体结 构在各个阶段的俯视结构示意图;
[0018] 图 5是根据本发明提供的方法的一种具体实施方式的流程图;
[0019] 图 6至图 22是根据本发明的一个具体实施方式按照图 5示出的流程
[0020] 图 23至图 25是根据本发明的另一个具体实施方式在形成侧墙和源 / 漏区过程中该半导体结构各个制造阶段的各结构示意图。
[0021]附图中相同或相似的附图标记代表相同或相似的部件。 具体实施方式
[0022]为使本发明的目的、 技术方案和优点更加清楚, 下面将结合附图对本 发明的实施例作详细描述。
[0023]下面详细描述本发明的实施例, 所述实施例的示例在附图中示出, 其 中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功 能的元件。下面通过参考附图描述的实施例是示例性的,仅用于解释本发明, 而不能解释为对本发明的限制。
[0024]下文的公开提供了许多不同的实施例或例子用来实现本发明的不同 结构。 为了简化本发明的公开, 下文中对特定例子的部件和设置进行描述。 当然, 它们仅仅为示例, 并且目的不在于限制本发明。 此外, 本发明可以在 不同例子中重复参考数字和 /或字母。这种重复是为了简化和清楚的目的,其 本身不指示所讨论各种实施例和 /或设置之间的关系。此外,本发明提供了的 各种特定的工艺和材料的例子,但是本领域普通技术人员可以意识到其他工 艺的可应用于性和 /或其他材料的使用。另外, 以下描述的第一特征在第二特 征之"上"的结构可以包括第一和第二特征形成为直接接触的实施例, 也可以 包括另外的特征形成在第一和第二特征之间的实施例,这样第一和第二特征 可能不是直接接触。 在附图中示出了根据本发明实施例的层结构示意图。 这 些图并非是按比例绘制的, 其中为了清楚的目的, 放大了某些细节, 并且可 能省略了某些细节。 图中所示出的各种区域、 层的形状以及它们之间的相对 大小、 位置关系仅是示例性的, 且并未按照实际比例绘制, 此外在实际中可 能由于制造公差或技术限制而有所偏差, 并且本领域技术人员根据实际所需 可以另外设计具有不同形状、 大小、 相对位置的区域 /层。 实施方式进行说明。
[0026]请参考图 5 , 图 5是根据本发明提供的方法的一种具体实施方式的流 程图, 该方法包括:
[0027]步骤 S 101 , 在衬底上形成在一方向上延伸的栅极线;
[0028]步骤 S 102 , 形成覆盖半导体结构的光刻胶层, 对该光刻胶层构图形成 跨所述栅极线的开口;
[0029]步骤 S103 , 通过在开口内形成自组装共聚物, 将所述开口缩小;
[0030]步骤 S 104,通过开口切断所述栅极线中,使所述栅极线在开口处绝缘。
[0031]先参考图 6至图 9, 执行步骤 S101 , 在衬底 100上形成在一方向上延 伸的栅极线 210。 图 6至图 9是根据本发明的半导体结构的制造方法形成栅 极线 210过程中该半导体结构的各向结构示意图。首先参考图 6,在衬底 100 上形成栅极堆叠层 200和光刻胶层 201。 其中, 衬底 100可以包括硅衬底 (例 如硅晶片)。根据现有技术公知的设计要求 (例如 P型衬底或者 N型衬底),衬 底 100可以包括各种掺杂配置。其他实施例中衬底 100还可以包括其他基本 半导体, 例如锗。 或者, 衬底 100可以包括化合物半导体, 例如碳化硅、 砷 化镓、 砷化铟或者磷化铟。 典型地, 衬底 100的厚度可以是但不限于约几百 微米, 例如可以在 400μιη -800μηι的厚度范围内, 根据设计需要, 衬底 100 可以选用体硅, 也可以选用绝缘体上硅(SOI )。 衬底上可以预先形成有浅沟 槽隔离结构, 浅沟槽隔离结构将衬底表面分为独立的有源区。
[0032]光刻胶层 201的材料可是烯类单体材料、含有叠氮醌类化合物的材料 或聚乙烯月桂酸酯材料, 当然也可以根据具体的制造需要选择合适的材料。
[0033]在一方向(图 8中为进出纸面的方向)上延伸的栅极线 210是对栅极 堆叠层 200上的光刻胶构图并进行刻蚀后所得。 首先利用掩模对光刻胶层 300进行曝光并显影以露出栅极堆叠层 200, 以绘制出与将要形成的栅极线 210的图案对应的线形图案, 如图 7所示。 然后进一步对栅极堆叠层 200进 行刻蚀以形成栅极线 210, 再移除光刻胶层 201 , 如图 8所示。 由于形成的 栅极线 210是栅极堆叠,该栅极堆叠包括栅极介质层和所述栅极介质层上的 栅极材料层叠加的结构, 所述栅极介质层在该栅极堆叠中处于紧邻衬底 100 的底层, 通常栅极介质层的材料可以是热氧化层, 包括氧化硅或氮氧化硅, 也可为高 K介质, 例如 HfD2、 HfSiO、 HfSiON, HfTaO, HffiO, HfZrO, A1203、 La203、 Zr02、 LaAlO中的一种或其组合, 其厚度在 lnm〜4nm之间; 栅极材料层可以是 Poly-Si 、 Ti 、 Co、 Ni、 Al、 W、 合金、 金属硅化物或其 组合。 在一些实施例中, 栅极材料层是多层结构, 例如由栅金属层和栅电极 层叠加而成, 其中; 栅金属层的材料可以选用 TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTa中的一种或其组合, 其厚度 在 5nm〜20nm之间 ,栅电极层 203的材料可以选用 Poly-Si,其厚度在 20nm 〜80nm之间。 可选地, 该栅极堆叠还可以包括至少一层覆盖所述栅极材料层 的介质层, 以保护其下的栅极堆叠的其他结构。 参考图 9, 图 8示出的半导 体结构示意图是图 9示出的半导体结构的俯视图沿 B-B方向的剖视结构示意 图。 图 9中可见栅极线 210是在上下的方向上延伸并等间距平行排列。 其他 实施例中, 栅极线的尺寸、 延伸方向和彼此之间的间距可以由半导体器件的 设计需要所决定。
[0034]参考图 10,对栅极堆叠层 200构图形成栅极线 210之后,会露出下方 的有源区 110和浅沟槽隔离结构 120。 可选地, 此时可以在有源区 110中形 成源 /漏区。 形成源漏区可以包括首先在栅极线的两侧形成源 /漏延伸区 , 之 后可以在栅极线的侧壁上形成侧墙, 最后在侧墙的两侧形成源漏区。 形成源 /漏延伸区、 侧墙和源 /漏区的方法在本领域是公知技术, 在此不再赘述。
[0035】在本实施例中, 此处暂时不形成源漏区和侧墙, 下文按此进行描述。
[0036]下一步请参考图 11和图 12, 执行步骤 S102 , 形成覆盖半导体结构的 光刻胶层 300, 对该光刻胶层 300构图形成跨所述栅极线的开口 310。
[0037] 一般地, 光刻胶层 300材料可以是烯类单体材料、 含有叠氮醌类化合 物的材料或聚乙烯月桂酸酯材料。 如图 11所示, 光刻胶层 300形成于整个 半导体结构之上, 即覆盖了栅极线 210和其两侧的衬底 100。需要说明的是, 上述"覆盖"的含义是: 在一些实施例中, 光刻胶层 300直接覆盖栅极线 210 和其两侧的衬底 100; 在另一些实施例中, 根据制造需求, 已形成了覆盖栅 极线 210和其两侧的衬底 100的其他结构, 例如外延应变层, 因此光刻胶层 300直接覆盖该外延应变层。 因此光刻胶层 300与栅极线 210和衬底 100之 间可能存在其他一些结构,只需满足光刻胶层 300处于栅极线 210和衬底 100 之上供构图所用即可。
[0038]参考图 12, 在光刻胶层 300上形成跨栅极线的开口 310。 在光刻胶层 300直接覆盖栅极线的实施例中, 开口 310暴露栅极线 210。 本实施例中, 图 12示出的开口 310暴露了多条栅极线 210, 使后续加工中该多条栅极线 210截断的位置处于同一直线上, 在其他一些实施例中, 开口 310可只暴露 一条栅极线 210, 图 12示出的开口 310的位置只是示例性的。 优选地, 若衬 底 100中已经具有浅沟槽隔离结构 120, 在满足设计要求的情况下, 通常将 开口 310形成于所述浅沟槽隔离结构 120的上方, 这样的布置有助于节约面 积, 提高集成度。 此外, 沿栅宽方向上, 使开口 310的相对两壁之间的距离 小于 50nm, 这样也有助于节约面积, 提高集成度。
[0039】此处, 执行步骤 S103 , 通过在开口内形成自组装共聚物, 将所述开 口缩小。
[0040] 由于下一步需要对开口 310进行处理, 为了更清楚地进行说明技术方 案,请参考图 13 ,图 13是图 12中示出的区域 400中开口 310的局部放大图, 其中, W1代表了开口 310在沿栅宽方向上的相对两壁之间的距离。 在光刻 制版过程中, 受技术水平的影响, 开口 310的尺寸受限, 例如有
30nm≤Wl≤50nm。
[0041]参考图 14, 图 14是在图 13示出的开口 310的内壁形成增加层 320 后的结构示意图。 前文中提到, 优选地, 光刻层 300的材料选用光刻胶, 因 此开口 310的内壁的材料也是光刻胶, 可以在开口 310的内壁的光刻胶上生 长一种自组装共聚物材料, 而生长出来的该自组装共聚物形成增加层 320 , 即增加层 320是自组装共聚物层 320。 所述自组装共聚物材料在光刻胶层上 生长的说明可以参考名为 《 Self-Assembling Materials for Lithographic
Patterning: Overview, Status and Moving Forward》的论文, 该论文发表在国际 光学工程学会 ( SPIE ) 的 7637期 《Alternative Lithographic Technologies II》 之上。该论文中关于所述自组装共聚物的部分详细说明了这种自组装共聚物 材料如何在光刻胶上生长。 根据该自组装共聚物的特性, 暴露的光刻胶上都 会生长出该自组装共聚物, 由于简便起见图 14中只在开口 310的内壁这个 关键位置绘出了生长出来的自组装共聚物, 以说明其在开口 310内的位置关 系。
[0042]在开口 310的内壁形成自组装共聚物层 320后, 由于自组装共聚物层 320具有一定厚度, 因此在栅宽方向上开口 310相对两壁之间的距离变为 W2, W2 < Wl„ 通常 W2小于 30nm, 例如小于 20nm, 甚至小于 10nm。 因 此, 开口 310的内壁覆盖了自组装共聚物层 320后, 在栅宽方向上开口 310 相对两壁之间的距离进一步减小。
[0043】参考图 15 , 开口 310的内壁覆盖自组装共聚物层 320, 因此暴露的栅极 线 210的面积相比自组装共聚物层 320未形成之前更小。通过在光刻胶层的开 口的内壁上形成增加层, 减小了在栅宽方向上所述开口相对两壁之间的距 离, 即减小了同一直线上相邻电隔离的栅极的端部之间的距离, 因此节约了 面积, 提高了半导体器件的集成度。
[0044]接下来参考图 16至图 19, 执行步骤 S104, 通过开口切断所述栅极线 中, 使所述栅极线在开口处绝缘。 具体来说, 本实施例中通过开口 310将离 子注入栅极线 210中 , 使所述栅极线 210在开口 310处绝缘。 在其他实施例 中也可以通过刻蚀、 激光烧蚀等方法在开口 310处切断栅极线。 本实施例中 通过开口 310进行离子注入, 使暴露的栅极线 210发生反应以形成绝缘层 230,该绝缘层 230沿栅长方向截断栅极线 210,使栅极线 210形成电隔离的 栅极。 首先参考图 16, 通过开口 310进行离子注入, 该离子注入通常是氧离 子注入, 使用氧离子注入可以使暴露的栅极线 210受到氧化, 栅极线 210受 到氧化生成的氧化物是绝缘的。请参考图 17, 经过离子注入处理后, 绝缘层 230已经形成, 以氧离子注入为例, 绝缘层 230是由暴露的栅极线 210与所 述氧离子反应生成的氧化物构成, 例如氧化硅、 金属氧化物等(根据所述栅 极堆叠的材料决定)。 参考图 18, 形成绝缘层 230后可移除光刻胶层 300以 便于进行后续加工, 绝缘层 230沿栅长方向截断栅极线 210, 使栅极线 210 形成电隔离的栅极,例如图 18中电隔离的栅极 211和栅极 212。需要说明是, 在本实施例中开口 310不仅暴露了多条栅极线 210,还暴露了部分衬底 100。 但是因为开口的位置一般处于浅沟槽隔离结构之上, 因此注入的氧离子不会 氧化有源区。 为了进一步说明绝缘层 230形成的位置, 请参考图 19, 图 19 是图 18示出的半导体结构沿 C-C方向的剖视结构示意图, 根据氧离子注入 的特性, 可以利用电场控制氧离子的能量, 使暴露的栅极线 210从外表面至 中心被全部氧化 , 以形成绝缘层 230。 从图 19中可知 , 绝缘层 230处于栅极 线 210的截面上, 并完全将原有完整的一条栅极线 210电隔离为两段, 即本 来导电的栅极线 210由于氧离子氧化了暴露的部分而断路,但是保留了完整 的栅极线 210的形状, 并不需要破坏栅极线 210的物理外形, 也不形成物理 意义上的切口, 这是与现有技术的不同之处。
[0045】在形成绝缘层 230后, 可以对该半导体结构进行后续加工, 如图 20 所示 , 在栅极线 210两侧形成围绕栅极线 210的侧墙 220 , 侧墙 220可以由 氮化硅、 氧化硅、 氮氧化硅、 碳化硅和 /或其他合适的材料形成。 侧墙 220 可以具有多层结构。 侧墙 220 可以通过沉积-刻蚀工艺形成, 其厚度范围大 约是 10nm-100nm。 图 20是图 21示出的半导体结构沿 D-D方向的剖视结构 示意图, 参考图 21 , 其中侧墙 220形成在栅极线 210的两侧, 即栅极 211 或栅极 212的两侧, 以保护栅极。 在形成侧墙之前可以先在栅极两侧形成源 漏延伸区。 形成侧墙之后可以在侧墙之外形成源漏区, 在此不在赘述。
[0046】此外根据半导体结构的设计需要, 在形成侧墙 220后, 可以形成至少 一层覆盖栅极线 210、 侧墙 220和衬底 100的应变层 400, 该应变层用于增 加应力以提升半导体器件的性能, 如图 22所示。
[0047】可选地, 可以先形成侧墙 220和至少一层应变层 400, 再形成绝缘层 230。 即形成绝缘层 230的步骤可以最后执行。 参考前述的具体实施方式, 先形成如图 10所示的栅极线 210组成的图形, 然后形成图 23所示的半导体 结构 , 即先在栅极线 210两侧形成源漏延伸区、 侧墙 220和源漏区。 图 24 是图 23示出的半导体结构沿 E-E方向的剖视结构示意图, 下一步可以形成 至少一层覆盖栅极线 210、侧墙 220和衬底 100的应变层 400,如图 25所示。 然后进行形成绝缘层 230的工艺步骤。 本具体实施方中, 侧墙 220和应变层 400的形成方法均可参考前述具体实施方式中相关部分的描述, 形成绝缘层 230的方法也可以参考前述具体实施方式, 需要指出的是, 由于本具体实施 方式中应变层 400覆盖栅极线 210, 因此一些实施例中, 在光刻胶层 300上 形成的开口 310暴露了栅极线 210应变层 400。 相应地, 需要调整氧离子注 入的能量和剂量, 使其穿过应变层 400并完全氧化其下的栅极线 210。
[0048]本发明的技术方案中,形成绝缘层 230的步骤可以在侧墙 220形成后 执行, 可以在侧墙 220和应变层 400都形成后执行 (通常地, 应变层 400在 侧墙 220形成后才形成), 也可以在侧墙 220和应变层 400形成前执行, 因 此在制造步骤上自由度高, 可以编排为多种制造流程。 但是需要指出的是, 形成绝缘层 230 (即形成电隔离的栅极)的步骤应该在形成与源 /漏区接触的 接触塞之前。 程,在形成绝缘层 230后可以包括如下步骤:形成至少一层覆盖所述栅极线、 侧墙和源 /漏区的介质层(若该半导体结构已形成应变层 400, 则所述至少一 层介质层覆盖应变层 400 ), 嵌于该至少一层介质层中的接触塞与源 /漏区 100 , 和 /或所述栅极电连接。 所述至少一层介质层可以通过化学气相沉积 ( Chemical vapor deposition , CVD )、 高密度等离子体 CVD或其他合适的 方法形成在衬底 100上, 其材料包括 Si02、 碳掺杂 Si02、 BPSG (硼磷硅玻 璃)、 PSG (磷硅玻璃)、 USG (无掺杂硅玻璃)、 氮氧化硅、 低 k材料或其 组合。 所述接触塞的材料可以是 W、 Al、 TiAl合金中任一种或其组合。
[0050]本发明提供的半导体结构及其制造方法与现有的 line-and-cut双重图 形化技术相比, 并不在栅极线上形成切口, 而是采用离子注入的方法在栅长 的方向上形成绝缘层, 以形成电隔离的栅极, 并不需要破坏栅极线 210的物 理外形, 也不形成物理意义上的切口, 而保留了完整的栅极线 210。 在接下 来形成介质层的过程中, 本发明的处理不会导致现有技术中的缺陷, 方便后 续加工,保证了半导体器件的质量。此外,形成绝缘层 230不受形成侧墙 220 和应变层 400限制,因此在制造步骤上自由度高,可以编排为多种制造流程, 可以满足更多的应用场景。
[0051]下面阐述本发明提供的半导体结构的优选结构,请参考图 20和图 21 , 图 21是本发明提供的半导体结构的一种具体实施方式的俯视结构示意图, 在该优选实施方式中, 半导体结构包括:
[0052]衬底 100;
[0053]在一方向上延伸的栅极线 210, 形成在所述衬底之上, 栅极线的两侧 形成有侧墙 220;
[0054】绝缘区 230, 在所述方向上将栅极线 210与相邻的栅极线 210隔离, 其 中所述绝缘区 230在所述方向上的宽度小于 30nm, 优选小于 20nm, 更优选小 于 10nm。
[0055】其中, 衬底 100包括硅衬底 (例如晶片)。 根据现有技术公知的设计要 求 (例如 P型衬底或者 N型衬底), 衬底 100可以包括各种掺杂配置。 其他实 施例中衬底 100还可以包括其他基本半导体, 例如锗。 或者, 衬底 100可以 包括化合物半导体, 例如碳化硅、 砷化镓、 砷化铟或者磷化铟。 典型地, 衬 底 100的厚度可以是但不限于约几百微米, 例如可以在 400μιη -800μιη的厚 度范围内。衬底 100上可以形成有浅沟槽隔离结构 120,浅沟槽隔离结构 120 将衬底 100表面分为独立的有源区 110。
[0056]栅极线 210是栅极堆叠,该栅极堆叠包括栅极介质层和所述栅极介质 层上的栅极材料层叠加的结构, 所述栅极介质层在该栅极堆叠中处于紧邻衬 底 100的底层, 通常栅极介质层的材料可以是热氧化层, 包括氧化硅、 氮氧 化硅,也可为高 Κ介质,例如 Hf02、 HfSiO、 HfSiON, HfTaO, HffiO, HfZrO , A1203、 La203、 Zr02、 LaAlO中的一种或其组合, 其厚度在 lnm〜4nm之间; 栅极材料层可以是 Poly-Si 、 Ti 、 Co、 Ni、 Al、 W、 合金、 金属硅化物或其 组合。 在一些实施例中, 栅极材料层是多层结构, 例如由栅金属层和栅电极 层叠加而成, 其中; 栅金属层的材料可以选用 TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTa中的一种或其组合, 其厚度 在 5nm〜20nm之间 ,栅电极层 203的材料可以选用 Poly-Si,其厚度在 20nm 〜80nm之间。 可选地, 该栅极堆叠还可以包括至少一层覆盖所述栅极材料层 的介质层, 以保护其下的栅极堆叠的其他结构。 栅极线的尺寸和彼此之间的 间距由半导体器件的设计需要所决定, 一般地, 栅极线平行排列。
[0057】此外, 侧墙 220形成在所述栅极线的两侧, 并围绕所述栅极线。 侧墙 220可以由氮化硅、 氧化硅、 氮氧化硅、 碳化硅和 /或其他合适的材料形成。 侧墙 220可以具有多层结构。 侧墙 220可以通过沉积-刻蚀工艺形成, 其厚 度范围大约是 10nm-100nm。 源 /漏区可以形成在衬底 100的有源区 120中, 通常地 , 源 /漏区形成在栅极线 210形成之后。
[0058]绝缘层 230沿栅长方向截断栅极线 210, 使栅极线 210形成电隔离的 栅极,例如栅极 211和栅极 212等。栅极 211和栅极 212处于同一栅极线 210 上, 两者被绝缘层 230断路而形成电隔离。 通常绝缘层 230的材料是形成的 所述栅极堆叠的材料(即栅极线的材料)的氧化物, 例如氧化硅、 金属氧化 物等绝缘材料, 其不同于侧墙 220的材料。 这与现有技术中依靠侧墙材料来 隔离相部栅极的末端不同。 优选地, 绝缘层 230形成在浅沟槽隔离结构 120 的上方, 这样有助于节省面积, 提高集成度。 沿栅宽方向上, 绝缘层 230的 厚度小于 50nm, 例如 10nm。
[0059] 由于形成绝缘层 230是采用的是离子注入方法, 例如注入氧离子。
[0060]为了进一步说明绝缘层的结构,请参考图 20, 图 20是图 21示出的半 导体结构沿 D-D方向的剖视结构示意图, 如图所示, 栅极线 210被绝缘层 230所截断形成电隔离。
[0061]可选地, 如图 22所示, 该半导体结构还包括至少一层应变层 400, 应 变层 400覆盖栅极线 210、 侧墙 220和源 /漏区, 用于提供应力以提升半导体 器件的性能。
[0062]可选地, 该半导体结构还包括至少一层覆盖所述栅极线、 侧墙和源 / 漏区的介质层(若该半导体结构已形成应变层 400, 则所述至少一层介质层 覆盖应变层 400 ), 嵌于该至少一层介质层中的接触塞与源 /漏区 100, 和 /或 所述栅极电连接。所述至少一层介质层的材料包括 Si02、碳掺杂 Si02、 BPSG (硼磷硅玻璃)、 PSG (磷硅玻璃)、 USG (无掺杂硅玻璃)、 氮氧化硅、 低 k 材料或其组合。 所述接触塞的材料可以是 W、 Al、 TiAl合金中任一种或其组 合。
[0063]需要说明的是,在同一个半导体器件中可以包括上述具体实施方式提 供的半导体结构, 也可以包括其他半导体结构。
[0064] 虽然关于示例实施例及其优点已经详细说明,应当理解在不脱离本发 明的精神和所附权利要求限定的保护范围的情况下, 可以对这些实施例进行 各种变化、 替换和修改。 对于其他例子, 本领域的普通技术人员应当容易理 解在保持本发明保护范围内的同时, 工艺步骤的次序可以变化。
[0065]此外, 本发明的应用范围不局限于说明书中描述的特定实施例的工 艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容, 作 为本领域的普通技术人员将容易地理解,对于目前已存在或者以后即将开发 出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤, 其中它们执行与本 发明描述的对应实施例大体相同的功能或者获得大体相同的结果,依照本发 明可以对它们进行应用。 因此,本发明所附权利要求旨在将这些工艺、机构、 制造、 物质组成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1、 一种半导体结构的制造方法, 包括:
a )在衬底上形成在一方向上延伸的栅极线;
b )形成覆盖半导体结构的光刻胶层, 对该光刻胶层构图形成跨所述栅 极线的开口;
c )通过在开口内形成自组装共聚物, 将所述开口缩小;
d )通过所述开口切断所述栅极线中, 使所述栅极线在开口处绝缘。
2、 根据权利要求 1所述的方法, 其中步骤 d ) 包括通过所述开口将离子 注入所述栅极线中, 使所述栅极线在开口处绝缘。
3、 根据权利要求 2所述的方法, 其中
所述离子注入是氧离子注入。
4、 根据权利要求 1所述的方法, 其中:
所述开口位于衬底中的浅沟槽隔离的上方。
5、 根据权利要求 2所述的方法, 其中, 在步骤 b )执行前该方法还包括: e )在所述栅极线的两侧形成侧墙。
6、 根据权利要求 5所述的方法, 其特征在于, 在步骤 e )执行后, 步骤 b ) 执行前, 该方法还包括:
e )形成至少一层覆盖所述栅极线和侧墙的应变层。
7、 一种半导体结构, 包括:
衬底;
在一方向上延伸的栅极线, 形成在所述衬底之上, 栅极线的两侧形成有 侧墙; 绝缘区, 在所述方向上将栅极线与相邻的栅极线隔离, 其中所述绝缘区 在所述方向上的宽度小于 30nm。
8、 根据权利要求 7所述的半导体结构, 其中:
所述绝缘区的材料是氧化物。
9、 根据权利要求 7所述的半导体结构, 其中:
所述绝缘区形成在浅沟槽隔离结构之上。
10、 根据权利要求 7所述的半导体结构, 其中:
所述绝缘区在所述方向上的宽度小于 20nm。
11、 根据权利要求 10所述的半导体结构, 其中:
所述绝缘区在所述方向上的宽度小于 10nm。
PCT/CN2013/080151 2013-01-06 2013-07-26 半导体结构及其制造方法 WO2014106376A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/652,956 US9397007B2 (en) 2013-01-06 2013-07-26 Method for manufacturing semiconductor structure through forming an additional layer inside opening of a photoresist layer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210543567.4A CN103915321A (zh) 2013-01-06 2013-01-06 半导体结构及其制造方法
CN201210543567.4 2013-01-06

Publications (1)

Publication Number Publication Date
WO2014106376A1 true WO2014106376A1 (zh) 2014-07-10

Family

ID=51040918

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/080151 WO2014106376A1 (zh) 2013-01-06 2013-07-26 半导体结构及其制造方法

Country Status (3)

Country Link
US (1) US9397007B2 (zh)
CN (1) CN103915321A (zh)
WO (1) WO2014106376A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102404973B1 (ko) 2015-12-07 2022-06-02 삼성전자주식회사 반도체 장치
US10613438B2 (en) 2018-01-15 2020-04-07 International Business Machines Corporation Self-aligned patterning methods which implement directed self-assembly
CN115706053A (zh) * 2021-08-12 2023-02-17 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201044439A (en) * 2009-01-12 2010-12-16 Ibm Method for reducing tip-to-tip spacing between lines
CN102347277A (zh) * 2010-07-30 2012-02-08 中国科学院微电子研究所 半导体器件结构及其制作方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5694188A (en) * 1994-09-17 1997-12-02 Kabushiki Kaisha Toshiba Reflection type liquid crystal display device having comb-shaped wall electrode
US6939794B2 (en) * 2003-06-17 2005-09-06 Micron Technology, Inc. Boron-doped amorphous carbon film for use as a hard etch mask during the formation of a semiconductor device
US7067435B2 (en) * 2004-09-29 2006-06-27 Texas Instruments Incorporated Method for etch-stop layer etching during damascene dielectric etching with low polymerization
US7514339B2 (en) * 2007-01-09 2009-04-07 International Business Machines Corporation Method for fabricating shallow trench isolation structures using diblock copolymer patterning
JP2009081420A (ja) * 2007-09-07 2009-04-16 Nec Electronics Corp 半導体装置の製造方法
US7785946B2 (en) * 2007-09-25 2010-08-31 Infineon Technologies Ag Integrated circuits and methods of design and manufacture thereof
US20090191711A1 (en) * 2008-01-30 2009-07-30 Ying Rui Hardmask open process with enhanced cd space shrink and reduction
JP2010041028A (ja) * 2008-07-11 2010-02-18 Tokyo Electron Ltd 基板処理方法
US8507840B2 (en) * 2010-12-21 2013-08-13 Zena Technologies, Inc. Vertically structured passive pixel arrays and methods for fabricating the same
JP5180121B2 (ja) * 2009-02-20 2013-04-10 東京エレクトロン株式会社 基板処理方法
US7759239B1 (en) * 2009-05-05 2010-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of reducing a critical dimension of a semiconductor device
US8728945B2 (en) * 2010-11-03 2014-05-20 Texas Instruments Incorporated Method for patterning sublithographic features
JP5981106B2 (ja) * 2011-07-12 2016-08-31 東京エレクトロン株式会社 プラズマエッチング方法
US8946806B2 (en) * 2011-07-24 2015-02-03 Globalfoundries Singapore Pte. Ltd. Memory cell with decoupled channels
US8877642B2 (en) * 2013-02-01 2014-11-04 Globalfoundries Inc. Double-pattern gate formation processing with critical dimension control
US8883648B1 (en) * 2013-09-09 2014-11-11 United Microelectronics Corp. Manufacturing method of semiconductor structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201044439A (en) * 2009-01-12 2010-12-16 Ibm Method for reducing tip-to-tip spacing between lines
CN102347277A (zh) * 2010-07-30 2012-02-08 中国科学院微电子研究所 半导体器件结构及其制作方法

Also Published As

Publication number Publication date
CN103915321A (zh) 2014-07-09
US9397007B2 (en) 2016-07-19
US20150332973A1 (en) 2015-11-19

Similar Documents

Publication Publication Date Title
KR101985593B1 (ko) 금속 게이트 구조물 및 그 방법
US10347751B2 (en) Self-aligned epitaxy layer
US9660033B1 (en) Multi-gate device and method of fabrication thereof
US9153657B2 (en) Semiconductor devices comprising a fin
US7659157B2 (en) Dual metal gate finFETs with single or dual high-K gate dielectric
WO2014032338A1 (zh) 半导体结构及其制造方法
CN103855015B (zh) FinFET及其制造方法
US10263111B2 (en) FinFET and method for manufacturing the same
US20140035051A1 (en) Semiconductor device and associated methods
KR20130046338A (ko) 핀형 전계 효과 트랜지스터(finfet) 기반 금속-반도체 합금 퓨즈 장치 및 이러한 장치를 제조하는 방법
CN106711143B (zh) 鳍式场效晶体管结构及其制造方法
KR20110107852A (ko) 로직 트랜지스터들과 집적된 프로그램가능 하이-케이/금속 게이트 메모리 트랜지스터들을 위한 스페이서 및 게이트 유전체 구조 및 그 구조를 형성하는 방법
WO2013000268A1 (zh) 一种半导体结构及其制造方法
US9583622B2 (en) Semiconductor structure and method for manufacturing the same
WO2013026213A1 (zh) 半导体器件结构及其制作方法
KR100414735B1 (ko) 반도체소자 및 그 형성 방법
WO2014106376A1 (zh) 半导体结构及其制造方法
JP2009055027A (ja) Mosトランジスタの製造方法、および、これにより製造されたmosトランジスタ
WO2013170477A1 (zh) 半导体器件及其制造方法
WO2013143032A1 (zh) 半导体器件及其制造方法
US11688791B2 (en) Gate structure and method
WO2014131239A1 (zh) 半导体器件及其制造方法
WO2013010340A1 (zh) 半导体器件结构及其制作方法
WO2014071666A1 (zh) 半导体器件及其制造方法
WO2013000197A1 (zh) 一种半导体结构及其制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13870357

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 14652956

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13870357

Country of ref document: EP

Kind code of ref document: A1