WO2015000204A1 - FinFET器件及其制作方法 - Google Patents

FinFET器件及其制作方法 Download PDF

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Publication number
WO2015000204A1
WO2015000204A1 PCT/CN2013/080887 CN2013080887W WO2015000204A1 WO 2015000204 A1 WO2015000204 A1 WO 2015000204A1 CN 2013080887 W CN2013080887 W CN 2013080887W WO 2015000204 A1 WO2015000204 A1 WO 2015000204A1
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Prior art keywords
protrusions
etching
fin
source
drain regions
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PCT/CN2013/080887
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English (en)
French (fr)
Inventor
殷华湘
马小龙
徐唯佳
徐秋霞
朱慧珑
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中国科学院微电子研究所
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Priority to US14/397,822 priority Critical patent/US9391073B2/en
Publication of WO2015000204A1 publication Critical patent/WO2015000204A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a novel FinFET device having a continuous raised surface and a method of fabricating the same. Background technique
  • a three-dimensional multi-gate device In the current sub-20nm technology, a three-dimensional multi-gate device (FinFET or Tri-gate) is the main device structure, which enhances the gate control capability and suppresses leakage and short channel effects.
  • a double-gate SOI-structured MOSFET can suppress short channel effect (SCE) and drain induced induced barrier lowering (DIBL) effects compared to conventional single-gate Si or SOI MOSFETs, with lower junction capacitance.
  • the threshold voltage can be adjusted by setting the work function of the metal gate, which can obtain about 2 times the driving current, which reduces the requirement for effective gate oxide thickness (EOT).
  • EOT effective gate oxide thickness
  • the gate of the tri-gate device surrounds the top surface of the channel region and the two sides, and the gate control capability is stronger. Further, full surround nanowire multi-gate devices are more advantageous.
  • the ring-gate nanowire device has better gate control effect and can effectively control the short channel effect, it has advantages in the reduction process of the sub-14 nanometer technology, but a key problem is due to the tiny conductive channel. No more drive current can be provided in the equivalent silicon planar area.
  • d is the diameter of a single nanowire (r)
  • n is the number of nanowires
  • s is the spacing between the nanowires. Therefore, for the case where the diameter d is 3, 5, 7, and lOnm, respectively, the nanowire spacing s Must be less than 6.4, 10.6, 15, and 21. 4 nm, respectively. That is, if a gate width equivalent to 1 ⁇ m of bulk silicon is to be obtained, the parallel arrangement of the nanowire devices is very tight. According to the existing FinFET Exposure and etching techniques (with a Fin pitch of around 60 nm) make it difficult to achieve such a very small pitch nanowire arrangement.
  • a stacked ring-gated nanowire structure in the vertical direction is an effective method to increase the transistor drive current, but it is very difficult to implement the process (manufacturing method), and it is a major challenge to be compatible with the conventional process and reduce the process cost.
  • one existing implementation of stacking nanowires is to use Si/SiGe multilayer heteroepitaxial and selective etching, that is, sequentially stacking a plurality of Si and SiGe layers on the buried oxide layer (BOX). The SiGe is then selectively removed by methods such as wet etching, thereby leaving a stack of Si nanowires. This method is severely affected by the quality of the epitaxial thin layer, which greatly increases the process Ben.
  • the conventional structure under the unit footprint area, the conventional structure (with gate fill between the nanowire stacks, that is, each nanowire is surrounded by the gate stack of HK/MG) has a small effective total current.
  • the effective cross-sectional area of the fins (fins, Fin) of the non-stacked nanowires (which is perpendicular to the direction in which the Fin or the nanowire extends, that is, perpendicular to the channel direction) is larger.
  • the object of the present invention is to overcome the above technical difficulties, and to provide a novel device structure and a manufacturing method thereof, which sufficiently increase the effective width of the conductive channel to increase the driving current.
  • the present invention provides a method of fabricating a FinFET device, comprising: forming a plurality of fin structures extending in a first direction on a substrate; forming a plurality of protrusions on a side of each fin structure in a second direction Forming a gate stack structure extending in the second direction on the fin structure; forming source and drain regions on both sides of the gate stack structure, and the fin structure between the source and drain regions constitutes a channel region.
  • the sides of the fin structure are treated by dry etching and/or wet etching to form a plurality of protrusions.
  • the process parameters for controlling etching and/or etching are such that the shapes of the plurality of protrusions include a rectangle, a triangle, a trapezoid, an inverted trapezoid, a ⁇ , a C, a D, a circle, an ellipse, a sector, a diamond, and a combination thereof.
  • the plurality of protrusions are periodic, and/or continuous, and/or discrete.
  • the dry etching includes an isotropic plasma dry etching or reactive ion etching having a lateral etching depth, or a combination method of isotropic dry etching and anisotropic dry etching.
  • wet etching includes a wet etching method using selective etching in different crystal directions.
  • the method further comprises: performing a surface treatment and a rounding process on the sidewall of the fin.
  • the present invention also provides a FinFET device, comprising: a plurality of fin structures extending in a first direction on a substrate; a plurality of gate stacks extending in a second direction and spanning each fin structure; a source/drain region located on each side of the gate stack along the second direction; a plurality of channel regions formed by fin structures between the plurality of source and drain regions; wherein each fin structure is along the second direction
  • the side wall has a plurality of protrusions.
  • the shape of the plurality of protrusions includes a rectangle, a triangle, a trapezoid, an inverted trapezoid, a ⁇ , a C, a D, a circle, an ellipse, a sector, a diamond, and a combination thereof.
  • the plurality of protrusions are periodic, and/or continuous, and/or discrete.
  • the height/thickness of the plurality of protrusions is less than 5% of the thickness/width of the fin structure.
  • a continuous protrusion particularly an arc surface, is formed on the side of the fin.
  • the ability to suppress the short channel effect is increased, and the total effective cross-sectional area of the channel is increased under the same planar projection area, thereby improving the overall performance of the device.
  • 1 to 8 are schematic cross-sectional views showing respective steps of a method of fabricating a FinFET according to the present invention
  • Figure 9 is a perspective view showing the structure of a FinFET device in accordance with the present invention.
  • FIG. 9 is a perspective view of a FinFET device fabricated in accordance with the present invention, including a plurality of fin structures extending in a first direction on a substrate, extending in a second direction and spanning a plurality of gates of each fin structure Stacking, a plurality of source and drain regions on both sides of the fin structure extending in the first direction, a plurality of channel regions formed by a portion of the fin structure between the plurality of source and drain regions, wherein the fin structure is along the second direction
  • the sides have continuous protrusions, such as arcuate surfaces.
  • the left part of the following figure is a cross-sectional view perpendicular to the channel direction (in the second direction, that is, the XX' axis) in FIG. 9, and the right part of the figure is parallel to FIG.
  • a plurality of fin structures extending in a first direction are formed, wherein the first direction is a direction in which the channel region of the device is extended.
  • the substrate 1 is provided, and the substrate 1 is appropriately selected according to the needs of the device, and may include single crystal silicon (Si), single crystal germanium (Ge), strained silicon (Strained Si), germanium silicon (SiGe), or a compound semiconductor material, for example.
  • the substrate 1 is preferably a body Si for compatibility with a CMOS process. Photolithography/etching of the substrate 1, a plurality of fins 1F formed by a plurality of trenches 1G distributed in the first direction and a substrate 1 material remaining between the trenches 1G are formed in the substrate 1.
  • the aspect ratio of the trench 1G is preferably greater than 5:1.
  • a hard mask layer HM is deposited on top of the plurality of fin structures, which may be made of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, and is preferably silicon nitride.
  • each fin structure 1F is etched to form a side surface of the fin structure IF in a second direction perpendicular to the first direction.
  • Continuous protrusion 1P Preferably, the side of each fin structure 1F is laterally etched in a second direction perpendicular to the first direction (the YY' axis in FIG. 9) by dry or wet etching using HM as a mask.
  • the side of 1F forms a continuous outward (vertical from the center of 1F toward the side surface) protrusion 1P, that is, the protrusion IP is formed by a plurality of identical or similar protrusions lPi, and the plurality of lPi may be periodically distributed or discretely distributed. .
  • the etching process for etching the 1F to form the protrusions 1P may be an isotropic fluorine-based or chlorine-based plasma dry etching, or TMAH wet etching, and selecting process parameters such as etching temperature to improve etching to the side.
  • the step of laterally etching the fins includes an isotropic plasma dry etch having a lateral etch depth, or a combination of isotropic etch and anisotropic etch.
  • the step of laterally etching the fins includes a wet etching method that utilizes different crystal orientation selective etching.
  • the etching process is reactive ion etching (RIE), and the etching gas includes a fluorine-based or chlorine-based gas such as NF 3 , SF 6 , CF 4 , CH 2 F 2 , CH 3 F, CHF 3 , Cl 2 And so on.
  • RIE reactive ion etching
  • the shape of the protrusion lPi can be controlled to be rectangular, triangular, trapezoidal, inverted trapezoidal, ⁇ -shaped (multi-section broken line connected), C-shaped (more than 1/2 curved surface, the curved surface can be round surface, elliptical surface, double Surfaces), D-shapes (1/2 surfaces, surfaces can be round faces, elliptical faces, hyperboloids), circles, ellipses, scallops, diamonds, and other polygons or surfaces.
  • the protrusion 1P is a continuous arc surface formed by a plurality of arc segments lPi (including a semicircle, an ellipse, or a portion of a circle having other angles) (the continuous arc surface helps to improve Uniformity of electric field distribution in the channel region of the fin improves device reliability).
  • the protrusion 1P is a continuous rough surface formed by a periodically distributed triangular or trapezoidal connection, or a composite surface in which a smooth surface and a rough surface are periodically combined, or an irregular protrusion.
  • the discrete raised surfaces, i.e., the protrusions 1P are periodic, continuous, or discrete.
  • the height/thickness of the plurality of protrusions 1P is less than 5% of the thickness/width of the fin structure 1F, for example, only 1 to 5 nm.
  • the protrusions 1P are continuously formed by the same sub-protrusions lPi in order to obtain uniform channel electrical properties.
  • the protrusion 1P is treated by surface treatment, rounding or the like to be rounded to obtain a smoother surface.
  • surface treatment is a method of surface etching followed by wet micro-etching, and the surface oxidation process includes furnace temperature oxidation or oxidation of a strong oxidizing agent solution.
  • Surface treatment, rounding and other processes can also choose hydrogen high temperature baking.
  • Surface treatment, rounding and other processes can also choose isotropic etching of silicon and the like.
  • a filling material such as silicon oxide, silicon oxynitride, silicon oxycarbide, low-k, or the like is deposited in a trench 1G between the fins 1F by a process such as PECVD, HDPCVD, RT0 (rapid thermal oxidation).
  • the dielectric layer is isolated to form a shallow trench isolation (STI) 2.
  • the STI 2 is then planarized using a CMP, etch back, etc. process until the hard mask layer HM is exposed.
  • STI2 is etched back, exposing most of the fin 1F, for example, leaving only the bottom of the fin 1F (for example, 1/10 to 1/5 of the height of the entire fin 1F) buried in the STI 2.
  • STI2 can be removed by wet etching with HF-based etching solution, or by fluorine-based plasma dry etching.
  • STI2 is etched down to expose most of the fins 1F.
  • the exposed fins 1F will Used as the channel region for later devices, the bottommost portion will be etched to serve as the isolation region for the device.
  • the hard mask layer HM is then removed by wet etching.
  • the dummy gate stacked layer is filled.
  • a silicon oxide pad oxide layer 3 is deposited on the STI2 and the fin 1F by LPCVD, PECVD, HDPCVD, RT0, chemical oxidation, etc., for protecting the fin 1F from being overetched in the subsequent etching process.
  • the dummy gate layer 4 is formed on the pad oxide layer 3 by a deposition method such as PECVD, HDPCVD, M0CVD, MBE, ALD, evaporation, sputtering, etc., and the material may be polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, polycrystalline. ⁇ , amorphous enamel, etc. and combinations thereof.
  • the thickness of each of the above layers is not necessarily set according to the ratio shown in the drawings, but is appropriately set according to the specific device size and electrical performance requirements.
  • the dummy gate stack 3/4 surrounds the top of the fin 1F and the side of the surface protrusion 1P.
  • the dummy gate stack layer 3/4 is etched to form a dummy gate stack structure that spans the fins 1F in the second direction.
  • the dummy gate stack 3/4 is etched until the top of the fin 1F is exposed, and the partial layer 3/4 on both sides of the first direction of the fin 1F is removed, only in the fin 1F.
  • a plurality of dummy gate stack structures are left on top (only one is shown in the figure).
  • source and drain regions 1S/1D are formed on both sides of the fin 1F in the first direction.
  • the fins 1F are etched until the substrate 1 is exposed, and the lifted source and drain regions 1S and 1D are selectively epitaxially formed by UHVCVD, M0CVD, ALD, MBE, atmospheric pressure epitaxy, etc., and the material thereof may be Same as the substrate 1 is Si; or for PMOS, the source and drain regions may be SiGe, SiSn, GeSn, Si, etc., and combinations thereof, thereby applying compressive stress to the channel region 1C to improve hole mobility; In the case of NM0S, the source/drain regions may be Si: C, Si: H, SiGe: C, Si, or the like, and combinations thereof, thereby applying tensile stress to the channel region 1C to increase electron mobility.
  • the doping is simultaneously in-situ doped epitaxially or after doping and annealing is performed after epitaxy such that the source and drain regions 1S/D have different doping types and concentrations than the substrate 1 to control the electrical characteristics of the device.
  • the top of the source/drain region 1S/D can be higher than the top of the fin 1F.
  • the sidewall spacer 5 may be formed on the side of the fin 1F in the first direction, and the light-doped source-drain extension region and the heavily doped source-drain region (both not shown separately) may be formed by the sidewall spacer 5.
  • the post-gate process is used to complete the subsequent fabrication.
  • An interlayer dielectric layer (ILD) 6 is formed over the entire device, wet etching removes the dummy gate stack 3/4, leaving a gate trench (not shown) in the ILD 6, in turn in the gate trench
  • a gate insulating layer 7 of a high-k material and a gate conductive layer 8 of a metal material are deposited to form a gate stack structure.
  • the CMP planarizes the gate stack until the ILD 6 is exposed.
  • a source/drain contact hole (not shown) is etched in the ILD 6 to reach the source/drain region 1S/D, and a barrier layer of a metal nitride and a conductive layer of a metal material are deposited in the source/drain contact hole to form Source and drain contact plugs (not shown).
  • FIG. 9 A perspective view of the finally formed device structure is shown in FIG. 9, comprising: a plurality of fin structures extending in a first direction on the substrate, extending in a second direction and spanning a plurality of gate stacks of each fin structure, a plurality of source and drain regions on both sides of the fin structure extending in the first direction, and a fin structure located between the plurality of source and drain regions constitutes a plurality of channel regions, wherein the fin structure has a continuous side along the second direction
  • Protrusions protrusions include rectangles, triangles, trapezoids, inverted trapezoids, cymbals (multiple sections of broken lines), C shape (more than 1/2 surface, surface can be round face, ellipse face, hyperboloid), D shape (1/2 surface, surface can be round face, ellipse face, hyperboloid), circle, ellipse, fan , diamonds, and other polygons or surfaces, the protrusions can be periodically distributed or discrete.
  • a continuous protrusion is formed on the side of the fin, thereby improving the ability to suppress the short channel effect, and increasing the effective total cross section of the channel under the same plane projection area. Area, which improves overall device performance.

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Abstract

本发明公开了一种FinFET器件及其制造方法，包括：多个鰭片结构，在衬底上沿第一方向延伸；多个栅极堆叠，沿第二方向延伸并且跨越了每个鰭片结构；多个源漏区，位于每个栅极堆叠沿第二方向两侧；多个沟道区，由位于多个源漏区之间的鰭片结构构成；其中，每个鰭片结构沿第二方向的侧壁具有多个突起。依照本发明的FinFET器件及其制作方法，在鰭片侧面形成连续突起特别是弧线表面，提高了抑制短沟道效应的能力，同时在同一平面投影面积下增大了沟道有效导电总截面面积，从而提高了器件总体性能。

Description

FinFET器件及其制作方法 本申请要求了 2013年 7月 2日提交的、 申请号为 201310275191. 8、 发明名称为 "FinFET器 件及其制作方法" 的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及一种半导体器件及其制造方法， 特别是涉及一种新型的具有连续突起表面的 FinFET器件及其制作方法。 背景技术
在当前的亚 20nm技术中， 三维多栅器件 （FinFET或 Tri-gate )是主要的器件结构， 这种结构增强了栅极控制能力、 抑制了漏电与短沟道效应。
例如， 双栅 S0I结构的 M0SFET与传统的单栅体 Si或者 SOI M0SFET相比， 能够抑制短沟 道效应（SCE) 以及漏致感应势垒降低 （DIBL)效应， 具有更低的结电容， 能够实现沟道轻掺 杂， 可以通过设置金属栅极的功函数来调节阈值电压， 能够得到约 2倍的驱动电流， 降低了 对于有效栅氧厚度（EOT) 的要求。 而三栅器件与双栅器件相比， 栅极包围了沟道区顶面以及 两个侧面， 栅极控制能力更强。 进一步地， 全环绕纳米线多栅器件更具有优势。
环栅纳米线器件虽然有更好的栅控作用， 能更有效的控制短沟道效应， 在亚 14纳米技术 的缩减过程中更具优势， 但是一个关键问题是由于微小的导电沟道， 在等效硅平面面积内不 能提供更多的驱动电流。
例如， 对于等效线宽 Ι μ πι 的器件而言， 环栅纳米线器件的尺寸要满足： d*n+ (n-l) *S = l m, 并且 3ΐ *(1*η>1 μ πι。 其中， d为单个纳米线 （爾） 的直径， n为纳米线的数目， s为 纳米线之间的间距。 因此， 对于直径 d分别为 3、 5、 7、 lOnm的情形而言， 纳米线间距 s必 须分别小于 6. 4、 10. 6、 15、 21. 4nm。 也即， 如果要获得等同于体硅 1 μ m的栅宽， 纳米线器 件的平行排列要非常的紧密。依据现有的 FinFET曝光和刻蚀技术（Fin间距在 60纳米左右）， 制作这种极小间距的纳米线立体排列结构是很难实现的。
在垂直方向上实现堆叠环栅纳米线结构是提高晶体管驱动电流的有效方法， 但在实现工 艺 （制作方法上） 十分困难， 与传统工艺兼容并减少工艺成本面临重大挑战。 例如， 一种现 有的实现堆叠纳米线的是利用 Si/SiGe多层异质外延并进行选择腐蚀， 也即在埋氧层 （BOX) 上依次交替异质外延多个 Si与 SiGe的层叠，然后通过例如湿法腐蚀等方法选择性去除 SiGe， 从而留下 Si纳米线的堆叠。这种方法严重受制于外延薄层质量的影响， 极大的增加了工艺成 本。 另一方面， 在单位 footprint面积下， 传统结构 （纳米线堆叠之间有栅极填充， 也即每 个纳米线四周均被 HK/MG的栅极堆叠环绕） 的堆叠纳米线有效总电流较小， 而在同一投影面 积下， 非堆叠纳米线的鰭片 （翅片， Fin) 的导通有效截面积 （垂直于 Fin或者纳米线延伸方 向截得， 也即垂直于沟道方向） 更大。
因此， 需要寻找一种充分增大导电沟道有效宽度提高驱动电流的新型器件结构及其制造 方法。 发明内容
由上所述， 本发明的目的在于克服上述技术困难， 提出一种新型器件结构及其制造方法， 充分增大导电沟道有效宽度从而提高驱动电流。
为此， 本发明提供了一种 FinFET器件的制作方法， 包括： 在衬底上形成沿第一方向延伸 的多个鰭片结构； 在每个鰭片结构沿第二方向的侧面形成多个突起； 在鰭片结构上形成沿第 二方向延伸的栅极堆叠结构； 在栅极堆叠结构两侧形成源漏区， 源漏区之间的鰭片结构构成 沟道区。
其中， 通过干法刻蚀和 /或湿法腐蚀处理鰭片结构侧面以形成多个突起。
其中， 控制刻蚀和 /或腐蚀的工艺参数使得多个突起的形状包括矩形、三角形、 梯形、 倒 梯形、 ∑形、 C形、 D形、 圆形、 椭圆形、 扇形、 菱形及其组合。
其中， 多个突起是周期性的、 和 /或连续的、 和 /或离散的。
其中，干法刻蚀包括具有横向刻蚀深度的各向同性的等离子体干法刻蚀或反应离子刻蚀， 或者各向同性干法刻蚀与各向异性干法刻蚀的组合方法。
其中， 湿法腐蚀包括利用不同晶向上选择腐蚀的湿法腐蚀方法。
其中， 形成突起之后进一步包括： 对鰭片侧壁进行表面处理、 圆化工艺。
本发明还提供了一种 FinFET器件， 包括： 多个鰭片结构， 在衬底上沿第一方向延伸； 多 个栅极堆叠， 沿第二方向延伸并且跨越了每个鰭片结构； 多个源漏区， 位于每个栅极堆叠沿 第二方向两侧； 多个沟道区， 由位于多个源漏区之间的鰭片结构构成； 其中， 每个鰭片结构 沿第二方向的侧壁具有多个突起。
其中， 多个突起的形状包括矩形、 三角形、 梯形、 倒梯形、 ∑形、 C形、 D形、 圆形、 椭 圆形、 扇形、 菱形及其组合。
其中， 多个突起是周期性的、 和 /或连续的、 和 /或离散的。
其中， 多个突起的高度 /厚度小于鰭片结构厚度 /宽度的 5 %。
依照本发明的 FinFET器件及其制作方法， 在鰭片侧面形成连续突起特别是弧线表面， 提 高了抑制短沟道效应的能力， 同时在同一平面投影面积下增大了沟道有效导电总截面面积， 从而提高了器件总体性能。 附图说明
以下参照附图来详细说明本发明的技术方案， 其中：
图 1至图 8为依照本发明的 FinFET制造方法各步骤的剖面示意图； 以及
图 9为依照本发明的 FinFET器件结构的立体示意图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果， 公开了充分增大导电沟道有效宽度从而提高驱动电流的 FinFET器件及其制造方法。 需要指出 的是， 类似的附图标记表示类似的结构， 本申请中所用的术语 "第一"、 "第二"、 "上"、 "下" 等等可用于修饰各种器件结构或制造工序。 这些修饰除非特别说明并非暗示所修饰器件结构 或制造工序的空间、 次序或层级关系。
图 9所示为依照本发明制造的 FinFET器件的立体示意图，包括衬底上沿第一方向延伸的 多个鰭片结构， 沿第二方向延伸并且跨越了每个鰭片结构的多个栅极堆叠， 沿第一方向延伸 的鰭片结构两侧的多个源漏区，位于多个源漏区之间的鰭片结构的一部分构成的多个沟道区， 其中鰭片结构沿第二方向的侧面具有连续的突起， 突起例如是弧线表面。 以下将先参照图 1 至图 8来描述制造方法的各个剖视图， 最后将回头进一步详细描述图 9的器件结构。
特别地， 以下某图的左部所示是沿图 9中垂直于沟道方向 （沿第二方向， 也即 X-X' 轴） 的剖视图， 某图的右部所示是沿图 9中平行于沟道方向 （沿第一方向， 也即 Y-Y' 方向） 的 剖视图。
参照图 1， 形成沿第一方向 （图 9中 X-X' 轴线）延伸的多个鰭片结构， 其中第一方向为 未来器件沟道区延伸方向。 提供衬底 1， 衬底 1依照器件用途需要而合理选择， 可包括单晶 体硅（Si )、 单晶体锗（Ge)、 应变硅（Strained Si )、 锗硅（SiGe)， 或是化合物半导体材料， 例如氮化镓 （GaN)、 砷化镓（GaAs)、 磷化铟（InP)、 锑化铟 （InSb)， 以及碳基半导体例如石 墨烯、 SiC、 碳纳管等等。 出于与 CMOS工艺兼容的考虑， 衬底 1优选地为体 Si。 光刻 /刻蚀 衬底 1， 在衬底 1中形成多个沿第一方向平行分布的沟槽 1G以及沟槽 1G之间剩余的衬底 1 材料所构成的鰭片 1F。沟槽 1G的深宽比优选地大于 5 : 1。优选地， 在多个鰭片结构的顶部沉 积硬掩模层 HM， 其材质可以是氧化硅、 氮化硅、 氮氧化硅及其组合， 并且优选地为氮化硅。
参照图 2， 刻蚀每个鰭片结构 1F， 在鰭片结构 IF沿垂直于第一方向的第二方向的侧面形成 连续的突起 1P。 优选地， 通过干法或者湿法刻蚀， 以 HM为掩模， 沿垂直于第一方向的第二方 向 （图 9中 Y-Y' 轴线） 侧向刻蚀每个鰭片结构 1F的侧面， 在 1F的侧面形成连续的向外 （从 1F 的中心垂直地朝向侧面表层）突起 1P， 也即突起 IP由多个相同或相似的突起 lPi连接形成， 多 个 lPi可以是周期性分布或者是离散分布。刻蚀 1F形成突起 1P的刻蚀工艺可以是各向同性的氟 基或氯基等离子体干法刻蚀， 或者 TMAH湿法腐蚀， 选择刻蚀温度等工艺参数以提高对于侧面 的刻蚀。 在本发明一个实施例中， 侧向刻蚀鰭片的步骤包括具有横向刻蚀深度的各向同性的 等离子体干法刻蚀， 或者各向同性刻蚀与各向异性刻蚀的组合方法。 此外， 侧向刻蚀鰭片的 步骤包括利用不同晶向上选择腐蚀的湿法腐蚀方法。优选地，刻蚀工艺是反应离子刻蚀（RIE)， 刻蚀气体包括氟基或氯基气体， 例如 NF3、 SF6、 CF4、 CH2F2、 CH3F、 CHF3、 Cl2等及其组合。 依照 刻蚀工艺参数不同， 可以控制突起 lPi的形状为矩形、 三角形、 梯形、 倒梯形、 ∑形 （多段折 线相连）、 C形 （超过 1/2曲面， 曲面可以是圆面、 椭圆面、 双曲面）、 D形 （1/2曲面， 曲面可 以是圆面、 椭圆面、 双曲面）、 圆形、 椭圆形、 扇形、 菱形以及其他多边形或曲面。 在本发明 一个优选实施例中， 突起 1P是由多个弧线段 lPi (包括半圆、 椭圆、 或具有其他角度的圆的一 部分） 连接构成的连续弧线表面 （连续弧线表面有助于提高鰭片沟道区电场分布均匀性， 提 高器件可靠性）。在本发明另一优选实施例中， 突起 1P是由周期性分布的三角形或梯形连接形 成的连续粗糙表面， 或者是平滑表面与粗糙表面周期性组合成的复合表面， 或者是不规则突 起构成的离散的突起表面， 也即突起 1P是周期性的、 连续的、 或者离散的。 多个突起 1P的高 度 /厚度小于鰭片结构 1F的厚度 /宽度的 5 %， 例如仅 l〜5nm。优选地， 突起 1P是由相同的子突 起 lPi连续构成， 以便获得均匀的沟道电学性能。
优选地， 形成了突起表面 1P之后， 采用表面处理、 圆化等工艺处理突起 1P以圆化， 获 得较为平滑的表面。 例如是采用表面氧化后再湿法微腐蚀的方法， 表面氧化工艺包括炉温氧 化或者强氧化剂溶液氧化等。表面处理、 圆化等工艺还可以选择氢气高温烘烤等。表面处理、 圆化等工艺还可选择各向同性腐蚀硅等。
参照图 3， 在鰭片 1F之间的沟槽 1G中通过 PECVD、 HDPCVD、 RT0 (快速热氧化） 等工艺 沉积填充材质例如为氧化硅、 氮氧化硅、 碳氧化硅、 low-k 等的绝缘隔离介质层， 从而构成 了浅沟槽隔离 （STI ) 2。 优选地， 随后采用 CMP、 回刻等工艺平坦化 STI 2直至暴露硬掩模 层 HM。
参照图 4， 回刻 STI2, 暴露鰭片 1F的大部分， 例如仅留下鰭片 1F的底部 （例如整个鰭 片 1F高度的 1/10〜1/5) 埋设在 STI 2内。 对于氧化硅材质的 STI2, 可以采用 HF基腐蚀液 湿法去除， 也可以采用氟基等离子体干法刻蚀， 向下刻蚀 STI2 以暴露出大部分鰭片 1F， 该 暴露的鰭片 1F将用作稍后器件的沟道区， 最底部将被刻蚀而作为器件的隔离区。优选地， 随 后通过湿法腐蚀去除硬掩模层 HM。
参照图 5，在多个鰭片 1F之间的再次暴露的沟槽 1G中，填充假栅极堆叠层。首先在 STI2 以及鰭片 1F上通过 LPCVD、 PECVD、 HDPCVD、 RT0、 化学氧化等方法沉积形成氧化硅材质的垫 氧化层 3， 用于保护鰭片 1F不在后续刻蚀过程中被过刻蚀。 在垫氧化层 3上通过 PECVD、 HDPCVD、 M0CVD、 MBE、 ALD、 蒸发、 溅射等沉积方法形成假栅极层 4， 材质可以是多晶硅、 非 晶硅、 微晶硅、 非晶碳、 多晶锗、 非晶锗等等及其组合。 以上各层的厚度不必按照图示的比 例， 而是根据具体的器件尺寸以及电学性能需求而合理设定。 假栅极堆叠 3/4环绕包围了鰭 片 1F顶部， 以及表面突起 1P的侧部。
参照图 6， 刻蚀假栅极堆叠层 3/4， 形成沿第二方向跨越鰭片 1F的假栅极堆叠结构。 例 如， 采用现有公知的图形化方法， 刻蚀假栅极堆叠 3/4直至暴露鰭片 1F的顶部， 去除鰭片 1F的第一方向两侧的部分层 3/4， 仅在鰭片 1F之上留下多个假栅极堆叠结构（图中仅显示一 个)。
参照图 7， 在鰭片 1F沿第一方向的两侧形成源漏区 1S/1D。在本发明一个优选实施例中， 刻蚀鰭片 1F， 直至暴露衬底 1， 通过 UHVCVD、 M0CVD、 ALD、 MBE、 常压外延等选择性外延形 成抬升的源漏区 1S和 1D， 其材质可以与衬底 1相同均为 Si ; 或者对于 PM0S而言， 源漏区可 以是 SiGe、 SiSn、 GeSn、 Si等及其组合， 从而向沟道区 1C施加压应力， 提高空穴迁移率； 而对于 NM0S而言， 源漏区可以是 Si : C、 Si : H、 SiGe : C、 Si等及其组合， 从而向沟道区 1C施 加张应力， 提高电子迁移率。 优选地， 在外延同时原位掺杂或者在外延之后注入掺杂并退火 激活， 使得源漏区 1S/D具有与衬底 1不同的掺杂类型、 浓度， 以控制器件的电学特性。 源漏 区 1S/D的顶部可以高于鰭片 1F的顶部。优选地， 可以在鰭片 1F沿第一方向的侧面形成侧墙 5， 并利用侧墙 5形成轻掺杂的源漏扩展区与重掺杂的源漏区 （均未分别示出）。
参照图 8， 采用后栅工艺， 完成后续制造。 在整个器件上形成层间介质层 （ILD) 6， 湿 法刻蚀去除假栅极堆叠 3/4， 在 ILD 6中留下栅极沟槽 （未示出）， 在栅极沟槽中依次沉积高 k材料的栅极绝缘层 7以及金属材料的栅极导电层 8， 构成栅极堆叠结构。 CMP平坦化栅极堆 叠结构直至暴露 ILD 6。 此后， 依照标准工艺， 在 ILD 6中刻蚀源漏接触孔 （未示出） 直达 源漏区 1S/D, 在源漏接触孔中沉积金属氮化物的阻挡层以及金属材料的导电层， 形成源漏接 触塞 （未示出）。
最后形成的器件结构的立体图如图 9所示， 包括： 衬底上沿第一方向延伸的多个鰭片结 构， 沿第二方向延伸并且跨越了每个鰭片结构的多个栅极堆叠， 沿第一方向延伸的鰭片结构 两侧的多个源漏区， 位于多个源漏区之间的鰭片结构构成多个沟道区， 其中鰭片结构沿第二 方向的侧面具有连续的突起， 突起包括矩形、三角形、梯形、倒梯形、 ∑形（多段折线相连）、 C形 （超过 1/2 曲面， 曲面可以是圆面、 椭圆面、 双曲面）、 D形 （1/2 曲面， 曲面可以是圆 面、 椭圆面、 双曲面）、 圆形、 椭圆形、 扇形、 菱形以及其他多边形或曲面， 突起可以是周期 性分布或者离散的。 上述这些结构的材料和几何形状已在方法描述中详述， 因此在此不再赘 述。
依照本发明的 FinFET器件及其制作方法， 在鰭片侧面形成连续突起特别是弧线表面， 提 高了抑制短沟道效应的能力， 同时在同一平面投影面积下增大了沟道有效导电总截面面积， 从而提高了器件总体性能。
尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人员可以知晓无需脱离本 发明范围而对器件结构做出各种合适的改变和等价方式。 此外， 由所公开的教导可做出许多 可能适于特定情形或材料的修改而不脱离本发明范围。 因此， 本发明的目的不在于限定在作 为用于实现本发明的最佳实施方式而公开的特定实施例， 而所公开的器件结构及其制造方法 将包括落入本发明范围内的所有实施例。

Claims

权 利 要 求
1、 一种 FinFET器件的制作方法， 包括：
在衬底上形成沿第一方向延伸的多个鰭片结构；
在每个鰭片结构沿第二方向的侧面形成多个突起；
在鰭片结构上形成沿第二方向延伸的栅极堆叠结构；
在栅极堆叠结构两侧形成源漏区， 源漏区之间的鰭片结构构成沟道区。
2、 如权利要求 1的方法， 其中， 通过干法刻蚀和 /或湿法腐蚀处理鰭片结构侧面以形成多 个突起。
3、 如权利要求 2的方法， 其中， 控制刻蚀和 /或腐蚀的工艺参数使得多个突起的形状包括 矩形、 三角形、 梯形、 倒梯形、 ∑形、 C形、 D形、 圆形、 椭圆形、 扇形、 菱形及其组合。
4、 如权利要求 1的方法， 其中， 多个突起是周期性的、 和 /或连续的、 和 /或离散的。
5、 如权利要求 2的方法， 其中， 干法刻蚀包括具有横向刻蚀深度的各向同性的等离子体 干法刻蚀或反应离子刻蚀， 或者各向同性干法刻蚀与各向异性干法刻蚀的组合方法。
6、 如权利要求 2的方法， 其中， 湿法腐蚀包括利用不同晶向上选择腐蚀的湿法腐蚀方法。
7、 如权利要求 1的方法， 其中， 形成突起之后进一步包括： 对鰭片侧壁进行表面处理、 圆化工艺。
8、 一种 FinFET器件， 包括：
多个鰭片结构， 在衬底上沿第一方向延伸；
多个栅极堆叠， 沿第二方向延伸并且跨越了每个鰭片结构；
多个源漏区， 位于每个栅极堆叠沿第二方向两侧；
多个沟道区， 由位于多个源漏区之间的鰭片结构构成；
其中， 每个鰭片结构沿第二方向的侧壁具有多个突起。
9、 如权利要求 8所述的 FinFET器件， 其中， 多个突起的形状包括矩形、 三角形、 梯形、 倒梯形、 ∑形、 C形、 D形、 圆形、 椭圆形、 扇形、 菱形及其组合。
10、 如权利要求 8所述的 FinFET器件， 其中， 多个突起是周期性的、 和 /或连续的、 和 / 或离散的。
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