CN107154429B - 鳍状场效应晶体管及其制备方法 - Google Patents
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Abstract
本发明提供一种鳍状场效应晶体管及其制备方法，其中，鳍状场效应晶体管由两道选择性蚀刻程序形成沟道，鳍状场效应晶体管包括衬底、浅沟槽隔离(STI)层、缓冲层、III‑V族材料、高介电常数介电层及导电材料。STI层形成于该衬底上，该STI层具有沟槽，缓冲层形成于该沟槽中的该衬底上，III‑V族材料形成于该缓冲层上，且该III‑V族材料具有多个垂直堆栈碗形的截面形状，高介电常数介电层形成于该STI层的上表面和该III‑V族材料周围，导电材料形成于该高介电常数介电层的周围，以作为栅极。
Description
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种鳍状场效应晶体管及其制备方法。
背景技术
III-V族半导体材料，例如砷化镓(GaAs)及砷化铟(InAs)具有较高的电子迁移率，因此用以传导较高的驱动电流。III-V族金属氧化半导体场效应晶体管(III-V MOSFET)的效能已证实具有显著的提升，并达到低栅极漏电流、高沟道迁移率及高驱动电流。于是，制造具有III-V族材料的高效能MOSFETs是可行的。
互补式金氧半导体(CMOS)的微小化衍生出许多物理上的限制以及问题，因此三维的鳍状场效应晶体管(FinFET)器件结构为一种具前景的替代，使晶体管的尺寸缩小化超越10纳米的技术节点。FinFET结构可优越地控制短沟道效应，然而，III-V FinFET的驱动电流仍须改善。
发明内容
本发明的目的在于，提供一种鳍状场效应晶体管及其制备方法。
为解决上述技术问题，本发明一种鳍状场效应晶体管的制备方法，包括：提供衬底；沉积浅沟槽隔离(STI)层于该衬底上；沉积多个含氧介电层和多个绝缘层的交替层于该STI层上；经由第一道蚀刻程序形成沟槽，该沟槽连通于该STI层和该些含氧介电层和该些绝缘层的该交替层；经由第二道蚀刻程序选择性蚀刻该沟槽的内侧壁的该交替层中的该些绝缘层，使该沟槽的该内侧壁具有多个垂直堆栈碗形的截面形状；选择性外延生长缓冲层于该沟槽中的该衬底上；选择性外延生长III-V族材料于该沟槽中的该缓冲层上；选择性移除该些含氧介电层和该些绝缘层的该交替层；沉积高介电常数介电层于该STI层的上表面和该III-V族材料的周围；及沉积导电材料于该高介电常数介电层的周围，以形成栅极。
根据一实施例，沉积该浅沟槽隔离(STI)层于该衬底上的步骤包括：该STI层的厚度介于10至100纳米之间。
根据一实施例，沉积该些含氧介电层和该些绝缘层的该交替层于该STI层的步骤包括：该些含氧介电层的材料为二氧化硅(SiO2)、氟氧化硅(SiOF)、氮氧化硅(SiON)、或其组合。
根据一实施例，沉积该些含氧介电层和该些绝缘层的该交替层于该STI层的步骤包括：该些含氧介电层的厚度分别为介于2至10纳米之间。
根据一实施例，沉积该些含氧介电层和该些绝缘层的该交替层于该STI层的步骤包括：该些绝缘层的材料为磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼磷硅酸盐玻璃(BPSG)、或其组合。
根据一实施例，沉积该些含氧介电层和该些绝缘层的该交替层于该STI层的步骤包括：该些绝缘层的厚度分别为介于5至10纳米之间。
根据一实施例，选择性外延生长该缓冲层于该沟槽中的该衬底上的步骤包括：该缓冲层的材料为砷化镓(GaAs)或硅锗(SiGe)。
根据一实施例，选择性外延生长该缓冲层于该沟槽中的该衬底上的步骤包括：该缓冲层的厚度介于10至100纳米之间。
根据一实施例，选择性外延生长该III-V族材料于该沟槽中的该缓冲层上的步骤包括：该III-V族材料为砷化铟镓(InGaAs)、砷化铟(InAs)或锑化铟(InSb)。
根据一实施例，经由该第一道蚀刻程序形成该沟槽的步骤包括：该第一道蚀刻程序为采用干式蚀刻法。
根据一实施例，经由该第二道蚀刻程序选择性蚀刻该沟槽的内侧壁的该交替层中的该些绝缘层的步骤包括：该第二道蚀刻程序为采用湿式蚀刻法。
相应的，本发明还提供一种鳍状场效应晶体管，该鳍状场效应晶体管包括：衬底；浅沟槽隔离(STI)层，形成于该衬底上，该STI层具有沟槽；缓冲层，形成于该沟槽中的该衬底上；III-V族材料，形成于该缓冲层上，且该III-V族材料具有多个垂直堆栈碗形的截面形状；高介电常数介电层，形成于该STI层的上表面和该III-V族材料周围；及导电材料，形成于该高介电常数介电层的周围，以作为栅极。
本发明提供的鳍状场效应晶体管，采用两次选择性蚀刻与两次选择性外延生长以形成多个垂直堆栈碗形的III-V族鳍状结构，不仅可简化制程，亦可以实现具高迁移率的沟道。
附图说明
图1为本发明一实施例中制备鳍状场效应晶体管的方法流程图；
图2为本发明一实施例中STI层与交错层形成于衬底上的剖面结构示意图；
图3为本发明一实施例中于连通于STI层和多个含氧介电层和多个绝缘层的交替层的沟槽的剖面结构示意图；
图4为本发明一实施例中具有多个垂直堆栈碗形的截面形状的沟槽的剖面结构示意图；
图5为本发明一实施例中缓冲层形成于沟槽中的衬底上的剖面结构示意图；
图6为本发明一实施例中III-V族材料形成于沟槽中的缓冲层上的剖面结构示意图；
图7为本发明一实施例中选择性移除多个含氧介电层和多个绝缘层的交替层的剖面结构示意图；
图8为本发明一实施例中沉积高介电常数介电层于STI层的上表面和III-V族材料的周围的剖面结构示意图；
图9为本发明一实施例中沉积导电材料于高介电常数介电层的周围的剖面结构示意图。
具体实施方式
下面将结合示意图对本发明的鳍状场效应晶体管及其制备方法进行更详细的描述，其中表示了本发明的较佳实施例，应该理解本领域技术人员可以修改在此描述的本发明，而仍然实现本发明的有利效果。因此，下列描述应当被理解为对于本领域技术人员的广泛知道，而并不作为对本发明的限制。
下文结合附图对本发明的鳍状场效应晶体管及其制备方法，图1为制备鳍状场效应晶体管的方法流程图，图2～图9为各步骤中的结构示意图，其制备过程包括如下步骤：
执行步骤S1，参考图2所示，提供一衬底100。根据一实施例，衬底100为单晶硅衬底。
执行步骤S2，再次参考图2所示，沉积浅沟槽隔离(STI)层120于衬底100上。根据一实施例，STI层120为二氧化硅。根据一实施例，STI层120的厚度介于10至100纳米之间。
执行步骤S3，再次参考图2所示，沉积多个含氧介电层130和多个绝缘层140的交替层150于STI层120上。根据一实施例，含氧介电层130的材料为二氧化硅(SiO2)、氟氧化硅(SiOF)、氮氧化硅(SiON)、或其组合。根据一实施例，每一层含氧介电层130的厚度为介于2至10纳米之间。根据一实施例，绝缘层140的材料为磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼磷硅酸盐玻璃(BPSG)、或其组合。根据一实施例，每一层绝缘层140的厚度为介于5至10纳米之间。根据一实施例，步骤S2与S3分别采用化学气相沉积(CVD)、金属有机物化学气相沉积(MOCVD)、分子束外延(MBE)或原子层沉积(ALD)等方式沉积STI层120、含氧介电层130与绝缘层140。
执行步骤S4，参考图3所示，经由第一道蚀刻程序形成一沟槽210，沟槽210连通于STI层120和多个含氧介电层130和多个绝缘层140的交替层150。根据一实施例，第一道蚀刻程序为采用干式蚀刻法，且采用的气体为Cl2和Ar的混合气体，然不以此为限。
执行步骤S5，参考图4所示，经由第二道蚀刻程序选择性蚀刻沟槽210的内侧壁220的交替层150中的多个绝缘层140，使沟槽210的内侧壁220具有多个垂直堆栈碗形的截面形状。根据一实施例，第二道蚀刻程序为采用湿式蚀刻法，且使用的溶液为NH3和H2O的混合溶液、KOH溶液或者是TMAH溶液(羟化四甲铵，tetramethylazanium hydroxide)。
执行步骤S6，参考图5所示，选择性外延生长缓冲层300于沟槽210中的衬底100上。根据一实施例，缓冲层300的材料为砷化镓(GaAs)或硅锗(SiGe)。根据一实施例，缓冲层300的厚度大致与STI层120的厚度相同，也就是介于10至100纳米之间。
执行步骤S7，参考图6所示，选择性外延生长III-V族材料400于沟槽210中的缓冲层300上。根据一实施例，III-V族材料400填满缓冲层300上的沟槽210。根据一实施例，III-V族材料400为砷化铟镓(InGaAs)、砷化铟(InAs)或锑化铟(InSb)。
执行步骤S8，参考图7所示，选择性移除多个含氧介电层130和多个绝缘层140的交替层150，使III-V族材料400暴露于STI层120上。
执行步骤S9，参考图8所示，沉积高介电常数(high-K)介电层500于STI层120的上表面和III-V族材料400的周围。根据一实施例，高介电常数介电层500之介电材料，例如TiO2、HfO2、ZrO2等等。
执行步骤S10，参考图9所示，沉积导电材料600于高介电常数介电层500的周围，以形成栅极。根据一实施例，采用微影与蚀刻技术以图案化定义栅极。根据一实施例，步骤S9与S10分别采用化学气相沉积(CVD)、金属有机物化学气相沉积(MOCVD)、分子束外延(MBE)或原子层沉积(ALD)等方式沉积高介电常数介电层500与导电材料600。根据一实施例，执行步骤S10之后，外延生长或植入源极/漏极材料于衬底100上，以作为鳍状场效应晶体管的源极/漏极。
再次参考图9，藉由上述方法步骤，本发明提供一种鳍状场效应晶体管1，包括衬底100、浅沟槽隔离(STI)层120、缓冲层300、III-V族材料400、高介电常数介电层500及导电材料600。STI层120形成于衬底100上，STI层120具有沟槽210′。缓冲层300形成于沟槽210′中的衬底100上。III-V族材料400形成于缓冲层300上，且III-V族材料400具有多个垂直堆栈碗形的截面形状。高介电常数介电层500形成于STI层120的上表面和III-V族材料400的周围。导电材料600形成于高介电常数介电层500的周围，以作为栅极。此外，源极/漏极材料可藉由外延生长或植入于衬底100上，以作为鳍状场效应晶体管1的源极/漏极。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明申请专利范围及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。
Claims (11)
1.一种鳍状场效应晶体管的制备方法，其特征在于，包括：
提供衬底；
沉积浅沟槽隔离层于该衬底上；
沉积多个含氧介电层和多个绝缘层的交替层于该浅沟槽隔离层上；
经由第一道蚀刻程序形成沟槽，该沟槽贯穿该浅沟槽隔离层和该些含氧介电层和该些绝缘层的该交替层；
经由第二道蚀刻程序选择性蚀刻该沟槽的内侧壁的该交替层中的该些绝缘层，使该沟槽的该内侧壁具有多个垂直堆栈碗形的截面形状；
选择性外延生长缓冲层于该沟槽中的该衬底上；
选择性外延生长III-V族材料于该沟槽中的该缓冲层上；
选择性移除该些含氧介电层和该些绝缘层的该交替层；
沉积高介电常数介电层于该浅沟槽隔离层的上表面和该III-V族材料的周围；及
沉积导电材料于该高介电常数介电层的周围，以形成栅极。
2.如权利要求1所述的鳍状场效应晶体管的制备方法，其特征在于，沉积该浅沟槽隔离层于该衬底上的步骤包括：该浅沟槽隔离层的厚度介于10至100纳米之间。
3.如权利要求1所述的鳍状场效应晶体管的制备方法，其特征在于，沉积该些含氧介电层和该些绝缘层的该交替层于该浅沟槽隔离层的步骤包括：该些含氧介电层的材料为二氧化硅、氟氧化硅、氮氧化硅、或其组合。
4.如权利要求1所述的鳍状场效应晶体管的制备方法，其特征在于，沉积该些含氧介电层和该些绝缘层的该交替层于该浅沟槽隔离层的步骤包括：该些含氧介电层的厚度分别介于2至10纳米之间。
5.如权利要求1所述的鳍状场效应晶体管的制备方法，其特征在于，沉积该些含氧介电层和该些绝缘层的该交替层于该浅沟槽隔离层的步骤包括：该些绝缘层的材料为磷硅酸盐玻璃、硼硅酸盐玻璃、硼磷硅酸盐玻璃、或其组合。
6.如权利要求1所述的鳍状场效应晶体管的制备方法，其特征在于，沉积该些含氧介电层和该些绝缘层的该交替层于该浅沟槽隔离层的步骤包括：该些绝缘层的厚度分别介于5至10纳米之间。
7.如权利要求1所述的鳍状场效应晶体管的制备方法，其特征在于，选择性外延生长该缓冲层于该沟槽中的该衬底上的步骤包括：该缓冲层的材料为砷化镓或硅锗。
8.如权利要求1所述的鳍状场效应晶体管的制备方法，其特征在于，选择性外延生长该缓冲层于该沟槽中的该衬底上的步骤包括：该缓冲层的厚度介于10至100纳米之间。
9.如权利要求1所述的鳍状场效应晶体管的制备方法，其特征在于，选择性外延生长该III-V族材料于该沟槽中的该缓冲层上的步骤包括：该III-V族材料为砷化铟镓、砷化铟或锑化铟。
10.如权利要求1所述的鳍状场效应晶体管的制备方法，其特征在于，经由该第一道蚀刻程序形成该沟槽的步骤包括：该第一道蚀刻程序采用干式蚀刻法。
11.如权利要求1所述的鳍状场效应晶体管的制备方法，其特征在于，经由该第二道蚀刻程序选择性蚀刻该沟槽的内侧壁的该交替层中的该些绝缘层的步骤包括：该第二道蚀刻程序采用湿式蚀刻法。
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| CN104282561A (zh) * | 2013-07-02 | 2015-01-14 | 中国科学院微电子研究所 | FinFET器件及其制作方法 |
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