TWI602265B - 鰭狀場效電晶體及其製備方法 - Google Patents
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
- H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Description
本發明涉及半導體製造技術領域，尤其涉及一種鰭狀場效電晶體及其製備方法。
III-V族半導體材料，例如砷化鎵(GaAs)及砷化銦(InAs)具有較高的電子遷移率，因此用以傳導較高的驅動電流。III-V族金屬氧化半導體場效電晶體(III-V MOSFET)的效能已證實具有顯著的提升，並達到低閘極漏電流、高通道遷移率及高驅動電流。於是，製造具有III-V族材料的高效能MOSFETs是可行的。
互補式金氧半導體(CMOS)的微小化衍生出許多物理上的限制以及問題，因此三維的鰭狀場效電晶體(FinFET)元件結構為一種具前景的替代，使電晶體的尺寸縮小化超越10奈米的技術節點。FinFET結構可優越地控制短通道效應，然而，III-V FinFET的驅動電流仍須改善。
本發明的目的在於，提供一種鰭狀場效電晶體及
其製備方法。
為解決上述技術問題，本發明一種鰭狀場效電晶體的製備方法，包括：提供基底；沈積淺溝槽隔離(STI)層於該基底上；沈積複數個含氧介電層和複數個絕緣層的交替層於該STI層上；經由第一道蝕刻程序形成溝槽，該溝槽連通於該STI層和該些含氧介電層和該些絕緣層的該交替層；經由第二道蝕刻程序選擇性蝕刻該溝槽的內側壁的該交替層中的該些絕緣層，使該溝槽的該內側壁具有複數個垂直堆疊碗形的截面形狀；選擇性磊晶成長緩衝層於該溝槽中的該基底上；選擇性磊晶成長III-V族材料於該溝槽中的該緩衝層上；選擇性移除該些含氧介電層和該些絕緣層的該交替層；沈積高介電常數介電層於該STI層的上表面和該III-V族材料的周圍；及沈積導電材料於該高介電常數介電層的周圍，以形成閘極。
根據一實施例，沈積該淺溝槽隔離(STI)層於該基底上的步驟包括：該STI層的厚度介於10至100奈米之間。
根據一實施例，沈積該些含氧介電層和該些絕緣層的該交替層於該STI層的步驟包括：該些含氧介電層的材料為二氧化矽(SiO2)、氟氧化矽(SiOF)、氮氧化矽(SiON)、或該等之組合。
根據一實施例，沈積該些含氧介電層和該些絕緣層的該交替層於該STI層的步驟包括：該些含氧介電層的厚度
分別為介於2至10奈米之間。
根據一實施例，沈積該些含氧介電層和該些絕緣層的該交替層於該STI層的步驟包括：該些絕緣層的材料為磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼磷矽酸鹽玻璃(BPSG)、或該等之組合。
根據一實施例，沈積該些含氧介電層和該些絕緣層的該交替層於該STI層的步驟包括：該些絕緣層的厚度分別為介於5至10奈米之間。
根據一實施例，選擇性磊晶成長該緩衝層於該溝槽中的該基底上的步驟包括：該緩衝層的材料為砷化鎵(GaAs)或矽鍺(SiGe)。
根據一實施例，選擇性磊晶成長該緩衝層於該溝槽中的該基底上的步驟包括：該緩衝層的厚度介於10至100奈米之間。
根據一實施例，選擇性磊晶成長該III-V族材料於該溝槽中的該緩衝層上的步驟包括：該III-V族材料為砷化銦鎵(InGaAs)、砷化銦(InAs)或銻化銦(InSb)。
根據一實施例，經由該第一道蝕刻程序形成該溝槽的步驟包括：該第一道蝕刻程序為採用乾式蝕刻法。
根據一實施例，經由該第二道蝕刻程序選擇性蝕刻該溝槽的內側壁的該交替層中的該些絕緣層的步驟包括：該第二道蝕刻程序為採用濕式蝕刻法。
相應的，本發明還提供一種鰭狀場效電晶體，該鰭狀場效電晶體包括：基底；淺溝槽隔離(STI)層，形成於該基底上，該STI層具有溝槽；緩衝層，形成於該溝槽中的該基底上；III-V族材料，形成於該緩衝層上，且該III-V族材料具有複數個垂直堆疊碗形的截面形狀；高介電常數介電層，形成於該STI層的上表面和該III-V族材料周圍；及導電材料，形成於該高介電常數介電層的周圍，以作為閘極。
本發明提供的鰭狀場效電晶體，採用兩次選擇性蝕刻與兩次選擇性磊晶成長以形成複數個垂直堆疊碗形的III-V族鰭狀結構，不僅可簡化製程，亦可以實現具高遷移率的通道。
S1~S‧‧‧鰭狀場效電晶體的製備方法流程步驟
1‧‧‧鰭狀場效電晶體
100‧‧‧基底
120‧‧‧淺溝槽隔離(STI)層
130‧‧‧NMOS主動區域
130‧‧‧含氧介電層
140‧‧‧絕緣層
150‧‧‧交錯層
210、210'‧‧‧溝槽
220‧‧‧內側壁
300‧‧‧緩衝層
400‧‧‧III-V族材料
500‧‧‧高介電常數介電層
600‧‧‧導電材料
第1圖為本發明一實施例中製備鰭狀場效電晶體的方法流程圖；第2圖為本發明一實施例中STI層與交錯層形成於基底上的剖面結構示意圖；第3圖為本發明一實施例中於連通於STI層和複數個含氧介電層和複數個絕緣層的交替層的溝槽的剖面結構示意圖；第4圖為本發明一實施例中具有複數個垂直堆疊碗形的截面形狀的溝槽的剖面結構示意圖；第5圖為本發明一實施例中緩衝層形成於溝槽中的基底
上的剖面結構示意圖；第6圖為本發明一實施例中III-V族材料形成於溝槽中的緩衝層上的剖面結構示意圖；第7圖為本發明一實施例中選擇性移除複數個含氧介電層和複數個絕緣層的交替層的剖面結構示意圖；第8圖為本發明一實施例中沈積高介電常數介電層於STI層的上表面和III-V族材料的周圍的剖面結構示意圖；第9圖為本發明一實施例中沈積導電材料於高介電常數介電層的周圍的剖面結構示意圖。
下面將結合示意圖對本發明的鰭狀場效電晶體及其製備方法進行更詳細的描述，其中表示了本發明的較佳實施例，應該理解本領域技術人員可以修改在此描述的本發明，而仍然實現本發明的有利效果。因此，下列描述應當被理解為對於本領域技術人員的廣泛知道，而並不作為對本發明的限制。
下文結合附圖對本發明的鰭狀場效電晶體及其製備方法，第1圖為製備鰭狀場效電晶體的方法流程圖，第2圖~第9圖為各步驟中的結構示意圖，其製備過程包括如下步驟：
執行步驟S1，參考第2圖所示，提供一基底100。
根據一實施例，基底100為單晶矽基底。
執行步驟S2，再次參考第2圖所示，沈積淺溝槽隔離(STI)層120於基底100上。根據一實施例，STI層120為二氧化矽。根據一實施例，STI層120的厚度介於10至100奈米之間。
執行步驟S3，再次參考第2圖所示，沈積複數個含氧介電層130和複數個絕緣層140的交替層150於STI層120上。根據一實施例，含氧介電層130的材料為二氧化矽(SiO2)、氟氧化矽(SiOF)、氮氧化矽(SiON)、或該等之組合。根據一實施例，每一層含氧介電層130的厚度為介於2至10奈米之間。根據一實施例，絕緣層140的材料為磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼磷矽酸鹽玻璃(BPSG)、或該等之組合。根據一實施例，每一層絕緣層140的厚度為介於5至10奈米之間。根據一實施例，步驟S2與S3分別採用化學氣相沈積(CVD)、金屬有機物化學氣相沉積(MOCVD)、分子束磊晶(MBE)或原子層沈積(ALD)等方式沈積STI層120、含氧介電層130與絕緣層140。
執行步驟S4，參考第3圖所示，經由第一道蝕刻程序形成一溝槽210，溝槽210連通於STI層120和多個含氧介電層130和多個絕緣層140的交替層150。根據一實施例，第一道蝕刻程序為採用乾式蝕刻法，且採用的氣體為Cl2和Ar的混合氣體，然不以此為限。
執行步驟S5，參考第4圖所示，經由第二道蝕刻程序選擇性蝕刻溝槽210的內側壁220的交替層150中的多個絕緣層140，使溝槽210的內側壁220具有複數個垂直堆疊碗形的截面形狀。根據一實施例，第二道蝕刻程序為採用濕式蝕刻法，且使用的溶液為NH3和H2O的混合溶液、KOH溶液或者是TMAH溶液(羥化四甲銨，tetramethylazanium hydroxide)。
執行步驟S6，參考第5圖所示，選擇性磊晶成長緩衝層300於溝槽210中的基底100上。根據一實施例，緩衝層300的材料為砷化鎵(GaAs)或矽鍺(SiGe)。根據一實施例，緩衝層300的厚度大致與STI層120的厚度相同，也就是介於10至100奈米之間。
執行步驟S7，參考第6圖所示，選擇性磊晶成長III-V族材料400於溝槽210中的緩衝層300上。根據一實施例，III-V族材料400填滿緩衝層300上的溝槽210。根據一實施例，III-V族材料400為砷化銦鎵(InGaAs)、砷化銦(InAs)或銻化銦(InSb)。
執行步驟S8，參考第7圖所示，選擇性移除多個含氧介電層130和多個絕緣層140的交替層150，使III-V族材料400暴露於STI層120上。
執行步驟S9，參考第8圖所示，沈積高介電常數(high-K)介電層500於STI層120的上表面和III-V族材料400的周圍。根據一實施例，高介電常數介電層500之介電材料，例
如TiO2、HfO2、ZrO2等等。
執行步驟S10，參考第9圖所示，沈積導電材料600於高介電常數介電層500的周圍，以形成閘極。根據一實施例，採用微影與蝕刻技術以圖案化定義閘極。根據一實施例，步驟S9與S10分別採用化學氣相沈積(CVD)、金屬有機物化學氣相沉積(MOCVD)、分子束磊晶(MBE)或原子層沈積(ALD)等方式沈積高介電常數介電層500與導電材料600。根據一實施例，執行步驟S10之後，磊晶成長或植入源極/汲極材料於基底100上，以作為鰭狀場效電晶體的源極/汲極。
再次參考第9圖，藉由上述方法步驟，本發明提供一種鰭狀場效電晶體1，包括基底100、淺溝槽隔離(STI)層120、緩衝層300、III-V族材料400、高介電常數介電層500及導電材料600。STI層120形成於基底100上，STI層120具有溝槽210'。緩衝層300形成於溝槽210'中的基底100上。III-V族材料400形成於緩衝層300上，且III-V族材料400具有複數個垂直堆疊碗形的截面形狀。高介電常數介電層500形成於STI層120的上表面和III-V族材料400的周圍。導電材料600形成於高介電常數介電層500的周圍，以作為閘極。此外，源極/汲極材料可藉由磊晶成長或植入於基底100上，以作為鰭狀場效電晶體1的源極/汲極。
顯然，本領域的技術人員可以對本發明進行各種改動和變型而不脫離本發明的精神和範圍。這樣，倘若本發
明的這些修改和變型屬於本發明申請專利範圍及其等同技術的範圍之內，則本發明也意圖包含這些改動和變型在內。
S1~S10‧‧‧鰭狀場效電晶體製備方法流程步驟
Claims (11)
- 一種鰭狀場效電晶體的製備方法，包括：提供基底；沈積淺溝槽隔離(STI)層於該基底上；沈積複數個含氧介電層和複數個絕緣層的交替層於該STI層上；經由第一道蝕刻程序形成溝槽，該溝槽連通於該STI層和該些含氧介電層和該些絕緣層的該交替層；經由第二道蝕刻程序選擇性蝕刻該溝槽的內側壁的該交替層中的該些絕緣層，使該溝槽的該內側壁具有複數個垂直堆疊碗形的截面形狀；選擇性磊晶成長緩衝層於該溝槽中的該基底上；選擇性磊晶成長III-V族材料於該溝槽中的該緩衝層上；選擇性移除該些含氧介電層和該些絕緣層的該交替層；沈積高介電常數介電層於該STI層的上表面和該III-V族材料的周圍；及沈積導電材料於該高介電常數介電層的周圍，以形成閘極。
- 如申請專利範圍第1項所述的製備方法，其中，沈積該淺溝槽隔離(STI)層於該基底上的步驟包括：該STI層的厚度介於10至100奈米之間。
- 如申請專利範圍第1項所述的製備方法，其中，沈積該些含氧介電層和該些絕緣層的該交替層於該STI層的步驟包括：該些含氧介電層的材料為二氧化矽(SiO2)、氟氧化矽(SiOF)、氮氧化矽(SiON)、或該等之組合。
- 如申請專利範圍第1項所述的製備方法，其中，沈積該些含氧介電層和該些絕緣層的該交替層於該STI層的步驟包括：該些含氧介電層的厚度分別為介於2至10奈米之間。
- 如申請專利範圍第1項所述的製備方法，其中，沈積該些含氧介電層和該些絕緣層的該交替層於該STI層的步驟包括：該些絕緣層的材料為磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼磷矽酸鹽玻璃(BPSG)、或該等之組合。
- 如申請專利範圍第1項所述的製備方法，其中，沈積該些含氧介電層和該些絕緣層的該交替層於該STI層的步驟包括：該些絕緣層的厚度分別為介於5至10奈米之間。
- 如申請專利範圍第1項所述的製備方法，其中，選擇性磊晶成長該緩衝層於該溝槽中的該基底上的步驟包括：該緩衝層的材料為砷化鎵(GaAs)或矽鍺(SiGe)。
- 如申請專利範圍第1項所述的製備方法，其中，選擇性磊晶成長該緩衝層於該溝槽中的該基底上的步驟包括：該緩衝層的厚度介於10至100奈米之間。
- 如申請專利範圍第1項所述的製備方法，其中，選擇性磊晶成長該III-V族材料於該溝槽中的該緩衝層上的步驟包括：該III-V族材料為砷化銦鎵(InGaAs)、砷化銦(InAs)或銻化銦(InSb)。
- 如申請專利範圍第1項所述的製備方法，其中，經由該第一道蝕刻程序形成該溝槽的步驟包括：該第一道蝕刻程序為採用乾式蝕刻法。
- 如申請專利範圍第1項所述的製備方法，其中，經由該第二道蝕刻程序選擇性蝕刻該溝槽的內側壁的該交替層中的該些絕緣層的步驟包括：該第二道蝕刻程序為採用濕式蝕刻法。
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