WO2014110851A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2014110851A1
WO2014110851A1 PCT/CN2013/071634 CN2013071634W WO2014110851A1 WO 2014110851 A1 WO2014110851 A1 WO 2014110851A1 CN 2013071634 W CN2013071634 W CN 2013071634W WO 2014110851 A1 WO2014110851 A1 WO 2014110851A1
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Prior art keywords
substrate
layer
fin
forming
gate
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PCT/CN2013/071634
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English (en)
French (fr)
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朱慧珑
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中国科学院微电子研究所
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Publication of WO2014110851A1 publication Critical patent/WO2014110851A1/zh
Priority to US14/797,762 priority Critical patent/US9502560B2/en

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Definitions

  • the present disclosure relates to the field of semiconductors, and more particularly to a semiconductor device and a method of fabricating the same. Background technique
  • a three-dimensional semiconductor device such as a FinFET (Fin Field Effect Transistor) has been proposed.
  • a FinFET Fin Field Effect Transistor
  • a FinFET includes a fin that is vertically formed on a substrate and a gate stack that intersects the fin. Additionally, an isolation layer is formed over the substrate to isolate the gate stack from the substrate. Therefore, the bottom of the fin is surrounded by the isolation layer, so that it is difficult to effectively control the bottom of the fin. As a result, leakage current between the source and the drain via the bottom of the fin is apt to occur.
  • a punch-through barrier can be used to reduce this leakage current.
  • PTS punch-through barrier
  • a method of fabricating a semiconductor device comprising: forming a well region in a substrate, the well region including a first portion and a second portion, the first portion being compared to a second portion doping concentration Lower, and closer to the surface of the substrate; forming a fin structure on the surface of the substrate; forming an isolation layer on the surface of the substrate, the isolation layer exposing a portion of the fin structure, and the exposed portion of the fin structure is used as the a fin of the semiconductor device; forming a sacrificial gate conductor layer on the isolation layer, the gate conductor layer intersecting the fin structure via the sacrificial gate dielectric layer; forming a gate spacer on the sidewall of the sacrificial gate conductor layer; forming on the isolation layer a dielectric layer, and planarizing the dielectric layer to expose the sacrificial gate conductor layer; selectively removing the sacrificial gate conductor layer to form a gate trench inside the gate spacer;
  • a semiconductor device comprising: a substrate having a well region formed therein, the well region including a first portion and a second portion, the first portion being doped compared to the second portion a lower concentration, and closer to the surface of the substrate; a fin structure formed on the surface of the substrate; an isolation layer formed on the surface of the substrate, the isolation layer exposing a portion of the fin structure, and exposing the fin structure Partially used as a fin of the semiconductor device; and a gate stack formed on the isolation layer that intersects the fin, wherein a via barrier is formed only in a region below a portion where the fin intersects the gate stack.
  • the formed PTS is self-aligned below the channel region, so that leakage current between the source and the drain can be effectively reduced. In addition, this is not formed under the source and drain regions.
  • junction capacitance between the source/drain and the well region can be further reduced due to the presence of the first portion of the well region having a relatively low doping concentration.
  • FIGS. 1-14 are schematic diagrams showing a flow of fabricating a semiconductor device in accordance with an embodiment of the present disclosure. detailed description
  • a layer/element when referred to as being "on" another layer/element, the layer/element may be located directly on the other layer/element, or a central layer may be present between them. element. In addition, if one layer/element is "on” another layer/element, then when turning the orientation, This layer/element may be located "under” the other layer/element.
  • a semiconductor device can include a substrate, a fin structure formed on the substrate, and a gate stack that intersects the fin structure.
  • the gate stack can be isolated from the substrate by an isolation layer.
  • the isolation layer may expose a portion of the fin structure, and the exposed portion of the fin structure may serve as a true fin of the semiconductor device.
  • the semiconductor device can also include a well region buried in the substrate.
  • the well region may include a first portion and a second portion, the first portion being lower in doping concentration than the second portion, and closer to the substrate surface.
  • the source/drain regions can be connected to the well region through the first portion having a lower doping concentration.
  • the semiconductor device may include a punch-through barrier formed only under the channel region
  • PTS PTS
  • PTS PTS
  • Such PTS can be formed, for example, by the self-aligned techniques described herein.
  • such a self-alignment technique can be implemented by combining a replacement gate technique.
  • a PTS can be formed by ion implantation through a replacement gate trench (or hole) formed in accordance with a replacement gate technique.
  • the formed PTS is located below the replacement gate trench in which the true gate stack is subsequently formed, and thus is self-aligned below the channel region (in the device including the fin, the region or region where the fin intersects the gate stack) .
  • the fin structure can be formed on the substrate (eg, by patterning the substrate).
  • the sacrificial gate stack can then be formed according to the replacement gate technique.
  • an isolation layer can be formed over the substrate, the isolation layer surrounding the bottom of the fin structure and exposing the remainder of the fin structure (the exposed portion of the fin structure serving as the true fin of the final device).
  • a sacrificial gate stack is formed on the isolation layer.
  • the sacrificial gate stack can include, for example, a sacrificial gate dielectric layer and a sacrificial gate conductor layer.
  • a gate spacer is formed on the sidewall of the sacrificial gate stack.
  • a dielectric layer is formed on the isolation layer and planarized, for example, chemical mechanical polishing
  • CMP CMP to expose the sacrificial gate stack. Thereafter, the sacrificial gate conductor layer can be selectively removed to form a gate trench (or hole) inside the gate spacer.
  • the PTS can be formed via the gate trench (or hole), for example by ion implantation. Due to the presence of the dielectric layer, ions are only substantially implanted into the area below the gate trench (or hole).
  • the isolation layer may be formed by depositing a dielectric material on the substrate and then etching back. Before etch back, it can be sputtered, such as Ar or N plasma. Shooting, planarizing the dielectric material. Through this sputtering planarization process, rather than conventional
  • the CMP planarization process enables a flatter surface.
  • a strain source/drain technique can also be applied.
  • the fin structure can be selectively etched by sacrificing the gate stack as a mask.
  • a semiconductor layer can be formed by epitaxial growth to form source and drain regions.
  • source and drain regions can stress the channel region (e.g., apply a compressive stress to a p-type device; and apply a tensile stress to an n-type device) to enhance device performance.
  • the substrate 1000 may be a substrate of various forms such as, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate such as a SiGe substrate, or the like.
  • a bulk Si substrate will be described as an example for convenience of explanation.
  • a well region may be formed in the substrate 1000.
  • an n-type well region can be formed; and for an n-type device, a p-type well region can be formed.
  • the n-type well region can be formed by implanting an n-type impurity such as P or As in the substrate 1000, and the p-type well region can be formed by implanting a p-type impurity such as B into the substrate 1000. If necessary, annealing can also be performed after implantation.
  • annealing can also be performed after implantation.
  • the well region can be formed to include two portions 1000-1 and 1000-2. Doping concentration of the portion 1000-2 located above the well region (e.g., less than about 2E18cm_ 3) below the well region located below the portion 1000-1 (e.g., greater than about 2E18cm- 3).
  • a well region can be formed, for example, as follows.
  • a first ion implantation can be performed that enters into the region of the substrate corresponding to the entire well region (1000-1 and 1000-2) (e.g., by controlling ion energy).
  • the first ion implantation results in a relatively low doping concentration (substantially determining the doping concentration of portion 1000-2).
  • a second ion implantation can be performed, which (for example, by controlling the ion energy) enters into a region of the substrate corresponding to the portion 1000-1 having a higher doping concentration.
  • the second ion implantation has the same dopant type as the first ion implantation, so that the doping concentration in the region corresponding to the portion 1000-1 rises (and thus substantially determines the doping concentration of the portion 1000-1).
  • a first ion implantation can be performed that enters into the region of the substrate corresponding to the entire well region (1000-1 and 1000-2) (e.g., by controlling ion energy).
  • the first ion implantation results in a relatively high doping concentration (substantially determining the doping concentration of portion 1000-2).
  • a second ion implantation can be performed that enters into the region of the substrate corresponding to the portion 1000-2 having a lower doping concentration (e.g., by controlling ion energy).
  • the second ion implantation has an opposite dopant type as the first ion implantation, such that the doping concentration in the region corresponding to the portion 1000-2 decreases (and thus substantially determines the doping concentration of the portion 1000-2).
  • the substrate 1000 can be patterned to form a fin structure.
  • a patterned photoresist 1002 is formed on the substrate 1000 as designed.
  • photoresist 1002 is patterned into a series of parallel equally spaced lines.
  • the substrate 1000 is etched by, for example, reactive ion etching (RIE) using the patterned photoresist 1002 as a mask to form a fin structure 1004.
  • RIE reactive ion etching
  • etching of the substrate 1000 can be performed into the well region 1000-1.
  • the photoresist 1002 can be removed.
  • the shape of the trench (between the fin structures 1004) formed by etching is not necessarily the regular rectangular shape shown in FIG. 2, and may be, for example, a taper that gradually becomes smaller from top to bottom. Table shape.
  • the position and number of fin structures formed are not limited to the example shown in Fig. 2.
  • the fin structure is not limited to being formed by directly patterning the substrate.
  • an additional semiconductor layer can be epitaxially grown on the substrate, and the additional semiconductor layer can be patterned to form a fin structure. If there is sufficient etch selectivity between the additional semiconductor layer and the substrate, the patterning can be substantially stopped on the substrate when patterning the fin structure, thereby achieving more precise control of the height of the fin structure. .
  • the expression "forming a fin structure on the (surface of the substrate)” includes forming a fin structure on the (surface of) the substrate in any suitable manner.
  • a sacrificial gate stack intersecting the fin structure may be formed in accordance with the replacement gate process.
  • an isolation layer is first formed on the substrate.
  • a dielectric layer 1006 may be formed on the substrate, for example by deposition, to cover the formed fin structure 1004.
  • dielectric layer 1006 can comprise an oxide such as silicon oxide.
  • the dielectric layer 1006 can be sputtered to the dielectric layer 1006.
  • Flattening is performed.
  • sputtering may use a plasma such as an Ar or N plasma.
  • the cutting speed of the dielectric layer 1006, the sputtering parameters such as the sputtering power, the gas pressure, and the like can be controlled according to plasma sputtering to determine the time during which the plasma sputtering is performed, so that the plasma sputtering can be performed for a certain period of time.
  • the segments are to sufficiently smooth the surface of the dielectric layer 1006.
  • plasma sputtering may end before reaching the top surface of the fin structure 1004 to avoid excessive damage to the fin structure 1004.
  • the top mask of the dielectric layer 1006 has sufficient flatness, and its undulations can be controlled, for example, within a few nanometers.
  • the dielectric layer 1006 may be etched back (eg, RIE) to expose a portion of the fin structure 1004, the exposed Part of it can then be used as the fin of the final device.
  • the remaining dielectric layer 1006 constitutes an isolation layer. Since the surface of the dielectric layer 1006 is smoothed by sputtering before etch back, the surface of the spacer layer 1006 remains substantially uniform on the substrate after etch back. In the case where a well region is formed in the substrate 1000, the isolation layer 1006 preferably slightly exposes the well region.
  • the top surface of the spacer layer 1006 is slightly lower than the top surface of the well region portion 1000-2 (the height difference between them is not shown in the drawing). More specifically, the top surface of the isolation layer 1006 may be between the top surface and the bottom surface of the well region portion 1000-2.
  • a sacrificial gate stack intersecting the fins may be formed on the isolation layer 1006. For example, this can be done as follows.
  • a sacrificial gate dielectric layer 1008 is formed, for example, by deposition.
  • the sacrificial gate dielectric layer 1008 can include an oxide having a thickness of about 0.8-1.5 nm.
  • the sacrificial gate dielectric layer 1008 can also include portions that extend over the top surface of the isolation layer 1006.
  • the sacrificial gate conductor layer 1010 is formed, for example, by deposition.
  • the sacrificial gate conductor layer 1010 may include polysilicon.
  • the sacrificial gate conductor layer 1010 can fill the gap between the fins and can be planarized, such as chemical mechanical polishing (CMP).
  • FIG. 7 shows a cross-sectional view taken along line BB' in FIG. 7(a)
  • the sacrificial gate conductor layer 1010 is patterned to define a sacrificial gate stack.
  • the sacrificial gate conductor layer 1010 is patterned into a strip that intersects the fin structure.
  • the subsequent sacrificial gate conductor layer 1010 is a mask, and the sacrificial gate dielectric layer 1008 is further patterned.
  • a gate spacer 1012 may be formed on the sidewall of the sacrificial gate conductor layer 1010.
  • the gate spacer 1012 can be formed by depositing a nitride (e.g., silicon nitride) having a thickness of about 5 to 20 nm and then performing RIE on the nitride.
  • a nitride e.g., silicon nitride
  • RIE reactive etching
  • strain source/drain techniques can be utilized in accordance with an example of the present disclosure.
  • the exposed sacrificial gate dielectric layer 1008 is first selectively removed (e.g., RIE).
  • RIE etching-reactive ion ion ion ion ion ion ion ion ion ion ion ion ion ion ion ion ion ion etching etching of the sacrificial gate dielectric layer 1008 .
  • the sacrificial gate dielectric layer is further patterned with the sacrificial gate conductor as a mask, which is no longer required.
  • Portions of the fin structure 1004 exposed by the removal of the sacrificial gate dielectric layer 1008 can then be selectively removed (e.g., RIE). This portion of the fin structure 1004 can be etched to reach the well region portion 1000-2. Due to the presence of the sacrificial gate stack (sacrificial gate dielectric layer, sacrificial gate conductor) and gate spacers, the fin structure 1004 can remain below the sacrificial gate stack. It is to be noted here that although the edge of the etched fin structure 1004 is shown as being completely aligned with the edge of the gate spacer 1012 in Fig. 9, the present disclosure is not limited thereto. For example, due to the lateral action of the etch (possibly small), the edge of the etched fin structure 1004 is retracted inwardly relative to the edge of the gate spacer 1012.
  • the semiconductor layer 1014 may be formed on the exposed fin structure portion by, for example, epitaxy. Source/drain regions may then be formed in the semiconductor layer 1014.
  • the semiconductor layer 1014 may be doped in situ while being grown. For example, for an n-type device, n-type in-situ doping can be performed; and for a p-type device, p-type in-situ doping can be performed. Additionally, to further enhance performance, the semiconductor layer 1014 can include a different material than the fin structure 1004 to enable stress to be applied to the fins 1004 where the channel regions of the device will be formed.
  • the semiconductor layer 1014 may include Si:C (the atomic percentage of C is, for example, about 0.2 to 2%) to apply tensile stress; for a p-type device, the semiconductor layer 1014 may include SiGe (for example, an atomic percentage of Ge is about 15-75%) to apply a pressure Stress.
  • the semiconductor layer 1014 is illustrated as a fin corresponding to the fin structure 1004 in the drawing (for example, a portion indicated by a broken line in FIGS. 11(a), 12(a), 14(a)), The disclosure is not limited to this.
  • the semiconductor layer 1014 may be grown to be broadened in the lateral direction to some extent.
  • the growth of the semiconductor layer 1014 may also occur on the top surface of the sacrificial gate conductor layer 1010. This is not shown in the drawings.
  • strain source/drain technique is described above, the present disclosure is not limited thereto.
  • the fin structure 1004 may be retained.
  • source/drain implantation can be performed by sacrificing the gate stack and the gate spacer as a mask to form source/drain regions.
  • a dielectric layer 1016 is formed, for example, by deposition.
  • the dielectric layer 1016 can comprise, for example, an oxide.
  • the dielectric layer 1016 is subjected to a planarization process such as CMP.
  • the CMP can be stopped at the gate spacer 1012 to expose the sacrificial gate conductor layer 1010.
  • Fig. 12 shows a cross-sectional view taken along line BB' in Fig. 12(a)
  • Fig. 12(c) shows a cross-sectional view taken along line CC' in Fig. 12(a)
  • the sacrificial gate conductor 1010 is selectively removed, for example, by a TMAH solution, thereby forming a gate trench 1018 inside the gate spacer 1012.
  • the sacrificial gate dielectric layer 1008 is preferably retained to reduce damage to the fin structure 1004 during subsequent ion implantation.
  • a punch-through barrier (PTS) 1020 can be formed by implantation through the gate trench 1018.
  • the PTS 1020 may include the same doping type as the well regions 1000-1, 1000-2, and the doping concentration is greater than the impurity concentration of the well region.
  • a p-type dopant such as 8, BF 2 or In can be implanted; for a p-type device, an n-type dopant such as 8 or ? can be implanted? .
  • Ion implantation can be perpendicular to the surface of the substrate. The parameters of the ion implantation are controlled such that the PTS is formed in a portion of the fin structure 1004 that is below the surface of the isolation layer 1006 and has a desired doping concentration.
  • a part of the dopant may be scattered from the exposed portion of the fin structure, thereby facilitating the formation of a steep doping profile in the depth direction.
  • This PTS helps to reduce source and drain leakage.
  • the PTS 1020 is self-aligned under the gate trench 1018 due to the presence of the dielectric layer 1016, and the PTS is not formed in the region under the semiconductor layer 1014 for forming the source and drain regions.
  • a gate conductor layer 1024 may be formed in the gate trench 1018 to form a final gate stack.
  • the sacrificial gate dielectric layer 1008 can also be removed, and the gate dielectric layer 1022 and the gate conductor layer 1024 are sequentially formed in the gate trench 1018.
  • the gate dielectric layer 1022 can comprise a high K gate dielectric such as HfO 2 having a thickness of about 1-5 nm.
  • Gate conductor layer 1024 can include a metal gate conductor.
  • a function adjustment layer (not shown) can also be formed between the gate dielectric layer 1022 and the gate conductor layer 1024.
  • the semiconductor device can include a fin structure 1004 formed on a substrate 1000.
  • the semiconductor device can also include an isolation layer 1006 formed over the substrate 1000, the isolation layer 1006 exposing a portion of the fin structure 1004.
  • the exposed portion of the fin structure 1004 can be used as a fin of the semiconductor device.
  • the semiconductor device can also include a gate stack (including gate dielectric layer 1022 and gate conductor layer 1024) formed on isolation layer 1006 that intersects fin 1004.
  • the semiconductor device further includes a PTS 1020 that is self-aligned below the channel region (corresponding to the portion of the fin 1004 that intersects the gate stack).
  • a well region may be formed in the substrate 1000, including a portion 1000-2 having a lower doping concentration and a portion 1000-1 having a higher doping concentration. As shown in Fig. 14, the source/drain regions (formed in the semiconductor layer 1014) are in contact with the well region portion 1000-2 having a lower doping concentration, so that the junction capacitance therebetween can be lowered.
  • the PTS 1020 may include the same doping type as the well regions 1000-1, 1000-2, and the doping concentration is greater than the impurity concentration of the well region.
  • the portion of the fin structure 1004 exposed by the isolation layer 1006 (the above-mentioned "fin") is left under the gate stack and the gate spacer, and a semiconductor layer is formed on the opposite side of the fin. 1014, used to form source/drain regions.
  • the semiconductor layer 1014 may be formed in a fin shape.

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Abstract

本申请公开了一种半导体器件及其制造方法。包括：衬底，衬底中形成有阱区，所述阱区包括第一部分和第二部分，第一部分相比于第二部分掺杂浓度较低，且更接近衬底的表面；在衬底的表面上形成的鳍状结构；在衬底的表面上形成的隔离层，该隔离层露出鳍状结构的一部分，鳍状结构的露出部分用作该半导体器件的鳍；以及在隔离层上形成的与鳍相交的栅堆叠，其中，仅在鳍与栅堆叠相交的部分下方的区域中形成有穿通阻挡部。

Description

半导体器件及其制造方法
本申请要求了 2013年 1月 15日提交的、 申请号为 201310014872.9、发明 名称为 "半导体器件及其制造方法" 的中国专利申请的优先权， 其全部内容通 过引用结合在本申请中。 技术领域
本公开涉及半导体领域， 更具体地， 涉及一种半导体器件及其制造方法。 背景技术
随着平面型半导体器件的尺寸越来越小， 短沟道效应愈加明显。 为此， 提 出了立体型半导体器件如 FinFET (鰭式场效应晶体管）。 一般而言， FinFET 包括在衬底上竖直形成的鰭以及与鰭相交的栅堆叠。 另外，衬底上形成有隔离 层， 以隔离栅堆叠与衬底。 因此， 鰭的底部被隔离层所包围， 从而栅难以有效 控制鰭的底部。 结果， 易于出现源和漏之间经由鰭底部的漏电流。
通常， 可以釆用穿通阻挡部（PTS )来减小这种漏电流。 但是， 这种 PTS 的引入增大了带间泄漏 （band-to-band leakage ), 结泄漏和结电容。 发明内容
本公开的目的至少部分地在于提供一种半导体器件及其制造方法。
根据本公开的一个方面， 提供了一种制造半导体器件的方法， 包括： 在衬 底中形成阱区， 所述阱区包括第一部分和第二部分， 第一部分相比于第二部分 掺杂浓度较低， 且更接近衬底的表面； 在衬底的表面上形成鰭状结构； 在衬底 的表面上形成隔离层， 隔离层露出鰭状结构的一部分，鰭状结构的露出部分用 作该半导体器件的鰭； 在隔离层上形成牺牲栅导体层， 所述栅导体层经由牺牲 栅介质层与鰭状结构相交； 在牺牲栅导体层的侧壁上形成栅侧墙； 在隔离层上 形成电介质层， 并对电介质层进行平坦化， 以露出牺牲栅导体层； 选择性地去 除牺牲栅导体层， 从而在栅侧墙内侧形成栅槽； 经由栅槽， 在鰭下方的区域中 形成穿通阻挡部； 以及在栅槽中形成栅导体。 根据本公开的另一方面， 提供了一种半导体器件， 包括： 衬底， 衬底中形 成有阱区， 所述阱区包括第一部分和第二部分， 第一部分相比于第二部分掺杂 浓度较低， 且更接近衬底的表面； 在衬底的表面上形成的鰭状结构； 在衬底的 表面上形成的隔离层， 该隔离层露出鰭状结构的一部分， 鰭状结构的露出部分 用作该半导体器件的鰭； 以及在隔离层上形成的与鰭相交的栅堆叠， 其中， 仅 在鰭与栅堆叠相交的部分下方的区域中形成有穿通阻挡部。
根据本发明的示例性实施例， 所形成的 PTS 自对准于沟道区下方， 从而 可以有效降低源和漏之间的漏电流。 另外， 由于在源、 漏区下方并不形成这种
PTS , 从而可以有效降低带间泄漏和结泄漏。 另外， 由于阱区中掺杂浓度相对 较低的第一部分的存在， 可以进一步降低源 /漏与阱区之间的结电容。 附图说明
通过以下参照附图对本公开实施例的描述， 本公开的上述以及其他目的、 特征和优点将更为清楚， 在附图中：
图 1-14是示出了根据本公开实施例的制造半导体器件流程的示意图。 具体实施方式
以下， 将参照附图来描述本公开的实施例。 但是应该理解， 这些描述只是 示例性的， 而并非要限制本公开的范围。 此外， 在以下说明中， 省略了对公知 结构和技术的描述， 以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比 例绘制的， 其中为了清楚表达的目的， 放大了某些细节， 并且可能省略了某些 细节。 图中所示出的各种区域、 层的形状以及它们之间的相对大小、位置关系 仅是示例性的， 实际中可能由于制造公差或技术限制而有所偏差， 并且本领域 技术人员根据实际所需可以另外设计具有不同形状、 大小、 相对位置的区域 / 层。
在本公开的上下文中， 当将一层 /元件称作位于另一层 /元件 "上" 时， 该 层 /元件可以直接位于该另一层 /元件上， 或者它们之间可以存在居中层 /元件。 另外，如果在一种朝向中一层 /元件位于另一层 /元件"上"，那么当调转朝向时， 该层 /元件可以位于该另一层 /元件 "下"。
根据本公开的实施例，提供了一种半导体器件， 该半导体器件可以包括衬 底、在衬底上形成的鰭状结构以及与鰭状结构相交的栅堆叠。栅堆叠可以通过 隔离层与衬底相隔离。 隔离层可以露出鰭状结构的一部分，鰭状结构的该露出 部分可以用作该半导体器件的真正鰭。
该半导体器件还可以包括掩埋于衬底中的阱区。为了降低该半导体器件的 源 /漏区与阱区之间的结电容， 阱区可以包括第一部分和第二部分， 第一部分 相比于第二部分掺杂浓度较低， 且更接近衬底的表面。 这样， 源 /漏区可以通 过掺杂浓度较低的第一部分与阱区相接。
为防止源漏区之间经由鰭底部的泄漏， 并同时降低源 /漏区与衬底之间的 结电容和结泄漏， 该半导体器件可以包括仅在沟道区下方形成的穿通阻挡部
( PTS )。 这种 PTS例如可以通过本文所述的自对准技术来形成。
根据本公开的实施例， 这种自对准技术可以通过结合替代栅技术来实现。 例如， 这种 PTS可以经由根据替代栅技术形成的替代栅槽（或孔）， 进行离子 注入来形成。 这样， 所形成的 PTS位于替代栅槽（在其中随后形成真正的栅 堆叠）下方， 并因此自对准于沟道区（在包括鰭的器件中， 鰭与栅堆叠相交的 区 i或） 下方。
具体地， 可以在衬底上（例如， 通过对衬底进行构图）形成鰭状结构。 然 后，可以根据替代栅技术，形成牺牲栅堆叠。例如，可以在衬底上形成隔离层， 隔离层包围鰭状结构的底部， 并露出鰭状结构的剩余部分（鰭状结构的露出部 分用作最终器件的真正鰭）。 在隔离层上形成牺牲栅堆叠。 该牺牲栅堆叠例如 可以包括牺牲栅介质层和牺牲栅导体层。 在牺牲栅堆叠的侧壁上形成栅侧墙。 然后， 在隔离层上形成电介质层， 并对其进行平坦化例如化学机械抛光
( CMP ), 以露出牺牲栅堆叠。 之后， 可以选择性去除牺牲栅导体层， 从而在 栅侧墙内侧形成栅槽（或孔）。 可以经由该栅槽（或孔）， 例如通过离子注入来 形成 PTS。 由于电介质层的存在， 离子基本上仅注入到位于栅槽（或孔）下方 的区域中。
根据本公开的实施例，隔离层可以通过在衬底上淀积电介质材料然后回蚀 来形成。 在回蚀之前， 可以通过溅射（sputtering ), 例如 Ar或 N等离子体溅 射， 对电介质材料进行平坦化处理。 通过这种溅射平坦化处理， 而非常规的
CMP平坦化处理， 可以实现更加平坦的表面。
根据本公开的实施例， 还可以应用应变源 /漏技术。 例如， 在形成牺牲栅 堆叠之后， 可以牺牲栅堆叠为掩模， 对鰭状结构进行选择性刻蚀。 然后， 可以 通过外延生长形成一半导体层， 用以形成源、 漏区。 这种源、 漏区可以向沟道 区施加应力（例如， 对于 p型器件， 施加压应力； 而对于 n型器件， 施加拉应 力）， 以增强器件性能。
本公开可以各种形式呈现， 以下将描述其中一些示例。
如图 1所示， 提供衬底 1000。 该衬底 1000可以是各种形式的衬底， 例如 但不限于体半导体材料衬底如体 Si衬底、 绝缘体上半导体 ( SOI )衬底、 化合 物半导体衬底如 SiGe衬底等。 在以下的描述中， 为方便说明， 以体 Si衬底为 例进行描述。
根据本公开的一些示例， 可以在衬底 1000中形成阱区。 例如， 对于 p型 器件， 可以形成 n型阱区； 而对于 n型器件， 可以形成 p型阱区。 例如， n型 阱区可以通过在衬底 1000中注入 n型杂质如 P或 As来形成， p型阱区可以通 过在衬底 1000中注入 p型杂质如 B来形成。 如果需要， 在注入之后还可以进 行退火。 本领域技术人员能够想到多种方式来形成 n型阱、 p型阱， 在此不再 赘述。
为改善器件性能， 可以将阱区形成为包括两个部分 1000-1和 1000-2。 位 于上方的阱区部分 1000-2的掺杂浓度（例如， 低于约 2E18cm_3 )低于位于下 方的阱区部分 1000-1 (例如， 高于约 2E18cm-3 )。 这样的阱区例如可以如下所 述形成。
根据一示例， 可以进行第一离子注入， 该第一离子注入（例如， 通过控制 离子能量）进入到衬底中与整个阱区 （ 1000-1 和 1000-2 )相对应的区域中。 第一离子注入导致相对较低的掺杂浓度 (基本上决定部分 1000-2的掺杂浓度）。 接着， 可以进行第二离子注入， 该第二离子注入（例如， 通过控制离子能量） 进入到衬底中与掺杂浓度较高的部分 1000-1相对应的区域中。 第二离子注入 与第一离子注入具有相同的掺杂剂类型， 从而与部分 1000-1相对应的区域中 的掺杂浓度上升 （并因此基本上决定部分 1000-1的掺杂浓度）。 根据另一示例， 可以进行第一离子注入， 该第一离子注入（例如， 通过控 制离子能量）进入到衬底中与整个阱区 （ 1000-1和 1000-2 )相对应的区域中。 第一离子注入导致相对较高的掺杂浓度 (基本上决定部分 1000-2的掺杂浓度）。 接着， 可以进行第二离子注入， 该第二离子注入（例如， 通过控制离子能量） 进入到衬底中与掺杂浓度较低的部分 1000-2相对应的区域中。 第二离子注入 与第一离子注入具有相反的掺杂剂类型， 从而与部分 1000-2相对应的区域中 的掺杂浓度下降（并因此基本上决定部分 1000-2的掺杂浓度）。
接下来， 可以对衬底 1000进行构图， 以形成鰭状结构。 例如， 这可以如 下进行。 具体地， 在衬底 1000上按设计形成构图的光刻胶 1002。 通常， 光刻 胶 1002被构图为一系列平行的等间距线条。 然后， 如图 2所示， 以构图的光 刻胶 1002为掩模， 对衬底 1000进行刻蚀例如反应离子刻蚀 （RIE ), 从而形 成鰭状结构 1004。在此，对衬底 1000的刻蚀可以进行到阱区 1000-1中。之后， 可以去除光刻胶 1002。
这里需要指出的是， 通过刻蚀所形成的 （鰭状结构 1004之间的） 沟槽的 形状不一定是图 2中所示的规则矩形形状，可以是例如从上到下逐渐变小的锥 台形。 另外， 所形成的鰭状结构的位置和数目不限于图 2所示的示例。
另外， 鰭状结构不限于通过直接对衬底进行构图来形成。 例如， 可以在衬 底上外延生长另外的半导体层， 对该另外的半导体层进行构图来形成鰭状结 构。如果该另外的半导体层与衬底之间具有足够的刻蚀选择性， 则在对鰭状结 构进行构图时， 可以使构图基本上停止于衬底，从而实现对鰭状结构高度的较 精确控制。
因此， 在本公开中， 表述 "在衬底（的表面）上形成鰭状结构" 包括以任 何适当的方式在衬底（的表面）上形成鰭状结构。
在通过上述处理形成鰭状结构之后， 可以按照替代栅工艺， 形成与鰭状结 构相交的牺牲栅堆叠。
为了隔离栅堆叠和衬底，在衬底上首先形成隔离层。具体地，如图 3所示， 可以在衬底上例如通过淀积形成电介质层 1006,以覆盖形成的鰭状结构 1004。 例如， 电介质层 1006可以包括氧化物 （如氧化硅）。
然后， 如图 4所示， 可以对电介质层 1006进行溅射， 来对电介质层 1006 进行平坦化处理。 例如， 溅射可以使用等离子体， 如 Ar或 N等离子体。 在此， 例如可以根据等离子体溅射对电介质层 1006的切削速度， 控制溅射参数例如 溅射功率和气压等， 来确定进行等离子体溅射的时间，使得等离子体溅射能够 执行一定的时间段以充分平滑电介质层 1006的表面。 另一方面， 在图 4所示 的示例中， 等离子体溅射可以在到达鰭状结构 1004的顶面之前结束， 以避免 对鰭状结构 1004造成过多的损伤。
尽管在图 4中示出了微观上的起伏， 但是事实上电介质层 1006的顶面具 有充分的平坦度， 其起伏可以控制在例如几个纳米之内。
根据本公开的另一实施例，还可以根据需要，对通过溅射平坦化后的电介 质层 1006进行少许 CMP。
在电介质层 1006的表面通过等离子体溅射而变得充分平滑之后， 如图 5 所示， 可以对电介质层 1006 进行回蚀 （例如， RIE ), 以露出鰭状结构 1004 的一部分， 该露出的部分随后可以用作最终器件的鰭。 剩余的电介质层 1006 构成隔离层。 由于回蚀之前电介质层 1006的表面通过溅射而变得平滑， 所以 回蚀之后隔离层 1006的表面在衬底上基本上保持一致。在衬底 1000中形成阱 区的情况下， 隔离层 1006优选稍稍露出阱区。 即， 隔离层 1006的顶面略低于 阱区部分 1000-2的顶面 （附图中没有示出它们之间的高度差）。 更具体而言， 隔离层 1006的顶面可以在阱区部分 1000-2的顶面与底面之间。
随后， 可以在隔离层 1006上形成与鰭相交的牺牲栅堆叠。 例如， 这可以 如下进行。
具体地， 如图 6所示， 例如通过淀积， 形成牺牲栅介质层 1008。 例如， 牺牲栅介质层 1008可以包括氧化物， 厚度为约 0.8-1.5nm。 在图 6所示的示例 中， 仅示出了 " Π " 形的牺牲栅介质层 1008。 但是， 牺牲栅介质层 1008也可 以包括在隔离层 1006的顶面上延伸的部分。 然后， 例如通过淀积， 形成牺牲 栅导体层 1010。例如，牺牲栅导体层 1010可以包括多晶硅。牺牲栅导体层 1010 可以填充鰭之间的间隙， 并可以进行平坦化处理例如化学机械抛光（ CMP )。
之后， 如图 7 (图 7 ( b )示出了沿图 7 ( a ) 中 BB'线的截面图）所示， 对 牺牲栅导体层 1010进行构图， 以限定牺牲栅堆叠。 在图 7的示例中， 牺牲栅 导体层 1010被构图为与鰭状结构相交的条形。 根据另一实施例， 还可以构图 后的牺牲栅导体层 1010为掩模， 进一步对牺牲栅介质层 1008进行构图。
接下来， 如图 8所示 （图 8 ( b )示出了沿图 8 ( a ) 中 CC'线的截面图）， 可以在牺牲栅导体层 1010的侧壁上形成栅侧墙 1012。 例如， 可以通过淀积形 成厚度约为 5-20nm的氮化物（如氮化硅）， 然后对氮化物进行 RIE, 来形成栅 侧墙 1012。 本领域技术人员知道多种方式来形成这种栅侧墙， 在此不再赘述。 在鰭状结构之间的沟槽为从上到下逐渐变小的锥台形时（由于刻蚀的特性，通 常为这样的情况）， 侧墙 1012基本上不会形成于鰭状结构的侧壁上。
为改善器件的性能， 根据本公开的一示例， 可以利用应变源 /漏技术。 具 体地， 如图 9所示， 首先选择性去除（例如， RIE )暴露在外的牺牲栅介质层 1008。在牺牲栅介质层 1008和隔离层 1006均包括氧化物的情况下， 由于牺牲 栅介质层 1008较薄， 因此对牺牲栅介质层 1008的 RIE基本上不会影响隔离 层 1006。 在以上形成牺牲栅堆叠的过程中， 以牺牲栅导体为掩模进一步构图 牺牲栅介质层的情况下， 不再需要该操作。
然后， 可以选择性去除（例如， RIE ) 由于牺牲栅介质层 1008 的去除而 露出的鰭状结构 1004的部分。对鰭状结构 1004该部分的刻蚀可以进行至到达 阱区部分 1000-2。 由于牺牲栅堆叠（牺牲栅介质层、 牺牲栅导体）和栅侧墙的 存在， 鰭状结构 1004可以留于牺牲栅堆叠下方。 这里需要指出的是， 尽管在 图 9中将刻蚀后鰭状结构 1004的边缘示出为与栅侧墙 1012的边缘完全对准， 但是本公开不限于此。 例如， 由于刻蚀的横向作用 （可能很小）， 从而刻蚀后 鰭状结构 1004的边缘相对于栅侧墙 1012的边缘向里缩进。
接下来， 如图 10所示， 例如可以通过外延， 在露出的鰭状结构部分上形 成半导体层 1014。 随后可以在该半导体层 1014中形成源 /漏区。根据本公开的 一实施例， 可以在生长半导体层 1014的同时， 对其进行原位掺杂。 例如， 对 于 n型器件， 可以进行 n型原位掺杂； 而对于 p型器件， 可以进行 p型原位掺 杂。另外，为了进一步提升性能，半导体层 1014可以包括不同于鰭状结构 1004 的材料， 以便能够向鰭 1004 (其中将形成器件的沟道区）施加应力。 例如， 在鰭状结构 1004包括 Si的情况下， 对于 n型器件， 半导体层 1014可以包括 Si:C ( C的原子百分比例如为约 0.2-2% ), 以施加拉应力； 对于 p型器件， 半 导体层 1014可以包括 SiGe (例如， Ge的原子百分比为约 15-75% ), 以施加压 应力。
尽管在附图中将半导体层 1014示出为与鰭状结构 1004相对应的鰭状（例 如， 图 11 (a)、 12 (a)、 14 (a) 中的虚线所示部位）， 但是本公开不限于此。 例如， 为了方便制造与源 /漏区的接触， 可以将半导体层 1014生长为在横向上 展宽一定程度。
在牺牲栅导体层 1010包括多晶硅的情况下，半导体层 1014的生长可能也 会发生在牺牲栅导体层 1010的顶面上。 这在附图中并未示出。
这里需要指出的是， 尽管以上描述了应变源 /漏技术， 但是本公开不限于 此。 例如， 可以不进行图 9-10的操作， 而是保留鰭状结构 1004。 在这种情况 下， 可以牺牲栅堆叠和栅侧墙为掩模， 进行源 /漏注入， 来形成源 /漏区。
接下来， 如图 11 (图 11 (b)示出了沿图 11 (a) 中 CC'线的截面图） 所 示， 例如通过淀积， 形成电介质层 1016。 该电介质层 1016例如可以包括氧化 物。 随后， 对该电介质层 1016进行平坦化处理例如 CMP。 该 CMP可以停止 于栅侧墙 1012, 从而露出牺牲栅导体层 1010。
随后， 如图 12 (图 12 (b)示出了沿图 12 (a) 中 BB'线的截面图， 图 12 (c)示出了沿图 12 (a) 中 CC'线的截面图）所示， 例如通过 TMAH溶液， 选择性去除牺牲栅导体 1010,从而在栅侧墙 1012内侧形成了栅槽 1018。这里， 优选地可以保留牺牲栅介质层 1008, 以在随后的离子注入过程中减小对鰭状 结构 1004的损伤。
然后， 如图 13 (图 13 (a)示出了与图 12 (b)的截面图相对应的截面图， 图 13 (b)示出了与图 12 (c) 中的截面图相对应的截面图） 所示， 可以经由 栅槽 1018, 通过注入来形成穿通阻挡部 （PTS) 1020。 PTS 1020可以包括与 阱区 1000-1、 1000-2相同的掺杂类型， 并且掺杂浓度大于阱区的杂质浓度。 例如， 对于 n型器件而言， 可以注入 p型掺杂剂， 如：8、 BF2或 In; 对于 p型 器件， 可以注入 n型掺杂剂， 如 8或？。 离子注入可以垂直于衬底表面。 控 制离子注入的参数， 使得 PTS形成于鰭状结构 1004位于隔离层 1006表面之 下的部分中， 并且具有期望的掺杂浓度。 应当注意， 由于鰭状结构 1004的形 状因子 （细长形）， 一部分掺杂剂 （离子或元素）可能从鰭状结构的露出部分 散射出去，从而有利于在深度方向上形成陡峭的掺杂分布。可以进行退火如尖 峰退火、 激光退火和 /或快速退火， 以激活注入的掺杂剂。 这种 PTS有助于减 小源漏泄漏。 如图 13 ( b ) 所示， 由于电介质层 1016的存在， PTS 1020自对 准于栅槽 1018下方， 而在用以形成源、 漏区的半导体层 1014下方的区域中并 没有形成 PTS。
然后， 如图 14 (图 14 ( b )示出了沿图 14 ( a ) 中 CC'线的截面图）所示， 可以在栅槽 1018中形成栅导体层 1024 , 形成最终的栅堆叠。 优选地， 还可以 去除牺牲栅介质层 1008, 并在栅槽 1018中依次形成栅介质层 1022和栅导体 层 1024。 栅介质层 1022可以包括高 K栅介质例如 Hf02, 厚度为约 l-5nm。 栅导体层 1024可以包括金属栅导体。 优选地， 在栅介质层 1022和栅导体层 1024之间还可以形成功函数调节层 （未示出）。
这样， 就得到了根据本公开实施例的半导体器件。 如图 14所示， 该半导 体器件可以包括在衬底 1000上形成的鰭状结构 1004。 该半导体器件还可以包 括在衬底 1000上形成的隔离层 1006, 该隔离层 1006露出鰭状结构 1004的一 部分。 鰭状结构 1004的该露出部分可以用作该半导体器件的鰭。 另外， 该半 导体器件还可以包括在隔离层 1006上形成的与鰭 1004相交的栅堆叠（包括栅 介质层 1022和栅导体层 1024 )。 另外， 该半导体器件还包括自对准于沟道区 (对应于鰭 1004与栅堆叠相交的部分） 下方的 PTS 1020。
衬底 1000中可以形成有阱区， 包括掺杂浓度较低的部分 1000-2和掺杂浓 度较高的部分 1000-1。 如图 14所示， 源 /漏区 （形成于半导体层 1014中）与 掺杂浓度较低的阱区部分 1000-2接触，从而可以降低它们之间的结电容。 PTS 1020可以包括与阱区 1000-1、 1000-2相同的掺杂类型， 并且掺杂浓度大于阱 区的杂质浓度。
另外，在应用应变源漏技术的情况下， 鰭状结构 1004被隔离层 1006露出 的部分（上述 "鰭"） 留于栅堆叠和栅侧墙下方， 且在鰭的相对侧面上形成有 半导体层 1014, 用以形成源 /漏区。 半导体层 1014可以形成为鰭状。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说 明。 但是本领域技术人员应当理解， 可以通过各种技术手段， 来形成所需形状 的层、 区域等。 另外， 为了形成同一结构， 本领域技术人员还可以设计出与以 上描述的方法并不完全相同的方法。 另外， 尽管在以上分别描述了各实施例， 但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是， 这些实施例仅仅是为了说明的 目的， 而并非为了限制本公开的范围。 本公开的范围由所附权利要求及其等价 物限定。 不脱离本公开的范围， 本领域技术人员可以做出多种替代和修改， 这 些替代和修改都应落在本公开的范围之内。

Claims

权 利 要 求 书
1. 一种制造半导体器件的方法， 包括：
在衬底中形成阱区， 所述阱区包括第一部分和第二部分， 第一部分相比于 第二部分掺杂浓度较低， 且更接近衬底的表面；
在衬底的表面上形成鰭状结构；
在衬底的表面上形成隔离层， 隔离层露出鰭状结构的一部分，鰭状结构的 露出部分用作该半导体器件的鰭；
在隔离层上形成牺牲栅导体层，所述牺牲栅导体层经由牺牲栅介质层与鰭 状结构相交；
在牺牲栅导体层的侧壁上形成栅侧墙；
在隔离层上形成电介质层， 并对电介质层进行平坦化， 以露出牺牲栅导体 层；
选择性地去除牺牲栅导体层， 从而在栅侧墙内侧形成栅槽；
经由栅槽， 在鰭下方的区域中形成穿通阻挡部； 以及
在栅槽中形成栅导体。
2. 根据权利要求 1所述的方法， 其中， 形成穿通阻挡部包括： 对于 n型器件， 经由栅槽注入 p型掺杂剂； 和 /或
对于 p型器件， 经由栅槽注入 n型掺杂剂。
3. 根据权利要求 1所述的方法， 其中， 形成阱区包括：
进行掺杂剂类型相同的两次离子注入，其中第一离子注入进入到与第一部 分和第二部分相对应的衬底区域中，第二离子注入进入到与第二部分相对应的 衬底区域中。
4. 根据权利要求 1所述的方法， 其中， 形成阱区包括：
进行掺杂剂类型相反的两次离子注入，其中第一离子注入进入到与第一部 分和第二部分相对应的衬底区域中，第二离子注入进入到与第一部分相对应的 衬底区域中。
5. 根据权利要求 1所述的方法， 其中， 形成隔离层包括：
在衬底上淀积电介质材料； 通过溅射对电介质材料进行平坦化； 以及
对电介质材料进行回蚀， 以露出鰭状结构的一部分。
6. 根据权利要求 1所述的方法， 其中， 在形成栅侧墙之后且在形成电 介质层之前， 该方法还包括：
以栅侧墙和牺牲栅导体层为掩模， 对鰭状结构进行选择性刻蚀； 以及 外延生长半导体层， 用以形成源、 漏区。
7. 根据权利要求 6所述的方法， 还包括： 在外延生长半导体层同时， 对该半导体层进行原位掺杂。
8. 根据权利要求 6所述的方法， 其中， 对于 p型器件， 半导体层带压 应力； 而对于 n型器件， 半导体层带拉应力。
9. 根据权利要求 1所述的方法， 其中，
在形成穿通阻挡部之后， 该方法还包括： 选择性去除牺牲栅介质层， 以及 在形成栅导体之前， 该方法还包括： 在栅槽中形成栅介质层。
10. 一种半导体器件， 包括：
衬底， 衬底中形成有阱区， 所述阱区包括第一部分和第二部分， 第一部分 相比于第二部分掺杂浓度较低， 且更接近衬底的表面；
在衬底的表面上形成的鰭状结构；
在衬底的表面上形成的隔离层， 该隔离层露出鰭状结构的一部分，鰭状结 构的露出部分用作该半导体器件的鰭； 以及
在隔离层上形成的与鰭相交的栅堆叠，
其中， 仅在鰭与栅堆叠相交的部分下方的区域中形成有穿通阻挡部。
11. 根据权利要求 10所述的半导体器件，还包括： 在鰭的相对侧面上形 成的半导体层， 在该半导体层中形成半导体器件的源 /漏区。
12. 根据权利要求 11所述的半导体器件， 其中， 对于 p型器件， 半导体 层带压应力； 而对于 n型器件， 半导体层带拉应力。
13. 根据权利要求 12所述的半导体器件， 其中， 衬底包括 Si, 鰭与衬底 一体， 半导体层包括 SiGe或 Si:C。
14. 根据权利要求 10所述的半导体器件， 其中， 所述穿通阻挡部自对准 于所述栅堆叠， 并且穿通阻挡部的掺杂类型与所述阱区的掺杂类型相同， 并且 掺杂浓度高于阱区的掺杂浓度。
15. 根据权利要求 10所述的半导体器件， 其中， 第一部分的掺杂浓度低 于约 2E18cm-3, 且第二部分的掺杂浓度高于约 2E18cm-3。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160329326A1 (en) * 2015-05-05 2016-11-10 International Business Machines Corporation Sub-fin doped bulk fin field effect transistor (finfet), integrated circuit (ic) and method of manufacture

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105552124B (zh) * 2014-10-30 2018-11-16 中芯国际集成电路制造(上海)有限公司 鳍式场效应管及其形成方法
US9954107B2 (en) * 2015-05-05 2018-04-24 International Business Machines Corporation Strained FinFET source drain isolation
US9698225B2 (en) * 2015-07-07 2017-07-04 International Business Machines Corporation Localized and self-aligned punch through stopper doping for finFET
US9368569B1 (en) * 2015-09-21 2016-06-14 International Business Machines Corporation Punch through stopper for semiconductor device
CN106611787A (zh) * 2015-10-26 2017-05-03 联华电子股份有限公司 半导体结构及其制作方法
US9659930B1 (en) * 2015-11-04 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10205024B2 (en) * 2016-02-05 2019-02-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure having field plate and associated fabricating method
CN107799421B (zh) * 2016-09-05 2021-04-02 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
WO2020141758A1 (ko) * 2018-12-31 2020-07-09 울산과학기술원 트랜지스터 소자, 이를 포함하는 삼진 인버터 장치, 및 이의 제조 방법
CN111834212B (zh) * 2019-04-23 2023-05-26 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070026615A1 (en) * 2005-07-27 2007-02-01 Sinan Goktepeli Method of forming a FINFET structure
US20090206405A1 (en) * 2008-02-15 2009-08-20 Doyle Brian S Fin field effect transistor structures having two dielectric thicknesses
US20090267155A1 (en) * 2008-04-24 2009-10-29 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
CN101960572A (zh) * 2008-03-06 2011-01-26 美光科技公司 具有空腔界定栅极的装置及其制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4057770B2 (ja) * 2000-10-11 2008-03-05 株式会社ルネサステクノロジ 半導体集積回路装置
US6764884B1 (en) * 2003-04-03 2004-07-20 Advanced Micro Devices, Inc. Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
KR100626372B1 (ko) * 2004-04-09 2006-09-20 삼성전자주식회사 전계 효과 트랜지스터를 갖는 반도체 소자 및 그 제조 방법
JP4921755B2 (ja) * 2005-09-16 2012-04-25 株式会社東芝 半導体装置
US8912602B2 (en) * 2009-04-14 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US8466034B2 (en) * 2010-03-29 2013-06-18 GlobalFoundries, Inc. Method of manufacturing a finned semiconductor device structure
US9023715B2 (en) * 2012-04-24 2015-05-05 Globalfoundries Inc. Methods of forming bulk FinFET devices so as to reduce punch through leakage currents

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070026615A1 (en) * 2005-07-27 2007-02-01 Sinan Goktepeli Method of forming a FINFET structure
US20090206405A1 (en) * 2008-02-15 2009-08-20 Doyle Brian S Fin field effect transistor structures having two dielectric thicknesses
CN101960572A (zh) * 2008-03-06 2011-01-26 美光科技公司 具有空腔界定栅极的装置及其制造方法
US20090267155A1 (en) * 2008-04-24 2009-10-29 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160329326A1 (en) * 2015-05-05 2016-11-10 International Business Machines Corporation Sub-fin doped bulk fin field effect transistor (finfet), integrated circuit (ic) and method of manufacture
US10903210B2 (en) * 2015-05-05 2021-01-26 International Business Machines Corporation Sub-fin doped bulk fin field effect transistor (FinFET), Integrated Circuit (IC) and method of manufacture

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