WO2015021670A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2015021670A1
WO2015021670A1 PCT/CN2013/082534 CN2013082534W WO2015021670A1 WO 2015021670 A1 WO2015021670 A1 WO 2015021670A1 CN 2013082534 W CN2013082534 W CN 2013082534W WO 2015021670 A1 WO2015021670 A1 WO 2015021670A1
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Prior art keywords
gate
substrate
gate stack
semiconductor device
dielectric layer
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PCT/CN2013/082534
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English (en)
French (fr)
Inventor
朱慧珑
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中国科学院微电子研究所
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Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to US14/402,304 priority Critical patent/US20160240624A1/en
Publication of WO2015021670A1 publication Critical patent/WO2015021670A1/zh
Priority to US15/424,642 priority patent/US9825135B2/en

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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Definitions

  • the present disclosure relates to the field of semiconductors, and more particularly to a semiconductor device and a method of fabricating the same.
  • the device fabrication process is first performed using a sacrificial gate stack.
  • the sacrificial gate is then removed and replaced with a true gate stack.
  • the space left after the sacrificial gate is removed is becoming smaller and smaller, so it becomes more and more difficult to fill a true gate stack therein.
  • a method of fabricating a semiconductor device can include: forming a sacrificial gate stack on a substrate; forming a gate spacer on a sidewall of the sacrificial gate stack; forming an interlayer dielectric layer on the substrate, and planarizing it to expose the sacrificial gate stack; Etching back the sacrificial gate stack to form an opening; expanding the resulting opening such that the opening assumes a shape that gradually increases from a side closer to the substrate toward the side away from the substrate; and removing the remaining sacrificial gate stack, and A gate stack is formed inside the side walls.
  • a semiconductor device may include: a substrate; a gate stack formed on the substrate; and a gate spacer on the sidewall of the gate stack, wherein a volume defined by the gate spacer is present at least in a portion thereof away from the substrate side Moving away from the side near the substrate A gradually increasing shape on one side of the substrate.
  • the space inside the gate spacer may be enlarged at least in the upper portion thereof by, for example, atomic or ion bombardment, in particular, a shape that gradually increases from the bottom to the top. This helps to improve the filling of the subsequent gate stack into this space.
  • FIGS. 1-5 are schematic views showing a flow of manufacturing a semiconductor device according to an embodiment of the present disclosure
  • FIGS. 6-8 are schematic views showing a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure
  • FIGS. A schematic diagram of a process for fabricating a semiconductor device in accordance with still another embodiment of the present disclosure
  • FIG. 22 is a schematic view showing a semiconductor device in accordance with still another embodiment of the present disclosure. detailed description
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be located directly on the other layer/element, or a central layer may be present between them. element. In addition, if a layer/element is "on” another layer/element, the layer/element may be "under” the other layer/element when the orientation is reversed.
  • a semiconductor device is provided.
  • the semiconductor device can be included in A gate stack formed on the substrate and a gate spacer on the sidewalls of the gate stack.
  • the volume defined by the gate spacers expands at a distance from the substrate relative to its proximity to the substrate. Therefore, this form of the gate spacer (on the inner side thereof) defines a space that is large and small (here, the side far from the substrate is referred to as "upper", and the side close to the substrate is referred to as "lower”; ).
  • the gate stack is relatively easy to fill into such a space.
  • the volume defined by the gate spacer may be at least from a side of the substrate (eg, the lower side) toward a side away from the substrate (at least in a portion thereof away from the side of the substrate (eg, the upper side) (
  • the upper side is gradually increased in size, thereby exhibiting, for example, a bucket shape that is large and small.
  • Such a gate spacer is easy to manufacture.
  • the gate stack can include a variety of suitable configurations.
  • the gate stack can include a stack of gate dielectric layers (e.g., high-k gate dielectric layers) and gate conductor layers (e.g., metal gate conductor layers) with a success function adjustment layer therebetween.
  • the gate stack can be used for planar devices such as MOSFETs.
  • a gate stack can be formed on the active region in the substrate to define a channel region in the active region. In the active regions on both sides of the channel region, source and drain regions may be formed.
  • the gate stack can be used for a stereotype device such as a FinFETo. Specifically, the gate stack can intersect the fins formed on the substrate and thus define a channel region in the fin.
  • the semiconductor device may further include a punch-through barrier (PTS) formed in a region below the intersection of the fin and the gate stack (specifically, the channel region).
  • PTS punch-through barrier
  • the gate stack does not fill the volume defined by the full gate spacer.
  • the gate conductor layer may be IHJ with respect to the end of the gate spacer away from the substrate side (e.g., the upper end portion).
  • the gate conductor layer of the IHJ can be covered with a dielectric layer. In this case, the process margin of the source/drain contact can be improved.
  • a method of fabricating a semiconductor device is provided that is particularly suitable for use in a back gate process.
  • a sacrificial gate stack can be formed on the substrate, and then device fabrication (e.g., formation of source and drain regions) can be performed using the sacrificial gate stack.
  • device fabrication e.g., formation of source and drain regions
  • the sacrificial gate stack can be removed leaving a gate trench inside the gate spacer.
  • the gate spacer can be processed to increase the gate trench at its upper portion. In this way, the gate stack can be filled into the gate trench relatively easily.
  • the sacrificial gate stack may be partially removed prior to processing the gate spacers, and after processing the gate spacers, the remaining sacrificial gate stacks may be removed.
  • the treatment of the grid spacers can be carried out, for example, by atomic and/or ion bombardment. According to one Advantageously, plasma sputtering can be employed.
  • FIG. 5 is a schematic view showing a semiconductor device in accordance with an embodiment of the present disclosure.
  • the semiconductor device can include a gate stack formed on the substrate 100.
  • the gate stack may include a gate dielectric layer 110 and a gate conductor layer 112.
  • the semiconductor device can also include a gate spacer 106 formed on a sidewall of the gate stack (in this example, gate dielectric layer 110).
  • the gate spacer 106 can be shaped such that its defined volume (eg, the volume inside it, in this example, specifically the volume occupied by the gate stack) increases relative to the substrate near the substrate .
  • the volume is in the shape of a bucket that is large and small in its upper portion.
  • an interlayer dielectric layer 108 formed on the substrate 100 is also shown in FIG.
  • the upper surface of the interlayer dielectric layer 108 may be flush with the upper surface of the gate stack.
  • the semiconductor device can be manufactured, for example, as follows.
  • a substrate 100 is provided.
  • the substrate 100 may be a suitable substrate in various forms, such as a bulk semiconductor substrate such as Si, Ge, etc., a compound semiconductor substrate such as SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb Etc., a semiconductor-on-insulator substrate (SOI) or the like.
  • a bulk silicon substrate and a silicon-based material will be described as an example. However, it should be noted that the present disclosure is not limited thereto.
  • a sacrificial gate stack can be formed on the substrate 100.
  • the sacrificial gate dielectric layer 102 and the sacrificial gate conductor layer 104 may be sequentially formed by deposition.
  • the sacrificial gate dielectric layer 102 may include an oxide (eg, SiO 2 ), and the sacrificial gate conductor layer 104 may include polysilicon.
  • the sacrificial gate dielectric layer 102 and the sacrificial gate conductor layer 104 can be patterned into a sacrificial gate stack, such as by photolithography. Halo and extension implants can be performed at the expense of the gate stack as a mask.
  • a gate spacer 106 may be formed on the sidewall of the gate stack.
  • the gate spacer 106 can be formed by conformally depositing a layer of nitride (e.g., silicon nitride) on the substrate and selectively etching the nitride layer, such as reactive ion etching (RIE). Subsequently, source/drain implantation can be performed using the gate stack and gate spacer 106 as a mask. An annealing treatment may also be performed to activate the implanted ions and form source/drain regions (not shown).
  • nitride e.g., silicon nitride
  • RIE reactive ion etching
  • gate spacer 106 In Figure 1, a single layer of gate spacers 106 is shown. However, the present disclosure is not limited thereto.
  • the gate spacer 106 can include a configuration of two or more layers.
  • An interlayer dielectric layer 108 can then be formed over the resulting structure. For example, it can be deposited by The oxide is then planarized, such as chemical mechanical polishing (CMP), to form the interlayer dielectric layer 108.
  • CMP chemical mechanical polishing
  • the gate spacer 106 may be a stop point so that the sacrificial gate stack can be exposed.
  • the sacrificial gate stack (in this example, the sacrificial gate conductor layer 104) may be partially etched back by selective etching such as RIE.
  • the etch back depth is, for example, about 10 nm to 60 nm.
  • an opening is formed inside the gate spacer 106.
  • the upper surface of the structure shown in FIG. 2 may be subjected to atomic and/or ion bombardment, such as plasma sputtering, preferably by Ar, N, etc.
  • atomic and/or ion bombardment such as plasma sputtering, preferably by Ar, N, etc.
  • the gate spacer is formed at least at its upper surface to be inclined such that the partially inclined surface is defined A space that tapers from top to bottom.
  • the height of the gate spacer 106 (in the case of a multi-layer configuration, the height of the multilayer gate spacer as a whole) may vary relatively little or almost unchanged. That is, atomic and/or ion bombardment can change the shape of the upper end face of the gate spacer 106 with less or substantially no removal of the upper end of the gate spacer 106 (in the case of a multi-layer configuration, the inner gate spacer The upper end portion may be removed, and the upper end portion of at least one or more of the outer layers is rarely or substantially removed, so that the overall height is almost constant, and the upper end surface is formed to be inclined).
  • the remaining gate stack (including the remaining sacrificial gate conductor layer 104 and sacrificial gate dielectric layer 102) may be further removed, as shown in FIG. 4, for example by selective etching such as RIE.
  • the space G defined by the gate spacer 106 (also referred to as "grid groove") is left inside the gate spacer 106.
  • the gate groove G has a shape which gradually increases from the bottom to the top in the upper portion thereof.
  • the present disclosure is not limited thereto.
  • the gate trench G may even taper from its top to the bottom (i.e., the surface of the substrate 100) over its entire height.
  • the dimensional change of the gate groove G is not limited to this gradual change. It will be understood by those skilled in the art that as long as the gate trench G is increased in its upper portion relative to the bottom portion, a true gate stack can be relatively easily filled therein.
  • the upper end surface of the gate groove G is not limited to the linear inclination shown in Fig. 4, but may include undulations due to atomic and/or ion bombardment, and may even be curved in a curved shape.
  • the gate stack can be filled in the gate trench G.
  • the gate dielectric layer 110 and the gate conductor layer 112 are sequentially formed by deposition.
  • the gate dielectric layer 110 may include a high-k gate dielectric such as Hf0 2 or the like having a thickness of about 0.5-3 nm;
  • the gate conductor layer 112 may include a metal gate conductor such as TiAl, TiN, or the like.
  • the metal gate conductor layer 112 is not limited to the single layer structure illustrated, and may include a multilayer structure. Since the gate trench G is increased in size at its upper portion, the filling of the gate stack therein can be made relatively easy.
  • portions of the gate dielectric layer 110 and the gate conductor layer 112 outside the gate trench G are removed, for example, by etch back, and thus a gate stack is formed.
  • the side wall can be used as a stopping point.
  • the present disclosure is not limited thereto.
  • the metal gate conductor layer 112 may be formed to be thin so that the gate trench G is not completely filled. Thereafter, a polysilicon or a metal layer or the like may be further formed on the metal gate conductor layer 112, for example, by deposition.
  • an interface layer may also be formed on the surface of the substrate 100 by deposition or thermal oxidation.
  • the interfacial layer may comprise an oxide (e.g., silicon oxide) having a thickness of between about 0.3 and 1.4 nm.
  • a high K gate dielectric layer can be formed on the interface layer.
  • the gate conductor layer 112 may be further etched back, as shown in FIG.
  • the height of the gate conductor layer 112 after etch back is about 10 nm to 50 nm.
  • a space in the gate trench G due to etch back is filled with a dielectric layer 114 (e.g., nitride) to cover the gate conductor layer 112.
  • dielectric layer 114 e.g., nitride
  • the advantage of this configuration in Figure 7 is that the process margin of the source/drain contact can be improved.
  • the contact portion 118 when the contact portion 118 is formed in the interlayer dielectric layer 108, the alignment requirements of the contact portion 118 with respect to the source/drain regions may be relatively loose due to the presence of the dielectric layer 114.
  • the contact 118 has been offset past the gate spacer 106. This offset is disadvantageous in the structure shown in FIG. Further, the contact portion 118 can be formed relatively large.
  • the semiconductor device may include a fin 1004 formed on a substrate 1000 and a fin 1004.
  • the gate stack is crossed (see Figure 15).
  • the gate stack may include a gate dielectric layer 1022 and a gate conductor layer 1024.
  • the semiconductor device can also include a gate spacer 1012 formed on a sidewall of the gate stack (in this example, the gate dielectric layer 1022).
  • the gate stack can be separated from the substrate via an isolation layer (see 1006 in Figure 13).
  • the gate spacer 1012 can be shaped such that its defined volume (eg, the volume inside it, in this example, specifically the volume occupied by the gate stack) is relatively far from the substrate at a distance from the substrate Increase.
  • the volume exhibits a bucket shape that is large and small in its upper portion.
  • the gate stack defines a channel region in the fin 1004.
  • Source/drain regions 1014 may be formed on the sides of the channel region in the fins 1004. Additionally, below the channel region, a PTS 1020 can be formed. In the example of Fig. 21, a device is formed in the well region 1000-1 formed in the substrate 1000.
  • the semiconductor device can be manufactured, for example, as follows.
  • a substrate 1000 is provided.
  • Substrate 100 can be a suitable substrate in a variety of forms, such as those described above in connection with FIG.
  • well region 1000-1 may be formed in substrate 1000.
  • the n-type well region can be formed by implanting an n-type impurity such as P or As in the substrate 1000
  • the p-type well region can be formed by implanting a p-type impurity such as B into the substrate 1000. If necessary, annealing can also be performed after the implantation.
  • a person skilled in the art can think of a plurality of ways to form an n-type well and a p-type well, which will not be described herein.
  • the substrate 1000 can be patterned to form a fin structure. For example, this can be done as follows. Specifically, a patterned photoresist 1002 is formed on the substrate 1000 as designed. Typically, photoresist 1002 is patterned into a series of parallel equally spaced lines. Then, as shown in FIG. 10, the substrate 1000 is etched, such as RIE, using the patterned photoresist 1002 as a mask to form a fin structure 1004. Here, etching of the substrate 1000 can be performed into the well region 1000-1. Thereafter, the photoresist 1002 can be removed.
  • the photoresist 1002 can be removed.
  • the shape of the trench (between the fin structures 1004) formed by etching is not necessarily the regular rectangular shape shown in FIG. 10, and may be, for example, a taper that gradually becomes smaller from top to bottom. Table shape.
  • the position and number of fin structures formed are not limited to the example shown in FIG.
  • the fin structure is not limited to being formed by directly patterning the substrate.
  • an additional semiconductor layer can be epitaxially grown on the substrate, and the additional semiconductor layer can be patterned to form a fin structure. If there is sufficient etch selectivity between the additional semiconductor layer and the substrate, then the finned junction When the composition is patterned, the pattern can be substantially stopped at the substrate, thereby achieving more precise control of the height of the fin structure.
  • the expression “forming a fin or fin structure on a substrate” includes forming a fin or fin structure on the substrate in any suitable manner
  • the expression “fin or fin structure formed on the substrate” “Includes any suitable fin or fin structure formed on the substrate in any suitable manner.
  • an isolation layer may be formed on the substrate.
  • a dielectric layer e.g., may include an oxide such as silicon oxide
  • the deposited dielectric layer is etched back to form an isolation layer 1006.
  • the deposited dielectric layer can completely cover the fin structure 1004 and the deposited dielectric can be planarized prior to etch back, such as CMP.
  • the spacer layer 1006 preferably slightly exposes the well region. That is, the top surface of the isolation layer 1006 is slightly lower than the top surface of the well region 1000-1 (the height difference between them is not shown in the drawing).
  • PTS 1020 is formed by ion implantation as indicated by the arrows in FIG.
  • a p-type impurity such as 8, BF 2 or In may be implanted;
  • an n-type impurity such as ⁇ 8 or ⁇ may be implanted. Ion implantation can be perpendicular to the surface of the substrate.
  • the parameters of the first ion implantation are controlled such that the PTS is formed in a portion of the fin structure 1004 below the surface of the isolation layer 1006 and has a desired doping concentration, for example, about 5E17-2E19 cm" 3 , and the doping concentration should be high.
  • the doping concentration of the well region 1000-1 in the substrate may be controlled due to the shape factor (elongated shape) of the fin structure 1004, a part of the dopant (ion or element) may be scattered from the exposed portion of the fin structure. This facilitates the formation of a steep doping profile in the depth direction. Annealing such as spike annealing, laser annealing, and/or rapid annealing can be performed to activate the implanted dopant. This PTS helps to reduce source and drain leakage.
  • a gate stack intersecting the fins may be formed on the isolation layer 1006.
  • this can be done as follows.
  • a sacrificial gate dielectric layer 1008 is formed, for example, by deposition.
  • the sacrificial gate dielectric layer 1008 can include an oxide having a thickness of between about 0.8 and 1.5 nm.
  • the sacrificial gate dielectric layer 1008 can also include portions that extend over the top surface of the isolation layer 1006.
  • the sacrificial gate conductor layer 1010 may include polysilicon.
  • the sacrificial gate conductor layer 1010 may fill a gap between the fins and may be subjected to a planarization process such as CMP.
  • the sacrificial gate conductor layer 1010 is patterned as shown in Fig. 14 (Fig. 13 corresponds to a cross-sectional view taken along line BB' in Fig. 14). In the example of Fig. 14, the sacrificial gate conductor layer 1010 is patterned into a strip shape that intersects the fin structure. According to another embodiment, the patterned sacrificial gate conductor layer 1010 can also be patterned to further pattern the sacrificial gate dielectric layer 1008.
  • a halo implant and a extension implant can be performed by sacrificing the gate conductor as a mask.
  • a gate spacer 1012 may be formed on the sidewall of the gate conductor layer 1010.
  • the gate spacers 1012 may be formed by depositing a nitride (e.g., silicon nitride) having a thickness of about 5 to 20 nm and then performing RIE on the nitride.
  • a nitride e.g., silicon nitride
  • RIE reactive ion etching
  • FIG. 16 is a cross-sectional view taken along line ⁇ 1 of Fig. 15, Fig. 16 (b) is a cross-sectional view taken along line B2B2' in Fig. 15, Fig. 16 (c) is along As shown in the cross-sectional view of the CC' line in Fig. 15, source/drain (S/D) implantation can be performed using the gate conductor and the side wall as a mask. Here, as shown by the arrow in Fig. 16 (b), an angular injection can be performed.
  • S/D source/drain
  • p-type impurities such as 8, BF 2 or In can be implanted; for n-type devices, n-type impurities such as As or subsequently can be implanted to activate the implanted ions to form source/drain District 1014.
  • n-type impurities such as As or subsequently can be implanted to activate the implanted ions to form source/drain District 1014.
  • FIG. 16(a) due to the presence of the gate stack, the intersection of the fin structure 1004 and the gate stack (the channel region will be formed therein) is substantially unaffected by the S/D implantation.
  • S / D implantation may compensate for PTS 1020.
  • beneath the source / drain region 1014 for example, reducing the dopant concentration is about 1020.
  • the PTS 1020 is located substantially below the channel region.
  • the compensated PTS below the source/drain regions 1014 is not shown in the figure. This compensation can improve device performance, especially the junction capacitance between the source/drain regions and the substrate.
  • an interlayer dielectric layer 1016 is formed, for example, by deposition.
  • Interlayer dielectric layer 1016 can include, for example, an oxide.
  • the interlayer dielectric layer 1016 is planarized. For example CMP. The CMP can stop at the gate spacers 1012 to expose the sacrificial gate stack.
  • the sacrificial gate stack (in this example, the sacrificial gate conductor layer 1010) may be partially etched back by selective etching such as RIE.
  • the etch back depth is about 10 nm to 60 nm.
  • an opening is formed inside the gate spacer 1012.
  • the upper surface of the structure shown in FIG. 2 may be subjected to atomic and/or ion bombardment, such as plasma sputtering, preferably with Ar, N, etc.
  • atomic and/or ion bombardment such as plasma sputtering, preferably with Ar, N, etc.
  • the gate spacer is formed to be inclined at least at the upper surface thereof such that the partially inclined surface defines a space which tapers from the top to the bottom.
  • the enlarged opening can be self-aligned to the remaining sacrificial gate stack.
  • the remaining gate stack (including the remaining sacrificial gate conductor layer 1010 and sacrificial gate dielectric layer 1008) may be further removed, as shown in FIG. 20, for example by selective etching such as RIE.
  • a space G also referred to as a "grid groove" defined by the gate spacer 1012 is left inside the gate spacer 1012.
  • the gate trench G is similar to the trench trench described above in connection with FIG.
  • a gate stack may be filled in the gate trench G, including a gate dielectric layer 1022 and a gate conductor layer 1024.
  • the gate conductor layer 112 may be further partially etched back and filled with a dielectric layer 1018 (e.g., nitride).
  • a dielectric layer 1018 e.g., nitride

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Abstract

提供了半导体器件及其制造方法。一示例方法包括：在衬底（100）上形成牺牲栅堆叠；在牺牲栅堆叠的侧壁上形成栅侧墙（106）；在衬底（100）上形成层间电介质层（108），并对其平坦化，以露出牺牲栅堆叠；部分地回蚀牺牲栅堆叠以形成开口；对所得的开口进行扩大，以使开口呈现从靠近衬底（100）一侧向远离衬底（100）一侧逐渐增大的形状；以及去除剩余的牺牲栅堆叠，并在栅侧墙（106）内侧形成栅堆叠。

Description

半导体器件及其制造方法
本申请要求了 2013年 8月 13 日提交的、 申请号为 201310351422.9、发明 名称为 "半导体器件及其制造方法" 的中国专利申请的优先权， 其全部内容通 过引用结合在本申请中。 技术领域
本公开涉及半导体领域， 更具体地， 涉及一种半导体器件及其制造方法。
背景技术
随着半导体器件的不断小型化， 逐渐釆用高 K栅介质 /金属栅配置代替传 统的 Si02/多晶硅栅配置。 与之相适应， 后栅（gate last )工艺正逐渐替代先栅 ( gate first ) 工艺。
在后栅工艺中， 先利用牺牲栅堆叠来进行器件制造处理。 随后， 去除牺牲 栅， 并代之以真正的栅堆叠。 然而， 牺牲栅去除之后留下的空间正变得越来越 小， 因此要在其中填充真正的栅堆叠变得越来越困难。
发明内容
本公开的目的至少部分地在于提供一种半导体器件及其制造方法，以改善 栅堆叠的填充。
根据本公开的一个方面，提供了一种制造半导体器件的方法。该方法可以 包括： 在衬底上形成牺牲栅堆叠； 在牺牲栅堆叠的侧壁上形成栅侧墙； 在衬底 上形成层间电介质层， 并对其平坦化， 以露出牺牲栅堆叠； 部分地回蚀牺牲栅 堆叠以形成开口； 对所得的开口进行扩大， 以使开口呈现从靠近衬底一侧向远 离衬底一侧逐渐增大的形状； 以及去除剩余的牺牲栅堆叠， 并在栅侧墙内侧形 成栅堆叠。
根据本公开的另一方面，提供了一种半导体器件。该半导体器件可以包括： 衬底； 在衬底上形成的栅堆叠以及位于栅堆叠侧壁上的栅侧墙， 其中， 栅侧墙 所限定的体积至少在其远离衬底一侧的一部分中呈现从靠近衬底一侧向远离 衬底一侧逐渐增大的形状。
根据本公开的实施例，在去除牺牲栅堆叠之后， 可以通过例如原子或离子 轰击， 来使栅侧墙内侧的空间至少在其上部扩大， 特别是呈现从下向上逐渐增 大的形状。 这有助于改善随后栅堆叠向该空间中的填充。 附图说明
通过以下参照附图对本公开实施例的描述， 本公开的上述以及其他目的、 特征和优点将更为清楚， 在附图中：
图 1-5是示出了根据本公开实施例的制造半导体器件流程的示意图； 图 6-8是示出了根据本公开另一实施例的制造半导体器件流程的示意图； 图 9-21是示出了根据本公开再一实施例的制造半导体器件流程的示意图； 以及
图 22是示出了根据本公开又一实施例的半导体器件的示意图。 具体实施方式
以下， 将参照附图来描述本公开的实施例。 但是应该理解， 这些描述只是 示例性的， 而并非要限制本公开的范围。 此外， 在以下说明中， 省略了对公知 结构和技术的描述， 以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比 例绘制的， 其中为了清楚表达的目的， 放大了某些细节， 并且可能省略了某些 细节。 图中所示出的各种区域、 层的形状以及它们之间的相对大小、位置关系 仅是示例性的， 实际中可能由于制造公差或技术限制而有所偏差， 并且本领域 技术人员根据实际所需可以另外设计具有不同形状、 大小、 相对位置的区域 / 层。
在本公开的上下文中， 当将一层 /元件称作位于另一层 /元件 "上" 时， 该 层 /元件可以直接位于该另一层 /元件上， 或者它们之间可以存在居中层 /元件。 另外，如果在一种朝向中一层 /元件位于另一层 /元件"上"，那么当调转朝向时， 该层 /元件可以位于该另一层 /元件 "下"。
根据本公开的实施例，提供了一种半导体器件。该半导体器件可以包括在 衬底上形成的栅堆叠以及位于栅堆叠侧壁上的栅侧墙。栅侧墙所限定的体积在 其远离衬底处相对于其靠近衬底处扩大。因此，这种形式的栅侧墙（在其内侧） 限定了上大下小的空间 （在此， 将远离衬底一侧称作 "上"， 将靠近衬底一侧 称作 "下"；)。 从而， 栅堆叠相对易于填充到这样的空间中。
根据一示例， 栅侧墙所限定的体积至少在其位于远离衬底一侧（例如， 上 侧）的一部分中， 可以从靠近衬底一侧（例如， 下侧）向着远离衬底一侧（例 如， 上侧）尺寸逐渐增大， 从而呈现例如上大下小的斗状。 这样的栅侧墙易于 制造。
栅堆叠可以包括各种合适的配置。例如，栅堆叠可以包括栅介质层（例如， 高 K栅介质层）和栅导体层（例如， 金属栅导体层） 的叠层， 在它们之间还 可以形成功函数调节层。 栅堆叠可以用于平面型器件如 MOSFET。 具体地， 栅堆叠可以形成于衬底中的有源区上，从而在有源区中限定沟道区。在沟道区 两侧的有源区中， 可以形成源区和漏区。 另外， 栅堆叠可以用于立体型器件如 FinFETo 具体地， 栅堆叠可以与衬底上形成的鰭相交， 并因此在鰭中限定沟 道区。 在沟道区两侧的鰭两端部中， 可以形成源区和漏区。 为防止源漏区之间 经由鰭底部的泄漏，该半导体器件还可以包括在鰭与栅堆叠相交部分（具体地， 沟道区） 下方的区域中形成的穿通阻挡部 （PTS )。
根据一有利示例， 栅堆叠没有填充满栅侧墙所限定的体积。 例如， 栅导体 层可以相对于栅侧墙远离衬底一侧的端部（例如， 上端部） IHJ进。 IHJ进的栅导 体层上可以覆盖有电介质层。 这种情况下， 可以改善源 /漏区接触部的工艺裕 度。
根据本公开的其他实施例，提供了一种制造半导体器件的方法， 该方法尤 其适用于后栅工艺。 根据后栅工艺， 可以在衬底上形成牺牲栅堆叠， 然后可以 利用牺牲栅堆叠进行器件制造（例如， 形成源区和漏区）。 随后， 可以去除牺 牲栅堆叠，从而在栅侧墙内侧留下栅槽。代替直接向栅槽中填充真正的栅堆叠， 可以对栅侧墙进行处理， 使栅槽在其上部增大。 这样， 可以相对容易地向栅槽 中填充栅堆叠。 为了在对栅侧墙处理期间保护有源区或鰭，在对栅侧墙处理之 前， 牺牲栅堆叠可以部分地去除， 而在对栅侧墙处理之后， 可以去除剩余的牺 牲栅堆叠。 对栅侧墙的处理例如可以通过原子和 /或离子轰击来进行。 根据一 有利示例， 可以釆用等离子体溅射。
本公开可以各种形式呈现， 以下将描述其中一些示例。
图 5是示出了根据本公开实施例的半导体器件的示意图。如图 5所示， 该 半导体器件可以包括在衬底 100 上形成的栅堆叠。 栅堆叠可以包括栅介质层 110和栅导体层 112。 此外， 该半导体器件还可以包括在栅堆叠 （该示例中， 栅介质层 110 )侧壁上形成的栅侧墙 106。 栅侧墙 106可以被成形为使得其所 限定的体积（例如， 其内侧的体积， 在该示例中， 具体地是栅堆叠所占据的体 积）在远离衬底处相对于靠近衬底处增大。 在该示例中， 所述体积在其上部呈 现上大下小的斗状。
另外， 图 5中还示出了衬底 100上形成的层间电介质层 108。 该层间电介 质层 108的上表面可以与栅堆叠的上表面齐平。
该半导体器件例如可以如下来制造。
具体地， 如图 1所示， 提供衬底 100。 衬底 100可以是各种形式的合适衬 底，例如体半导体衬底如 Si、 Ge等，化合物半导体衬底如 SiGe、 GaAs、 GaSb、 AlAs、 InAs、 InP、 GaN、 SiC、 InGaAs, InSb、 InGaSb 等， 绝缘体上半导体 衬底（SOI )等。 在此， 以体硅衬底及硅系材料为例进行描述。 但是需要指出 的是， 本公开不限于此。
在衬底 100上可以形成牺牲栅堆叠。 例如， 可以通过淀积， 依次形成牺牲 栅介质层 102和牺牲栅导体层 104。牺牲栅介质层 102可以包括氧化物（例如， Si02 ), 牺牲栅导体层 104可以包括多晶硅。 之后， 例如通过光刻， 可以将牺 牲栅介质层 102和牺牲栅导体层 104构图为牺牲栅堆叠。可以牺牲栅堆叠为掩 模， 进行晕圈 （halo )和延伸区 （extension ) 注入。 然后， 可以在栅堆叠的侧 壁上， 形成栅侧墙 106。 例如， 栅侧墙 106可以通过在衬底上共形淀积一层氮 化物 （例如氮化硅）， 并对该氮化物层进行选择性刻蚀如反应离子刻蚀 （RIE ) 来形成。 随后， 可以栅堆叠和栅侧墙 106为掩模， 进行源 /漏注入。 还可以进 行退火处理， 以激活注入的离子， 并形成源 /漏区 （未示出）。
在图 1中， 示出了单层的栅侧墙 106。 但是， 本公开不限于此。 例如， 栅 侧墙 106可以包括两层或更多层的配置。
然后， 可以所得到的结构上形成层间电介质层 108。 例如， 可以通过淀积 氧化物， 然后进行平坦化如化学机械抛光（CMP )来形成层间电介质层 108。 在平坦化时， 可以栅侧墙 106为停止点， 从而可以露出牺牲栅堆叠。
随后， 如图 2所示， 可以通过选择性刻蚀如 RIE, 部分地回蚀牺牲栅堆叠 (在该示例中， 牺牲栅导体层 104 )。 回蚀深度例如为约 10nm-60nm。 于是， 在栅侧墙 106内侧形成开口。
接下来， 如图 3所示 （见其中示出的箭头）， 可以对图 2所示结构的上表 面进行原子和 /或离子轰击， 例如等离子体溅射， 优选地用 Ar、 N等等离子轰 击， 以将开口扩大。 由于图 2所示结构的形貌（中间凹进）以及由此造成的对 于原子和 /或离子轰击的负载条件， 栅侧墙至少在其上部的表面形成为倾斜， 使得该部分倾斜的表面限定出从上向下渐缩（tapered )的空间。 当进行基本上 竖直的轰击时， 扩大的开口可以自对准于剩余的牺牲栅堆叠。 因此， 较非自对 准扩大的开口方法而言， 可以节省器件所占面积并减少制造成本。
在此， 栅侧墙 106的高度（在多层配置的情况下， 是指多层栅侧墙作为整 体的高度）可以变化相对较小或几乎没有改变。 即， 原子和 /或离子轰击可以 改变栅侧墙 106上端面的形状，而较少地或基本上没有去除栅侧墙 106的上端 部（在多层配置的情况下， 内侧的栅侧墙的上端部可能被去除， 而外侧的至少 一层或多层的上端部极少地或基本上没有被去除， 从而整体上高度几乎不变， 且上端面形成为倾斜）。
之后， 可以如图 4所示， 例如通过选择性刻蚀如 RIE, 进一步去除剩余的 栅堆叠 （包括剩余的牺牲栅导体层 104和牺牲栅介质层 102 )。 于是， 就在栅 侧墙 106内侧留下了由栅侧墙 106限定的空间 G (也称作 "栅槽" )„
在图 4的示例中， 栅槽 G在其上部呈现从下向上逐渐增大的形状。 但是， 本公开不限于此。 例如， 如果栅侧墙允许的话， 则栅槽 G甚至可以在其整个 高度上从其顶部一直到其底部（即， 衬底 100的表面）呈渐缩状。 另外， 栅槽 G 的尺寸变化也不限于这种逐渐变化。 本领域技术人员应理解， 只要栅槽 G 在其上部相对于底部增大，就可以相对容易地向其中填充真正的栅堆叠。此外， 栅槽 G的上端面不限于图 4中所示的直线状倾斜， 而是可以包括由于原子和 / 或离子轰击造成的起伏， 甚至可以呈曲线状倾斜。
随后， 如图 5所示， 可以在栅槽 G中填充栅堆叠。 例如， 可以在图 4所 示的结构上， 通过淀积， 依次形成栅介质层 110和栅导体层 112。 例如， 栅介 质层 110可以包括高 K栅介质如 Hf02等， 厚度为约 0.5-3nm; 栅导体层 112 可以包括金属栅导体如 TiAl、 TiN等。 另外， 金属栅导体层 112不限于图示的 单层结构， 也可以包括多层结构。 由于栅槽 G在其上部尺寸增大， 从而栅堆 叠向其中的填充可以变得相对容易。
接下来， 例如通过回蚀， 去除栅介质层 110和栅导体层 112在栅槽 G之 外的部分， 并因此形成栅堆叠。 回蚀时， 可以侧墙为停止点。
在图 5的示例中， 示出了栅介质层 110和栅导体层 112将栅槽 G完全填 满的示例。但是，本公开不限于此。例如，金属栅导体层 112可以形成为较薄， 使得栅槽 G并未完全填满。 之后， 还可以在金属栅导体层 112之上例如通过 淀积进一步形成多晶硅或金属层等。
根据一示例， 还可以在衬底 100 的表面上通过淀积或热氧化形成界面层 (未示出）。 界面层可以包括氧化物 （例如氧化硅）， 厚度为约 0.3-1.4nm。 高 K栅介质层可以形成在该界面层上。
这里需要指出的是，在以上描述中，对于后栅工艺本身的处理和参数没有 进行详细描述。 本领域技术人员可以设想多种合适的处理和参数。
根据本公开的另一实施例，在得到图 5所示的结构之后，还可以进一步部 分地回蚀栅导体层 112, 如图 6所示。 例如， 回蚀后栅导体层 112的高度为约 10nm-50nm。 然后， 可以如图 7所示， 栅槽 G内由于回蚀产生的空间中填充 电介质层 114 (例如， 氮化物）， 以覆盖栅导体层 112。 这里需要指出的是， 尽 管图 7中将电介质层 114示出为位于栅槽 G内， 但是其也可以延伸到删除 G 之外从而从层间电介质层 108上延伸。
图 7 中这种结构的优点在于可以改善源 /漏区接触部的工艺裕度。 例如， 如图 8所示， 当在层间电介质层 108中形成接触部 118时， 由于电介质层 114 的存在， 接触部 118相对于源 /漏区的对准要求可以相对宽松。 例如， 在图 8 的示例中， 接触部 118已经偏移到经过栅侧墙 106。 而这种偏移在图 5所示的 结构中是不利的。 此外， 接触部 118可以形成的相对较大。
图 21 是示出了根据本公开另一实施例的半导体器件的示意图。 如图 21 所示， 该半导体器件可以包括在衬底 1000上形成的鰭 1004以及与鰭 1004相 交的栅堆叠 （参见图 15 )。 栅堆叠可以包括栅介质层 1022和栅导体层 1024。 此外， 该半导体器件还可以包括在栅堆叠 （该示例中， 栅介质层 1022 )侧壁 上形成的栅侧墙 1012。 栅堆叠可以经由隔离层（参见图 13中的 1006 )与衬底 隔开。 同样地， 栅侧墙 1012可以被成形为使得其所限定的体积（例如， 其内 侧的体积， 在该示例中， 具体地是栅堆叠所占据的体积）在远离衬底处相对于 靠近衬底处增大。 在该示例中， 所述体积在其上部呈现上大下小的斗状。
栅堆叠在鰭 1004中限定了沟道区。在鰭 1004中在沟道区两侧可以形成源 /漏区 1014。 另外， 在沟道区下方， 可以形成 PTS 1020。 在图 21的示例中， 器件形成于衬底 1000中形成的阱区 1000-1中。
该半导体器件例如可以如下来制造。
具体地， 如图 9所示， 提供衬底 1000。 衬底 100可以是各种形式的合适 衬底， 如以上结合图 1描述的那些衬底。 根据本公开的一些示例， 可以在衬底 1000中形成阱区 1000-1。 例如， 对于 p型器件， 可以形成 n型阱区； 而对于 n 型器件， 可以形成 p型阱区。 例如， n型阱区可以通过在衬底 1000中注入 n 型杂质如 P或 As来形成， p型阱区可以通过在衬底 1000中注入 p型杂质如 B 来形成。 如果需要， 在注入之后还可以进行退火。 本领域技术人员能够想到多 种方式来形成 n型阱、 p型阱， 在此不再赘述。
接下来， 可以对衬底 1000进行构图， 以形成鰭状结构。 例如， 这可以如 下进行。 具体地， 在衬底 1000上按设计形成构图的光刻胶 1002。 通常， 光刻 胶 1002被构图为一系列平行的等间距线条。 然后， 如图 10所示， 以构图的光 刻胶 1002为掩模， 对衬底 1000进行刻蚀如 RIE, 从而形成鰭状结构 1004。 在此， 对衬底 1000的刻蚀可以进行到阱区 1000-1中。 之后， 可以去除光刻胶 1002。
这里需要指出的是， 通过刻蚀所形成的 （鰭状结构 1004之间的） 沟槽的 形状不一定是图 10中所示的规则矩形形状， 可以是例如从上到下逐渐变小的 锥台形。 另外， 所形成的鰭状结构的位置和数目不限于图 10所示的示例。
另外， 鰭状结构不限于通过直接对衬底进行构图来形成。 例如， 可以在衬 底上外延生长另外的半导体层， 对该另外的半导体层进行构图来形成鰭状结 构。如果该另外的半导体层与衬底之间具有足够的刻蚀选择性， 则在对鰭状结 构进行构图时， 可以使构图基本上停止于衬底，从而实现对鰭状结构高度的较 精确控制。
因此， 在本公开中， 表述 "在衬底上形成鰭或鰭状结构" 包括以任何适当 的方式在衬底上形成鰭或鰭状结构， 表述 "在衬底上形成的鰭或鰭状结构" 包 括以任何适当的方式在衬底上形成的任何适当鰭或鰭状结构。
在通过上述处理形成鰭状结构之后， 可以在衬底上形成隔离层。 例如， 如 图 11所示， 可以在衬底上例如通过淀积形成电介质层 （例如， 可以包括氧化 物如氧化硅）， 然后对淀积的电介质层进行回蚀， 来形成隔离层 1006。 通常， 淀积的电介质层可以完全覆盖鰭状结构 1004, 并且在回蚀之前可以对淀积的 电介质进行平坦化， 如 CMP。 在衬底 1000中形成阱区 1000-1的情况下， 隔 离层 1006优选稍稍露出阱区。 即， 隔离层 1006的顶面略低于阱区 1000-1的 顶面 （附图中没有示出它们之间的高度差）。
这里需要指出的是， 这种隔离层并不是必须的， 特别是在衬底为 SOI衬 底的情况下。
为改善器件性能， 特别是降低源漏泄漏， 根据本公开的一示例， 如图 12 中的箭头所示， 通过离子注入来形成 PTS 1020。 例如， 对于 n型器件而言， 可以注入 p型杂质， 如：8、 BF2或 In; 对于 p型器件， 可以注入 n型杂质， 如 八8或卩。 离子注入可以垂直于衬底表面。控制第一离子注入的参数，使得 PTS 形成于鰭状结构 1004位于隔离层 1006表面之下的部分中，并且具有期望的掺 杂浓度， 例如约 5E17-2E19 cm"3, 并且掺杂浓度应高于衬底中阱区 1000-1的 掺杂浓度。 应当注意， 由于鰭状结构 1004的形状因子（细长形 ), 一部分掺杂 剂（离子或元素）可能从鰭状结构的露出部分散射出去， 从而有利于在深度方 向上形成陡峭的掺杂分布。 可以进行退火如尖峰退火、 激光退火和 /或快速退 火， 以激活注入的掺杂剂。 这种 PTS有助于减小源漏泄漏。
随后， 可以在隔离层 1006上形成与鰭相交的栅堆叠。 例如， 这可以如下 进行。 具体地， 如图 13所示， 例如通过淀积， 形成牺牲栅介质层 1008。 例如， 牺牲栅介质层 1008可以包括氧化物， 厚度为约 0.8-1.5nm。 在图 13所示的示 例中， 仅示出了 " Π " 形的牺牲栅介质层 1008。 但是， 牺牲栅介质层 1008也 可以包括在隔离层 1006的顶面上延伸的部分。 然后， 例如通过淀积， 形成牺 牲栅导体层 1010。 例如， 牺牲栅导体层 1010可以包括多晶硅。 牺牲栅导体层 1010可以填充鰭之间的间隙， 并可以进行平坦化处理例如 CMP。
如图 14 (图 13对应于沿图 14中 BB'线的截面图 )所示， 对牺牲栅导体层 1010进行构图。 在图 14的示例中， 牺牲栅导体层 1010被构图为与鰭状结构 相交的条形。 根据另一实施例， 还可以构图后的牺牲栅导体层 1010为掩模， 进一步对牺牲栅介质层 1008进行构图。
在形成构图的牺牲栅导体之后， 例如可以牺牲栅导体为掩模， 进行晕圈 ( halo ) 注入和延 4申区 ( extension ) 注入。
接下来， 如图 15所示， 可以在栅导体层 1010的侧壁上形成栅侧墙 1012。 例如， 可以通过淀积形成厚度约为 5-20nm 的氮化物 （如氮化硅）， 然后对氮 化物进行 RIE, 来形成栅侧墙 1012。 本领域技术人员知道多种方式来形成这 种侧墙， 在此不再赘述。 在鰭之间的沟槽为从上到下逐渐变小的锥台形时（由 于刻蚀的特性，通常为这样的情况），栅侧墙 1012基本上不会形成于鰭的侧壁 上。
在形成侧墙之后， 如图 16 (图 16 ( a )是沿图 15中 Β1ΒΓ线的截面图， 图 16 ( b )是沿图 15中 B2B2'线的截面图， 图 16 ( c )是沿图 15中 CC'线的截 面图 )所示， 可以栅导体及侧墙为掩模， 进行源 /漏（S/D )注入。 在此， 如图 16 ( b ) 中的箭头所示， 可以进行倾斜（angular ) 注入。 对于 p型器件， 可以 注入 p型杂质， 如：8、 BF2或 In; 对于 n型器件， 可以注入 n型杂质， 如 As 或 随后， 可以通过退火， 激活注入的离子， 以形成源 /漏区 1014。 如图 16 ( a )所示， 由于栅堆叠的存在， 鰭状结构 1004与栅堆叠相交部分（沟道区将 在其中形成）基本上不会受到 S/D注入的影响。
由于 S/D注入与 PTS的杂质类型相反， S/D注入可以对源 /漏区 1014下方 的 PTS 1020进行补偿， 例如将 PTS 1020中的掺杂剂浓度降低到约 5E16-1E19 cm_3。 从而， PTS 1020大体上位于沟道区下方。 对于源 /漏区 1014下方经补偿 后的 PTS, 在图中没有示出。 这种补偿可以改善器件性能， 特别是降低源 /漏 区与衬底之间的结电容。
随后， 如图 17所示， 例如通过淀积， 形成层间电介质层 1016。 层间电介 质层 1016例如可以包括氧化物。 随后，对层间电介质层 1016进行平坦化处理 例如 CMP。 该 CMP可以停止于栅侧墙 1012, 从而露出牺牲栅堆叠。
接着， 如图 18所示， 可以通过选择性刻蚀如 RIE, 部分地回蚀牺牲栅堆 叠（在该示例中， 牺牲栅导体层 1010 )。 例如， 回蚀深度为约 10nm-60nm。 于 是， 在栅侧墙 1012内侧形成开口。
接下来， 如图 11所示（见其中示出的箭头）， 可以对图 2所示结构的上表 面进行原子和 /或离子轰击， 例如等离子体溅射， 优选地用 Ar、 N等等离子轰 击， 以将开口扩大。 参见以上结合图 3的描述， 栅侧墙至少在其上部的表面形 成为倾斜，使得该部分倾斜的表面限定出从上向下渐缩的空间。 当进行基本上 竖直的轰击时， 扩大的开口可以自对准于剩余的牺牲栅堆叠。
之后， 可以如图 20所示， 例如通过选择性刻蚀如 RIE, 进一步去除剩余 的栅堆叠 （包括剩余的牺牲栅导体层 1010和牺牲栅介质层 1008 )。 于是， 就 在栅侧墙 1012内侧留下了由栅侧墙 1012限定的空间 G (也称作 "栅槽" )。 该 栅槽 G与以上结合图 4描述的栅槽类似。
随后， 如图 21所示， 可以在栅槽 G中填充栅堆叠， 包括栅介质层 1022 和栅导体层 1024。 对此， 可以参照以上结合图 5的详细描述。
根据本公开的另一示例， 如图 22所示， 可以进一步部分地回蚀栅导体层 112, 并在其上部填充电介质层 1018 (例如， 氮化物）。 对此， 可以参照以上 结合图 6和 7的详细描述。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说 明。 但是本领域技术人员应当理解， 可以通过各种技术手段， 来形成所需形状 的层、 区域等。 另外， 为了形成同一结构， 本领域技术人员还可以设计出与以 上描述的方法并不完全相同的方法。 另外， 尽管在以上分别描述了各实施例， 但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是， 这些实施例仅仅是为了说明的 目的， 而并非为了限制本公开的范围。 本公开的范围由所附权利要求及其等价 物限定。 不脱离本公开的范围， 本领域技术人员可以做出多种替代和修改， 这 些替代和修改都应落在本公开的范围之内。

Claims

权 利 要 求 书
1. 一种制造半导体器件的方法， 包括：
在衬底上形成牺牲栅堆叠；
在牺牲栅堆叠的侧壁上形成栅侧墙；
在衬底上形成层间电介质层， 并对其平坦化， 以露出牺牲栅堆叠； 部分地回蚀牺牲栅堆叠以形成开口；
对所得的开口进行扩大，以使开口呈现从靠近衬底一侧向远离衬底一侧逐 渐增大的形状； 以及
去除剩余的牺牲栅堆叠， 并在栅侧墙内侧形成栅堆叠。
2. 根据权利要求 1所述的方法， 其中， 进行扩大包括： 进行原子和 /或离 子轰击。
3. 根据权利要求 2所述的方法， 其中， 原子和 /或离子轰击包括： 等离子 体溅射。
4. 根据权利要求 1所述的方法， 其中， 扩大后的开口自对准于剩余的牺 牲栅堆叠。
5. 根据权利要求 1所述的方法， 其中， 栅堆叠包括栅介质层和栅导体层， 该方法还包括：
部分地回蚀栅导体层；
在栅导体层上形成电介质层， 以覆盖回蚀后的栅导体层。
6. 一种半导体器件， 包括：
衬底；
在衬底上形成的栅堆叠以及位于栅堆叠侧壁上的栅侧墙，
其中，栅侧墙所限定的体积至少在其远离衬底一侧的一部分中呈现从靠近 衬底一侧向远离衬底一侧逐渐增大的形状。
7. 根据权利要求 6所述的半导体器件， 其中， 栅堆叠包括栅介质层和栅 导体层， 其中栅导体层相对于栅侧墙远离衬底一侧的端部凹进， 且该半导体器 件还包括覆盖栅导体层的电介质层。
8. 根据权利要求 6所述的半导体器件， 还包括： 在衬底上形成的鰭， 其中栅堆叠与鰭相交。
9. 根据权利要求 8所述的半导体器件， 还包括：
在鰭与栅堆叠相交的部分下方的区域中形成的穿通阻挡部。
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