CN1832142A - 制作用于cmos器件的自对准双应力衬里的方法和结构 - Google Patents
制作用于cmos器件的自对准双应力衬里的方法和结构 Download PDFInfo
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Abstract
一种制作用于CMOS器件的自对准双应力衬里的方法,该方法包括:在第一极性类型的器件和第二极性类型的器件上方制作第一类型的应力层,以及在第一类型的氮化物层上方制作牺牲层。在第二极性类型的器件上方的部分第一类型的应力层和牺牲层被图案化和去除。在第二极性类型的器件上方和在第一极性类型的器件上牺牲层的剩余部分上方制作第二类型的应力层,使得第二类型的应力层被制作成在水平表面上方比在侧壁表面上方厚度更大。去除侧壁表面上的部分第二类型的应力衬里,以及去除第一极性类型的器件上方的部分第二类型的应力衬里。
Description
技术领域
本发明一般地涉及半导体器件处理技术,并且更具体地涉及通过制作自对准双应力衬里(SDSL)而改善CMOS器件可靠性的方法和结构。
背景技术
在金属氧化物半导体场效应晶体管(MOSFET)器件中的热载流子效应由接近源/漏扩散区的沟道端部处的高电场引起。更具体地,在经过高场区域时要求大能量的电子,可以由于例如碰撞电离而产生电子空穴对,从而通过经由栅氧化物向栅极材料注入热载流子而导致高的栅极漏电和早期栅氧化物击穿。作为进一步的结果,在栅介质中也存在着净的负电荷密度。被俘获的电荷随时间累积,导致NMOS晶体管中的正阈值漂移,或PMOS晶体管中的负阈值漂移。
由于热电子比热空穴更容易迁移,因此热载流子效应在NMOS晶体管中比在PMOS晶体管中导致更大的阈值倾斜(threshold skew)。虽然如此,如果其有效沟道长度(Leff)小于例如0.8微米(μm),PMOS晶体管仍将经历负阈值倾斜。今天的标准薄栅氧化物(例如小于1.5纳米)趋向于对热载流子退化较不敏感,因为热载流子可以容易地通过薄栅氧化物隧穿。另一方面,较厚的栅氧化物器件(例如大于1.5纳米)更易受热载流子退化影响,因为热载流子趋向于随时间在氧化物中累积。因而,对于专用于诸如输入/输出电路的集成电路的某些应用,在单个芯片上可以有一些器件相对于该芯片上的其它器件形成有较厚的栅氧化物(例如逻辑或模拟电路晶体管)。
已知减少热载流子退化效应的方法包括向栅氧化物中添加诸如氮、氟和氯的杂质。然而,由于杂质(如氮)趋向于在薄膜的表面局域化,添加杂质对较厚的栅氧化物效果比较不明显。而且,对栅氧化物的直接渗氮也可能伴随着不希望的效应,如电子迁移率的退化。
用于改善由热载流子效应引起的器件寿命的已经公开的另一种技术是使用氘退火。通过由氘置换标准界面钝化退火步骤中的氢,NFET器件的寿命可以改善至大约10-100倍。然而,必须在足够高的温度(例如500℃以上)才能有效进行氘退火,这可能引起导致器件退化的掺杂剂去激活。关于氘退火的附加信息可以在Thomas G.Ference等人的公开文献“The Combined Effects of DeuteriumAnneals and Deuterated Barrier-Nitride Processing on Hot-ElectronDegradation in MOSFET′s”,IEEE Transactions on Electron Devices,Vo1.46,No.4,1999年4月,第747-753页中找到。然而,再次地,该技术通常也应用到较薄的栅氧化物。
近来,已经引入了双衬里技术,以在P型MOS器件中提供相对于N型MOS器件不同的应力。例如,在CMOS器件的PFETs上方形成第一类型的氮化物衬里,而在CMOS器件的NFETs上方形成第二类型的氮化物衬里。更具体地,已经发现在PFET沟道中的压应力的应用改善其中的载流子迁移率,而NFET沟道中的张应力的应用改善其中的载流子迁移率。因而PFET器件上方的第一类型氮化物衬里按照实现压应力的方式而形成,而PFET器件上方的第一类型氮化物衬里按实现压应力的方式形成。
对于这种采用双衬里的CMOS器件,常规的方法是采用独立的光刻图案化步骤形成两种不同的氮化物。也即,例如在PFET和NFET器件上方形成第一类型的氮化物衬里,随后在NFET器件上方的第一类型的氮化物衬里的一部分被图案化和去除。在可选的氧化物层形成之后,在两个区域上方形成第二类型的氮化物衬里,使用第二图案化步骤随后去除PFET器件上方的第二类型氮化物衬里部分。不幸的是,由于与光刻层面对先前层面的对准相关的固有的不精确性,形成两个衬里会导致二者之间的间隙或不重叠。具体地,由于在蚀刻期间,不重叠/间隙区域中的硅化物将过蚀刻,因此这种间隙对于随后蚀刻用于金属接触通道的孔将引起问题。进而,这将增加硅化物的表面电阻。
另一方面,两个衬里也可以制作成一个衬里重叠另一个衬里的形式。事实上,用于两个独立的图案化步骤的模版(reticle)被典型地设计成保证重叠,使得在两个衬里材料之间没有间隙。然而,使某些区域具有重叠的氮化物衬里产生其它的随后处理的问题,这些问题由诸如可靠性和布图无效的问题而导致。例如,用于随后的接触形成的反应离子蚀刻(RIE)工艺可能不得不容许在电路的一些区域中的单一厚度的衬里,同时也容许在界面区域中的双厚度(重叠)衬里。而且如果这种重叠区域被排除在接触形成之外,则产生可用布图面积和关键尺寸(CD)公差方面的限制。重叠也将在随后蚀刻用于金属接触通道的孔期间引起问题,因为在蚀刻中,除了重叠区域下方的硅化物,所有的硅化物将被过蚀刻(over etched)。这将增加表面电阻和器件的结漏电。
因此,期望能够以不导致不同衬里类型之间的间隙和/或其重叠的自对准方式实现双衬里CMOS器件的制作。
发明内容
前面讨论的现有技术的缺点和不足可以通过制作用于互补金属氧化物半导体(CMOS)器件的自对准双应力衬里的方法来克服或减轻。在示例性的实施方式中,该方法包括在第一极性类型的器件和第二极性类型的器件上方制作第一类型的应力层,第二极性类型的器件上方的应力层和牺牲层被图案化和去除。在第二极性类型的器件上方,并且在第一极性类型的器件上方的牺牲层的剩余部分上方,制作第二类型的应力层,使得第二类型的应力层被制作成在水平表面上方比侧壁表面上方的厚度更大。去除侧壁表面上的第二类型的应力衬里部分,并去除第一极性类型的器件上方的第二类型的应力衬里部分。
在另一个实施方式中,制作用于半导体器件的自对准双材料衬里的方法包括在衬底上方制作第一类型的层,并且在第一类型的层上方制作牺牲层。在衬底的第一区域上方,一部分第一类型的层和牺牲层被图案化和去除。在衬底的第一区域上方,并且在衬底第二区域上方的牺牲层的剩余部分上方,制作第二类型的层,使得第二类型的层被制作成在水平表面上方比在侧壁表面上方的厚度更大。去除侧壁表面上第二类型的衬里部分和衬底的第二区域上方的第二类型的氮化物衬里部分。
在仍另一个实施方式中,互补金属氧化物半导体(CMOS)器件包括在第一极性类型的器件上方形成的第一类型的应力层,和在第二类型的器件上方形成的第二类型的应力层,第二类型的应力层与第一类型的应力层自对准。在与第一和所述第二极性类型的器件中的另一个自对准期间,第一和所述第二极性类型的器件之一具有至少一部分与之相关的侧壁隔层材料被去除。
附图说明
参照示例性的附图,其中在数个图中类似的要素以类似的方式标数。
图1是适合于按照本发明的实施方式使用的、在其上形成有一对互补金属氧化物半导体(CMOS)器件的半导体衬底的截面图;
图2(a)至2(k)说明按照本发明的第一实施方式制作用于CMOS器件的自对准双氮化硅衬里的示例性工艺流程;
图3(a)至3(j)说明按照本发明的第二实施方式制作用于CMOS器件的自对准双氮化硅衬里的示例性工艺流程。
具体实施方式
本文公开了一种通过制作自对准双氮化硅衬里改善CMOS器件可靠性的方法和结构。简言之,本文公开的实施方式导致两种类型的氮化物衬里之间重叠区域的消除,同时仍然保持着横跨器件的连续衬里作为有效的扩散阻挡。两个氮化物衬里结合在二者之间陡峭限定的自对准界面处,从而形成连续和均匀的单一氮化物层,不至于使随后的接触蚀刻工艺复杂化和/或导致附加限制的基本规则(groundrules)。本文描述的实施方式的原理也可以被一般地应用于期望从两个独立的层材料形成均匀的单一层材料的情形。
开始参照图1,其中示出了具有在其上形成、并被浅沟槽隔离105彼此隔开的一对示例性的互补金属氧化物半导体(CMOS)器件(即NFET器件102和PFET器件104)的半导体衬底100的截面图。在此处示出的器件制造的特定工艺阶段,但在其上形成第一层间介质(ILD)层之前,已经发生栅106材料(例如多晶硅)和被掺杂的源/漏扩散区108的硅化。图1还说明了用于形成NFET 102和PFET 104的栅氧化物层110(例如SiO2)、氧化物衬里112和氮化物隔层114,如同本领域的技术人员将认识到的那样。
按照第一实施方式,图2(a)至2(h)说明用于在硅化的NFET102和PFET 104器件上方形成自对准双氮化硅衬里的示例性工艺流程。在图2(a)中,在整个结构上方形成张应力氮化硅层116(例如采用BTBAS(双特丁基氨硅烷)前体沉积的Si3N4),示例性的厚度为约500-1000埃()。然后,在图2(b)中,在张应力氮化物层116上方形成厚氧化物层118,示例性的厚度为至少约1000埃,更特殊地,为约5000埃。施加光致抗蚀剂材料120以覆盖NFET器件区(即露出PFET器件区),实施图案化步骤,如图2(c)所示。
图2(d)说明去除PFET器件104上方露出的一部分厚氧化物层118以及张应力氮化物层116。这可以通过例如对氧化物和氮化物材料的反应离子蚀刻(RIE)来实施。特别地,由于去除张应力氮化物层116,与PFET器件104相关的侧壁隔层114在一定程度上尺寸减小。在NFET器件102上方去除剩余的光致抗蚀剂材料120之后,在整个器件上方形成压应力氮化物层122,如图2(e)所示。为了在水平表面上比在侧壁表面上形成厚度更大的压应力氮化物层122,如所示出的那样,可以通过在大约200℃-大约500℃下高密度等离子体(HDP)沉积或等离子体增强CVD(PECVD)例如SiH4/NH3/N2而形成压应力氮化物材料。因而,当压应力氮化物层122被各向同性地蚀刻或湿法蚀刻时,如图2(f)所示,在厚氧化物层118侧壁上初始形成的一部分压应力氮化物层122被去除。
在这方面,将看到在压应力氮化物层122和张应力氮化物层116之间限定了自对准的陡峭界面124,而没有采用直接的第二光刻图案化步骤以去除NFET器件102上方的压应力氮化物材料。然而为了便于其去除,然后在整个结构上方形成薄氧化物层126(例如约50-100埃),如图2(g)所示。然后,在图2(h)中,在结构上方形成光致抗蚀剂材料128,并随后图案化,从而部分地重叠在NFET器件102上方剩余的压应力氮化物材料116。诸如通过RIE去除NFET器件102上方的薄氧化物层126的露出部分,之后各向同性或湿法蚀刻(例如)以去除NFET器件102上方的压应力氮化物层122,停止于厚氧化物层118。这如图2(i)所示。作为图案化重叠的结果,在NFET器件102上方留下氧化物尖端。
在去除光致抗蚀剂材料128之后,蚀刻剩余的薄氧化物层126,直到去除尖端130,如图2(j)所示。这将有助于避免随后ILD沉积期间的可能无效(voiding)。最后,在ILD氧化物132的沉积和随后的平面化之前,任何剩余的薄氧化物材料126和厚氧化物层可以留在原位,如图2(k)所示。之后,可以继续常规的处理以完成CMOS器件。可选地,也可以在形成ILD氧化物132之前去除薄氧化物层126和厚氧化物层118。
现在一般地参照图3(a)至3(j)说明按照本发明的第二实施方式的制作用于CMOS器件的自对准双氮化硅衬里的另一个示例性工艺流程。如同第一实施方式,第二实施方式的工艺流程从图3(a)开始,在整个结构上方制作张应力氮化硅层116,示例性厚度为约500埃至约1000埃。随后是薄氧化物层302(例如约50-100埃)和牺牲氮化物层304(例如约500-700埃)的覆盖形成,如图3(b)所示。实施图案化步骤从而覆盖NFET器件区(即,露出PFET器件区),其中应用光致抗蚀剂材料306,如图3(c)所示。
图3(d)说明去除PFET器件104上方牺牲氮化物层304、薄氧化物层302和张应力氮化物层116的露出部分。这例如可以通过对氮化物、氧化物以及(再一次地)氮化物材料的连续反应离子RIE来实施。应当注意,由于去除张应力氮化物层116,也去除了与PFET器件104相关的侧壁隔层。在NFET器件102上方去除剩余的光致抗蚀剂材料306之后,在整个器件上方制作压应力氮化物层308,如图3(e)所示。为了将压应力氮化物308制作成在水平表面上比在侧壁表面上的厚度更大,如图所示,可以通过在约200℃至约500℃下高密度等离子体(HDP)沉积和PECVD例如SiH4/NH3/N2来制作压应力氮化物材料。并且,可以按相对于张应力氮化物层116稍大的水平厚度(例如约600-1200埃)制作压应力氮化物层308。
当压应力氮化物层308被各向同性蚀刻或湿法蚀刻(除去约100-200埃的示例性厚度)时,如图2(f)所示,去除了初始制作在各种侧壁形貌表面上的部分压应力氮化物层308。并且压应力氮化物层308的最终厚度大致等同于张应力氮化物层116的厚度。此外,在压应力氮化物层308和张应力氮化物层116之间限定了自对准的陡峭界面310,而没有采用用于去除NFET器件102上方的压应力氮化物材料的直接第二光刻图案化步骤。
然而,为了选择性地去除NFET器件102上方的压应力氮化物材料,然后在整个结构上方制作薄氧化物层312(如约50-100埃),如图3(g)所示。然后,在图3(h)中,在该结构上方制作光致抗蚀剂材料314,之后图案化光致抗蚀剂材料,使得光致抗蚀剂材料与在NFET器件102上方剩余的牺牲氮化物材料304(但不在NFET器件102上的张应力氮化物材料308上方)部分重叠。诸如通过RIE去除NFET器件102上方薄氧化物层312的露出部分,随后例如通过各向同性或湿法蚀刻(例如)去除NFET器件102上方的压应力氮化物层308,停止于薄氧化物层302上。这在图3(i)中说明。作为图案化重叠的结果,在NFET器件102上方留下氧化物尖端。最后,如图3(j)所示,去除剩余的光致抗蚀剂层314,随后对剩余的薄氧化物材料(即来自图3(i)的层312、302)进行湿法蚀刻。因为在图3(d)中去除PFET器件104的初始侧壁隔层,因此沉积保护薄氮化物层316。在这方面,可以继续常规的器件处理操作以完成CMOS结构。
尽管已经参照优选的一个实施方式或多个实施方式描述了本发明,但本领域的技术人员应当理解可以进行各种变化,并且对于其要素可以替换成等价物,而不背离本发明的范围。此外,对于本发明的教授内容可以作出各种变动,以适应特定的情形或材料,而不背离其必要的范围。因此,希望本发明不限于作为用于执行本发明而考虑的最佳模式所描述的特定实施方式,而是本发明将包括权利要求范围内所包含的所有实施方式。
Claims (17)
1.一种制作用于互补金属氧化物半导体(CMOS)器件的自对准双应力衬里的方法,该方法包括:
在第一极性类型的器件和第二极性类型的器件上方制作第一类型的应力层;
在所述第一类型的应力层上方制作牺牲层;
图案化并去除所述第二极性类型的器件上方的部分所述第一类型的应力层和所述牺牲层;
在所述第二极性类型的器件上方和在所述第一极性类型的器件上所述牺牲层的剩余部分上方制作第二类型的应力层,使得所述第二类型的应力层被制作成在水平表面上方比在侧壁表面上方厚度更大;
去除侧壁表面上的部分所述第二类型的应力衬里;以及
去除所述第一极性类型的器件上方的部分所述第二类型的应力衬里。
2.根据权利要求1的方法,其中所述第一类型的应力层是张应力氮化物层,所述第二类型的应力层是压应力氮化物层。
3.根据权利要求2的方法,其中所述第一极性类型的器件是NFET器件,所述第二极性类型的器件是PFET器件。
4.根据权利要求3的方法,其中在去除所述张应力氮化物层期间,去除与所述PFET器件相关的至少一部分侧壁隔层材料。
5.根据权利要求3的方法,其中所述牺牲层还包括厚度至少约1000埃的厚氧化物层。
6.根据权利要求5的方法,其中所述去除所述NFET器件上方的部分所述压应力氮化物衬里还包括:
在CMOS器件的NFET和PFET区域二者上方制作薄氧化物层,所述薄氧化物层被制作成约50埃至约100埃的厚度;
图案化并蚀刻所述NFET区域上方的一部分所述薄氧化物层;以及
采用所述厚氧化物层作为蚀刻停止层,去除所述NFET器件上方的所述压应力氮化物衬里的所述剩余部分。
7.根据权利要求6的方法,其中所述薄氧化物层被图案化成部分地与所述NFET器件上方的所述压应力氮化物衬里重叠,从而在去除所述NFET器件的所述压应力氮化物衬里之后产生氧化物尖端。
8.根据权利要求7的方法,还包括去除所述薄氧化物层的至少所述氧化物尖端部分。
9.根据权利要求3的方法,其中所述牺牲层还包括:
被制作成约50埃至约100埃的厚度的第一薄氧化物层;以及
被制作成约500埃至约700埃的厚度的牺牲氮化物层。
10.根据权利要求9的方法,其中所述去除所述NFET器件上方的部分所述压应力氮化物衬里还包括:
在CMOS器件的NFET和PFET区域二者上方制作第二薄氧化物层,所述第二薄氧化物层被制作成约50埃至约100埃的厚度;
图案化并蚀刻所述NFET区域上方的一部分所述第二薄氧化物层;以及
采用所述第一薄氧化物层作为蚀刻停止层,去除所述NFET器件上方的所述牺牲氮化物层和所述压应力氮化物衬里。
11.根据权利要求10的方法,还包括:
去除所述第一和所述第二薄氧化物层的剩余部分;以及
在CMOS器件的NFET和PFET区域二者上方制作薄氮化物层。
12.根据权利要求3的方法,其中所述压应力氮化物层被制作成大于所述张应力氮化物层的初始厚度,使得在所述去除侧壁表面上的部分所述压应力氮化物层之后,所获得的所述压应力氮化物层的厚度基本上等于所述张应力氮化物层的厚度。
13.一种制作用于半导体器件的自对准双材料衬里的方法,该方法包括:
在衬底上制作第一类型的层;
在所述第一类型的层上制作牺牲层;
图案化并去除衬底第一区域上方的部分所述第一类型的层和所述牺牲层;
在衬底的所述第一区域上方和在衬底第二区域上所述牺牲层的剩余部分上方制作第二类型的层,使得所述第二类型的层被制作成在水平表面上方比在侧壁表面上方厚度更大;
去除侧壁表面上的部分所述第二类型的衬里;以及
去除衬底的所述第二区域上方的部分所述第二类型的氮化物衬里。
14.一种互补金属氧化物半导体(CMOS)器件,包括:
在第一极性类型的器件上方形成的第一类型的应力层和在第二类型的器件上方形成的第二类型的应力层,所述第二类型的应力层与所述第一类型的应力层自对准;以及
在与所述第一和所述第二极性类型的器件中的另一个自对准期间,所述第一和所述第二极性类型的器件之一具有至少一部分与之相关的侧壁隔层材料被去除。
15.根据权利要求14的CMOS器件,其中所述第一类型的应力层是张应力氮化物层,所述第二类型的应力层是压应力氮化物层。
16.根据权利要求15的CMOS器件,其中所述第一极性类型的器件是NFET器件,所述第二极性类型的器件是PFET器件。
17.根据权利要求16的CMOS器件,还包括在所述第一类型的应力层和所述第二类型的应力层上方形成的保护氮化物层。
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Also Published As
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CN100585833C (zh) | 2010-01-27 |
US20080012019A1 (en) | 2008-01-17 |
US7288451B2 (en) | 2007-10-30 |
US20060199326A1 (en) | 2006-09-07 |
US7569892B2 (en) | 2009-08-04 |
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