CN102543744B - 晶体管及其制作方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 242
- 239000010410 layer Substances 0.000 claims abstract description 190
- 239000000758 substrate Substances 0.000 claims abstract description 108
- 239000013078 crystal Substances 0.000 claims abstract description 75
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 33
- 239000011229 interlayer Substances 0.000 claims abstract description 21
- 230000007547 defect Effects 0.000 claims description 39
- RLLPVAHGXHCWKJ-IEBWSBKVSA-N (3-phenoxyphenyl)methyl (1s,3s)-3-(2,2-dichloroethenyl)-2,2-dimethylcyclopropane-1-carboxylate Chemical compound CC1(C)[C@H](C=C(Cl)Cl)[C@@H]1C(=O)OCC1=CC=CC(OC=2C=CC=CC=2)=C1 RLLPVAHGXHCWKJ-IEBWSBKVSA-N 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 14
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims description 8
- 239000000243 solution Substances 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 7
- -1 Nitrogen ion Chemical class 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 239000012670 alkaline solution Substances 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 230000005012 migration Effects 0.000 abstract description 7
- 238000013508 migration Methods 0.000 abstract description 7
- 239000002800 charge carrier Substances 0.000 description 10
- 238000002360 preparation method Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000006835 compression Effects 0.000 description 5
- 238000007906 compression Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000012772 electrical insulation material Substances 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明提供了一种晶体管及其制作方法,所述方法包括:提供半导体衬底,所述半导体衬底上形成有半导体层,所述半导体层的晶向与所述半导体衬底的晶向不同;在所述半导体层上形成伪栅极结构;在所述伪栅极结构两侧的半导体衬底和半导体层内形成源区和漏区;在所述半导体层上形成与所述伪栅极结构齐平的层间介质层;去除所述伪栅极结构、位于所述伪栅极结构下方的半导体层,在所述层间介质层和半导体层内形成开口,所述开口露出下方的半导体衬底;在所述开口内形成金属栅极结构。本发明提高了载流子的迁移速率,增大了晶体管的饱和电流。
Description
技术领域
本发明涉及半导体技术领域,特别涉及晶体管及其制作方法。
背景技术
应变记忆技术(Stress Memorization Technique,简称SMT)以及应力刻蚀阻挡层技术(Stressd-CESL,contact etch stop layer)是现有的提高晶体管载流子迁移率的两种技术。通过上述两种技术,在晶体管的沟道区形成稳定应力,提高沟道中的载流子迁移率。所述应力平行于沟道长度方向,可以为延伸应力或压缩应力。通常拉伸应力可以使得沟道区域中的原子排列更加疏松,从而提高电子的迁移率,适用于NMOS晶体管;而压缩应力使得沟道区域内的原子排布更加紧密,有助于提高空穴的迁移率,适用于PMOS晶体管。
请参考图1~图3,为现有技术的晶体管的制作方法剖面结构示意图。
首先,参考图1,提供半导体衬底10,所述半导体衬底10上形成有NMOS晶体管和PMOS晶体管,所述NMOS晶体管和PMOS晶体管之间具有隔离结构11。所述NMOS晶体管包括P阱(未示出)、形成于P阱内的NMOS晶体管源/漏区12、位于源/漏区12之间半导体衬底上的NMOS晶体管栅极13;所述PMOS晶体管包括:N阱(未示出)、形成于N阱内的PMOS晶体管的源/漏区14、位于源/漏区14之间的PMOS晶体管的栅极15。
然后,参考图2,在所述NMOS晶体管以及PMOS晶体管表面形成覆盖源/漏区12、栅极13以及半导体衬底10的应力层16,所述应力层16的材质可以为氮化硅。所述应力层16可以提供拉伸应力或压应力。假设所述应力层16提供拉伸应力,对NMOS晶体管产生有益影响。
然后,参考图3,使用掩膜层进行刻蚀,去除PMOS晶体管表面的应力层16,保留位于NMOS晶体管表面的应力层16。然后,进行退火,使得NMOS晶体管表面的应力层16诱发拉伸应力,所述拉伸应力保留在NMOS晶体管中,提高了NMOS晶体管沟道区载流子(即电子)的迁移率。在退火之后,通常进行刻蚀工艺去除位于NMOS晶体管的栅极13、源/漏区12以及半导体衬底10的应力层16。
在公开号为CN101393894A的中国专利申请中可以发现更多关于现有的MOS晶体管的制作方法。
但是,在实际中发现,利用现有的方法形成的晶体管的饱和电流值偏低,影响器件的性能。
发明内容
本发明解决的问题是提供了一种晶体管及其制作方法,所述方法提高了晶体管的饱和电流,改善了器件的性能。
为解决上述问题,本发明提供一种晶体管的制作方法,包括:
提供半导体衬底,所述半导体衬底上形成有半导体层,所述半导体层的晶向与所述半导体衬底的晶向不同;
在所述半导体层上形成伪栅极结构;
在所述伪栅极结构两侧的半导体衬底和半导体层内形成源区和漏区;
在所述半导体层上形成与所述伪栅极结构齐平的层间介质层;
去除所述伪栅极结构、位于所述伪栅极结构下方的半导体层,在所述层间介质层和半导体层内形成开口,所述开口露出下方的半导体衬底;
在所述开口内形成金属栅极结构。
可选地,所述晶体管为NMOS晶体管,所述半导体衬底的晶向为(100),所述半导体层的晶向为(110)。
可选地,所述晶体管为PMOS晶体管,所述半导体衬底的晶向为(110),所述半导体层的晶向为(100)。
可选地,所述半导体层的厚度为3~30纳米。
可选地,还包括:
进行轻掺杂离子注入,在所述半导体衬底和半导体层内形成轻掺杂区的步骤,所述轻掺杂区位于所述栅极结构两侧。
可选地,在所述开口内制作所述金属栅极结构之前,还包括:
在所述开口内制作外延层的步骤,所述外延层位于所述金属栅极结构与半导体衬底之间,所述外延层的晶向与所述半导体衬底的晶向相同。
可选地,所述外延层的材质为锗硅,所述锗硅中锗的质量浓度范围为4~40%。
可选地,还包括:对所述外延层进行缺陷吸附离子注入的步骤,在所述外延层内形成缺陷吸附离子,所述缺陷吸附离子用于吸附沟道区内的缺陷。
可选地,所述缺陷吸附离子注入的掺杂离子为氟离子或氮离子。
可选地,所述半导体层的去除方法为湿法刻蚀的方法。
可选地,所述湿法刻蚀的方法利用的溶液为碱性溶液。
相应地,本发明还提供一种晶体管,包括:
半导体衬底,所述半导体衬底上形成有半导体层,所述半导体层的晶向与所述半导体衬底的晶向不同;
层间介质层,位于所述半导体层上;
开口,位于所述层间介质层和半导体层内,所述开口露出下方的半导体衬底;
金属栅极结构,位于所述开口内;
源区,位于所述金属栅极结构一侧的半导体层和半导体衬底内;
漏区,位于所述金属栅极结构另一侧的半导体层和半导体衬底内。
可选地,所述晶体管为NMOS晶体管,所述半导体衬底的晶向为(100),所述半导体层的晶向为(110)。
可选地,所述晶体管为PMOS晶体管,所述半导体衬底的晶向为(110),所述半导体层的晶向为(100)。
可选地,所述半导体层的厚度为3~30纳米。
可选地,还包括:
轻掺杂区,位于所述半导体衬底和半导体层内,且所述轻掺杂区位于所述金属栅极结构两侧。
可选地,还包括:
外延层,位于所述金属栅极结构与半导体衬底之间,且所述外延层位于所述源区和漏区之间,所述外延层的晶向与所述半导体衬底的晶向相同,且所述外延层与所述半导体层齐平。
可选地,所述外延层的材质为锗硅,所述锗硅中锗的质量浓度范围为4~40%。
可选地,所述外延层内形成有缺陷吸附离子,所述缺陷吸附离子用于吸附沟道区内的缺陷。
可选地,所述缺陷吸附离子为氟离子或氮离子。
与现有技术相比,本发明具有以下优点:
本发明首先在半导体衬底上形成与所述半导体衬底具有不同晶向的半导体层,在所述半导体层上制作伪栅极结构,接着,在所述伪栅极结构两侧的半导体衬底和半导体层内形成源区和漏区;由于所述源区和漏区是形成在所述半导体衬底和半导体层内的,所述源区和漏区之间的半导体衬底和半导体层作为沟道区,所述半导体衬底和半导体层的晶向不同,从而所述半导体衬底和半导体层在所述沟道区产生应力,该应力提高了源区和漏区的载流子的迁移率,从而提高了晶体管的饱和漏电流,改善了半导体器件的性能;
进一步优化地,在所述开口内制作所述金属栅极结构之前,还包括:在所述开口内制作外延层的步骤,从而制作的外延层与所述半导体衬底的晶向相同,利用该外延层制作取代半导体层作为沟道区的一部分,可以减小由于半导体层与半导体层的晶向不同在所述沟道区引起的漏电流,并且外可以防止外延层的晶向与所述半导体衬底的晶向不同引起的载流子的迁移速率下降的问题;
进一步优化地,还包括:对所述外延层进行缺陷吸附离子注入的步骤,在所述外延层内形成缺陷吸附离子,所述缺陷吸附离子用于吸附沟道区内的缺陷,从而防止沟道区的缺陷引起的氧化增强扩散效应,减小器件的漏电流。
附图说明
图1~图3是现有技术的晶体管制作方法剖面结构示意图;
图4是本发明的晶体管制作方法流程示意图;
图5~图11是本发明的晶体管制作方法剖面结构示意图。
具体实施方式
现有的方法形成的晶体管的饱和电流值偏低,影响器件的性能。经过发明人研究发现,造成所述晶体管的饱和电流值偏低的原因是,晶体管的载流子的迁移率偏低,无法满足实际的要求,影响了器件的性能。并且,随着晶体管特征尺寸的缩小,现有的晶体管的特征尺寸缩小至45纳米范围,栅介质层的厚度减小,源区和漏区之间的距离缩短,从而使得所述晶体管内存在的漏电流问题也较为严重。
发明人经过创造性劳动,提出一种晶体管的制作方法,请参考图4所示的本发明的晶体管制作方法流程示意图。所述方法包括:
步骤S1,提供半导体衬底,所述半导体衬底上形成有半导体层,所述半导体层的晶向与所述半导体衬底的晶向不同;
步骤S2,在所述半导体层上形成伪栅极结构;
步骤S3,在所述伪栅极结构两侧的半导体衬底和半导体层内形成源区和漏区;
步骤S4,在所述半导体层上形成与所述伪栅极结构齐平的层间介质层;
步骤S5,去除所述伪栅极结构、位于所述伪栅极结构下方的半导体层,在所述层间介质层和半导体层内形成开口,所述开口露出下方的半导体衬底;
步骤S6,在所述开口内形成金属栅极结构。
下面结合具体的实施例对本发明的技术方案进行详细的说明。为了更好地说明本发明的技术方案,请参考图5~图11所示的本发明一个实施例的晶体管制作方法剖面结构示意图。
首先,请参考图5,提供半导体衬底100,所述半导体衬底100上形成有半导体层101,所述半导体层101的晶向与所述半导体衬底100的晶向不同。
由于所述半导体层101的晶向与所述半导体衬底100的晶向不同,从而在所述半导体层101与所述半导体衬底100之间产生应力。所述应力的类型与所述半导体层101的晶向与所述半导体衬底100的晶向有关系。
具体地,当所述半导体衬底100的晶向为(100),所述半导体层101的晶向为(110)时,所述半导体衬底100与所述半导体层101之间产生的应力为拉应力,该拉应力能够提高电子的迁移率,从而有益于提高NMOS晶体管的饱和电流值;当所述半导体衬底100的晶向为(110),所述半导体层101的晶向为(100)时,所述半导体衬底100与所述半导体层101之间产生的应力为压应力,该压应力能够提高空穴的迁移率,从而有益于提高PMOS晶体管的饱和电流值。
若要产生足够的应力,所述半导体层101需要满足一定的厚度,即所述半导体层101的厚度需要大于3纳米;但是所述半导体层101的厚度也不应过大,以防止无法形成符合要求的晶体管,所述半导体层101的厚度应小于32纳米。在上述的厚度范围内,能够产生足够的应力,有效提高载流子的迁移率,同时不会影响晶体管的性能。
接着,请参考图6,在所述半导体层101上形成栅介质层102,在所述栅介质层102上形成伪栅极103。所述伪栅极103与栅介质层102共同构成伪栅极结构。
所述栅介质层102的材质为电学绝缘材质,所述电学绝缘材质优选为氧化硅或氮氧化硅。所述栅介质层102的厚度范围为3~80埃。所述栅介质层102优选地利用氧化工艺制作。
所述伪栅极103的材质为多晶硅。所述多晶硅可以利用化学气相沉积工艺制作。所述化学气相沉积工艺与现有技术相同,作为本领域技术人员的公知技术,在此不做详细的说明。
作为本发明的优选实施例,在伪栅极103形成后,还要在所述伪栅极103和栅介质层102的两侧的半导体层101上形成伪栅极侧墙(spacer)104,所述伪栅极侧墙104用于保护所述伪栅极103和栅介质层102。所述伪栅极侧墙104可以为单层的氧化硅层或多层的氧化硅层-氮化硅层-氧化硅层构成的ONO结构。
然后,请参考图7,在所述伪栅极103和栅介质层102两侧的半导体衬底100和半导体层101内形成源区105和漏区106。
所述源区105和漏区106通过源/漏离子注入(SD implant)形成。所述源/漏离子注入与现有技术相同,作为本领域技术人员的公知技术,在此不做详细的说明。
所述源区105和漏区106之间的半导体层101和半导体衬底100为沟道区。由于所述半导体层101与所述源区105和漏区106之间产生应力,从而有利于提高所述沟道区的载流子的迁移速率,进而可以提高晶体管的饱和电流。
接着,请参考图8,在所述半导体层101上形成与所述栅极104齐平的层间介质层107。所述层间介质层107的材质可以为氧化硅、氮化硅、碳化硅或氮氧化硅。
接着,请参考图9,进行刻蚀工艺,去除所述伪栅极103(参考图8)、栅介质层102(参考图8)以及位于所述栅介质层102下方的部分半导体层101,在所述层间介质层107和半导体层101内形成开口,所述开口露出下方的半导体衬底100。所述开口用于在后续的工艺步骤中制作金属栅极结构。所述去除的部分半导体层101的宽度等于所述伪栅极结构的宽度。
所述伪栅极103和栅介质层102的去除方法可以为干法刻蚀或湿法刻蚀,若采用干法刻蚀去除所述伪栅极103和栅介质层102,可以采用含有氟离子、氟离子的等离子体进行刻蚀,若采用湿法刻蚀,可以采用酸性溶液,所述酸性溶液可以为盐酸、醋酸和硝酸的混合溶液;所述半导体层101的去除方法为湿法刻蚀的方法,所述湿法刻蚀的方法采用碱性溶液,所述碱性溶液可以采用KOH溶液,所述碱性溶液也可以采用氢氧化铵溶液。
由于所述刻蚀工艺可能造成位于伪栅极103和栅介质层102两侧的伪栅极侧墙104(参考图8)损伤,从而可能引起后续形成的金属栅极结构漏电流。因此,作为本发明的优选实施例,还需要进行刻蚀工艺,去除位于所述伪栅极103和栅介质层102两侧的伪栅极侧墙104(参考图8),从而露出下方的部分半导体层101。
然后,请参考图10,进行轻掺杂离子注入(LDD implant),在所述半导体层101和半导体衬底100内形成轻掺杂区108,所述轻掺杂离子注入具有一定的倾斜角度,以能够控制形成的轻掺杂区108的宽度,防止将掺杂离子注入所述开口下方的半导体衬底100内。作为一个实施例,所述轻掺杂区离子注入的角度范围为20~45度。
然后,请参考图11,作为优选的实施例,在所述轻掺杂区域108形成后,还需要进行外延工艺,在所述半导体层101内的开口内形成外延层109,所述外延层109的晶向与所述半导体衬底100的晶向相同。所述外延层109的位置与后续形成的金属栅极结构的位置对应,所述外延层109位于所述源区105和漏区106之间的半导体层101内,且所述外延层109与所述半导体层101齐平。由于所述外延层109与所述半导体衬底100的晶向相同,利用该外延层109可以作为沟道区的一部分,从而减小由于半导体层与半导体层的晶向不同在所述沟道区引起的漏电流。
所述外延层109的材质为半导体材质,作为一个实施例,所述外延层109的材质为锗硅,其中锗的质量浓度为4~40%。
在所述外延层109形成后,还要对所述外延层109进行缺陷吸附离子注入的步骤,在所述外延层109内形成缺陷吸附离子,所述缺陷吸附离子用于吸附沟道区内的缺陷。本实施例中,所述缺陷吸附离子注入的掺杂离子为氟离子或氮离子。所述缺陷吸附离子用于吸附沟道区内的缺陷,从而防止沟道区的缺陷引起的氧化增强扩散效应,减小器件的漏电流。
然后,请继续参考图11,在所述层间介质层107的开口的侧壁上制作金属栅极侧墙110,所述金属栅极侧墙110的材质为氧化硅、氮化硅、碳化硅或氮氧化硅。所述金属栅极侧墙110的厚度应小于20纳米,以有利于减小晶体管的面积。
接着,在所述层间介质层107的开口的侧壁和底部制作高K介质层111,所述高K介质层111的材质可以为氧化铪、氧化铪硅、氧化镧、氧化锆、氧化锆硅、氧化钛、氧化钽、氧化钡锶钛、氧化钡钛或氧化铝等。其中位于所述开口底部的高K介质层111覆盖于所述外延层109的表面。
由于所述高K介质层111位于所述开口的侧壁和底部,从而与现有技术的高K介质层只形成在开口的底部相比,本发明减小了晶体管的漏电流。
接着,继续参考图11,在所述开口内制作金属栅极112,所述金属栅极112与所述层间介质层107、金属侧墙1110、高K介质层111和金属栅极112齐平。所述金属栅极112与所述高K介质层111共同构成金属栅极结构,所述金属栅极结构位于所述外延层109上方。
经过上述工艺步骤形成的晶体管,请参考图11所示,所述晶体管包括:
半导体衬底100,所述半导体衬底100上形成有半导体层101,所述半导体层101的晶向与所述半导体衬底100的晶向不同;
层间介质层107,位于所述半导体层101上;
开口,位于所述层间介质层107和半导体层101内,所述开口露出下方的半导体衬底100;
金属栅极结构,位于所述开口内,所述金属栅极结构包括位于所述开口内的高K介质层111和金属栅极112,其中所述高K介质层111位于所述开口的侧壁和底部,所述金属栅极112将所述开口填满;
金属栅极侧墙110,位于所述开口的侧壁,且所述金属栅极结构与所述层间介质层107之间;
源区105,位于所述金属栅极结构一侧的半导体层101和半导体衬底100内;
漏区106,位于所述金属栅极结构另一侧的半导体层101和半导体衬底100内。
作为本发明优选实施例,所述晶体管还包括:
外延层109,位于所述金属栅极结构与半导体衬底100之间,且所述外延层109的位置与所述源区105和漏区106的位置对应,所述外延层109的晶向与所述半导体衬底100的晶向相同,所述外延层109用于将所述半导体层101内的开口填满;
轻掺杂区108,位于所述半导体衬底100和半导体层101内,且所述轻掺杂区108位于所述金属栅极结构两侧。
所述外延层109作为晶体管的沟道区,其晶向与所述半导体衬底100的晶向相同,从而所述外延层109可以晶体管的漏电流,并且可以防止沟道区的晶向与所述半导体衬底100的晶向不同引起的载流子的迁移速率下降的问题。所述外延层109的材质为锗硅,其中锗的质量浓度为4~40%,所述外延层109内有缺陷吸附离子,所述缺陷吸附离子用于吸附沟道区内的缺陷。所述缺陷吸附区内的掺杂离子为氟离子或氮离子。
需要说明的是,所述半导体层100的晶向和半导体衬底100的晶向需要根据所述晶体管的类型进行具体的设置,当所述晶体管为NMOS晶体管,所述半导体衬底100的晶向为(100),所述半导体层101的晶向为(110),在所述半导体衬底100与半导体层101之间产生的应力为拉应力,从而有利于提高电子的迁移速率,有利于增大NMOS晶体管的饱和电流;当所述晶体管为PMOS晶体管,所述半导体衬底100的晶向为(110),所述半导体层101的晶向为(100),从而有利于提高空穴的迁移速率,有利于增大PMOS晶体管的饱和电流。
若要产生足够的应力,所述半导体层101需要满足一定的厚度,即所述半导体层101的厚度需要大于3纳米;但是所述半导体层101的厚度也不应过大,以防止无法形成符合要求的晶体管,所述半导体层101的厚度应小于32纳米。在上述的厚度范围内,能够产生足够的应力,有效提高载流子的迁移率,同时不会影响晶体管的性能。作为本发明的一个实施例,所述半导体层的厚度为3~30纳米。
综上,本发明提供了一种晶体管及其制作方法,所述方法首先在半导体衬底上形成与所述半导体衬底具有不同晶向的半导体层,在所述半导体层上制作伪栅极结构,接着,在所述伪栅极结构两侧的半导体衬底和半导体层内形成源区和漏区;由于所述源区和漏区是形成在所述半导体衬底和半导体层内的,所述源区和漏区之间的半导体衬底和半导体层作为沟道区,所述半导体衬底和半导体层的晶向不同,从而所述半导体衬底和半导体层在所述沟道区产生应力,该应力提高了源区和漏区的载流子的迁移率,从而提高了晶体管的饱和漏电流,改善了半导体器件的性能;
在本发明优选实施例中,在所述开口内制作所述金属栅极结构之前,还包括:在所述开口内制作外延层的步骤,从而制作的外延层与所述半导体衬底的晶向相同,利用该外延层制作取代半导体层作为沟道区的一部分,可以减小由于半导体层与半导体层的晶向不同在所述沟道区引起的漏电流,并且外可以防止外延层的晶向与所述半导体衬底的晶向不同引起的载流子的迁移速率下降的问题;
在本发明优选实施例中,还包括:对所述外延层进行缺陷吸附离子注入的步骤,在所述外延层内形成缺陷吸附离子,所述缺陷吸附离子用于吸附沟道区内的缺陷,从而防止沟道区的缺陷引起的氧化增强扩散效应,减小器件的漏电流。
本发明虽然已以较佳实施例公开如上,但其并不是用来限定本发明,任何本领域技术人员在不脱离本发明的精神和范围内,都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改,因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰,均属于本发明技术方案的保护范围。
Claims (18)
1.一种晶体管的制作方法,其特征在于,包括:
提供半导体衬底,所述半导体衬底表面上形成有半导体层,所述半导体层的晶向与所述半导体衬底的晶向不同,所述半导体层和半导体衬底之间产生应力;
在所述半导体层上形成伪栅极结构;
在所述伪栅极结构两侧的半导体衬底和半导体层内形成源区和漏区;
在所述半导体层上形成与所述伪栅极结构齐平的层间介质层;
去除所述伪栅极结构、位于所述伪栅极结构下方的半导体层,在所述层间介质层和半导体层内形成开口,所述开口露出下方的半导体衬底;
在所述开口内形成外延层,所述外延层的晶向与所述半导体衬底的晶向相同,且所述外延层与所述半导体层齐平;
在所述开口内形成金属栅极结构。
2.如权利要求1所述的晶体管的制作方法,其特征在于,所述晶体管为NMOS晶体管,所述半导体衬底的晶向为(100),所述半导体层的晶向为(110)。
3.如权利要求1所述的晶体管的制作方法,其特征在于,所述晶体管为PMOS晶体管,所述半导体衬底的晶向为(110),所述半导体层的晶向为(100)。
4.如权利要求1所述的晶体管的制作方法,其特征在于,所述半导体层的厚度为3~30纳米。
5.如权利要求1所述的晶体管的制作方法,其特征在于,还包括:
进行轻掺杂离子注入,在所述半导体衬底和半导体层内形成轻掺杂区的步骤,所述轻掺杂区位于所述栅极结构两侧。
6.如权利要求1所述的晶体管的制作方法,其特征在于,所述外延层的材质为锗硅,所述锗硅中锗的质量浓度范围为4~40%。
7.如权利要求6所述的晶体管的制作方法,其特征在于,还包括:对所述外延层进行缺陷吸附离子注入的步骤,在所述外延层内形成缺陷吸附离子,所述缺陷吸附离子用于吸附沟道区内的缺陷。
8.如权利要求7所述的晶体管的制作方法,其特征在于,所述缺陷吸附离子注入的掺杂离子为氟离子或氮离子。
9.如权利要求1所述的晶体管的制作方法,其特征在于,所述半导体层的去除方法为湿法刻蚀的方法。
10.如权利要求9所述的晶体管的制作方法,其特征在于,所述湿法刻蚀的方法利用的溶液为碱性溶液。
11.一种晶体管,其特征在于,包括:
半导体衬底,所述半导体衬底表面上形成有半导体层,所述半导体层的晶向与所述半导体衬底的晶向不同,所述半导体层和半导体衬底之间产生应力;
层间介质层,位于所述半导体层上;
开口,位于所述层间介质层和半导体层内,所述开口露出下方的半导体衬底;
金属栅极结构,位于所述开口内;
源区,位于所述金属栅极结构一侧的半导体层和半导体衬底内;
漏区,位于所述金属栅极结构另一侧的半导体层和半导体衬底内;
外延层,位于所述金属栅极结构与半导体衬底之间,且所述外延层位于所述源区和漏区之间,所述外延层的晶向与所述半导体衬底的晶向相同,且所述外延层与所述半导体层齐平。
12.如权利要求11所述的晶体管,其特征在于,所述晶体管为NMOS晶体管,所述半导体衬底的晶向为(100),所述半导体层的晶向为(110)。
13.如权利要求11所述的晶体管,其特征在于,所述晶体管为PMOS晶体管,所述半导体衬底的晶向为(110),所述半导体层的晶向为(100)。
14.如权利要求11所述的晶体管,其特征在于,所述半导体层的厚度为3~30纳米。
15.如权利要求11所述的晶体管,其特征在于,还包括:
轻掺杂区,位于所述半导体衬底和半导体层内,且所述轻掺杂区位于所述金属栅极结构两侧。
16.如权利要求11所述的晶体管,其特征在于,所述外延层的材质为锗硅,所述锗硅中锗的质量浓度范围为4~40%。
17.如权利要求11所述的晶体管,其特征在于,所述外延层内形成有缺陷吸附离子,所述缺陷吸附离子用于吸附沟道区内的缺陷。
18.如权利要求17所述的晶体管,其特征在于,所述缺陷吸附离子为氟离子或氮离子。
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