WO2014029149A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2014029149A1
WO2014029149A1 PCT/CN2012/081506 CN2012081506W WO2014029149A1 WO 2014029149 A1 WO2014029149 A1 WO 2014029149A1 CN 2012081506 W CN2012081506 W CN 2012081506W WO 2014029149 A1 WO2014029149 A1 WO 2014029149A1
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WIPO (PCT)
Prior art keywords
layer
source
drain region
lattice constant
semiconductor device
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PCT/CN2012/081506
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English (en)
French (fr)
Inventor
钟汇才
赵超
梁擎擎
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中国科学院微电子研究所
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Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to US14/423,395 priority Critical patent/US9306016B2/en
Publication of WO2014029149A1 publication Critical patent/WO2014029149A1/zh

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    • H01L29/78654—Monocrystalline silicon transistors

Definitions

  • the present invention relates to semiconductor manufacturing technology, and more particularly to a semiconductor device and a method of fabricating the same. Background technique
  • FIG. 1(a) A bulk silicon substrate 100 having a gate stack is provided, and a bulk silicon substrate 100 on both sides of the gate stack is first etched to form a recess, and then For example, boron-doped SiGe or phosphorus- or arsenic-doped Si:C is embedded in the recess to form a source/drain region 110 having stress.
  • the SOI substrate 100 includes a base layer 101, an insulating layer 102, and a device layer 103.
  • the embedded source/drain region 110 is formed in the device layer 103 of the SOI substrate 100, and the source/drain region 110 is isolated from the base layer 101 due to the presence of the insulating layer 102, thereby effectively weakening the leakage current path (please Referring to the position shown by the broken line in Fig. 1(a) and Fig. 1(b), the leakage current between the source/drain region 110 and the substrate 100 is suppressed.
  • the thickness of the SOI substrate device layer 103 is generally thin, so the depth of the source/drain regions 110 formed on the SOI substrate 100 is also shallow due to the thickness of the device layer 103, resulting in source/drain regions.
  • An object of the present invention is to provide a semiconductor device and a method of fabricating the same that can reduce the contact resistance of a source/drain region while eliminating a leakage current path between a source/drain region and a SOI substrate.
  • a method of fabricating a semiconductor device comprising the steps of:
  • Another aspect of the present invention also provides a semiconductor device, including:
  • a SOI substrate comprising a substrate layer, an insulating layer over the substrate layer, and a device layer over the insulating layer;
  • source/drain regions formed in the bottom of the SOI, on both sides of the gate stack, wherein the source/drain regions extend through the device layer and extend to an upper surface of the insulating layer and Between the lower surfaces;
  • a crystalline dielectric layer between the source/drain regions and the substrate layer is
  • the present invention has the following advantages:
  • the bottom of the source/drain region is located in the insulating layer at the bottom of the SOI village, and a crystalline dielectric layer is formed between the source/drain region and the bottom of the SOI village, and the bottom of the source/drain region is isolated from the bottom of the SOI village, thereby Effectively The leakage current path between the source/drain region and the bottom of the SOI is eliminated, and the generation of leakage current is suppressed;
  • 1(a) and 1(b) are schematic cross-sectional views showing a semiconductor device in the prior art
  • FIG. 2 is a flow chart of a method of fabricating a semiconductor device in accordance with the present invention.
  • 3 through 11 are cross-sectional views showing stages of fabricating a semiconductor device in accordance with the flow shown in FIG. 2, in accordance with one embodiment of the present invention.
  • first and second features are formed in direct contact
  • additional features formed in the first and second features.
  • Embodiments between the signs, such that the first and second features may not be in direct contact.
  • FIG. 2 is a flow chart of a method of fabricating a semiconductor device in accordance with the present invention
  • FIGS. 3 through 11 are cross-sectional views showing stages of fabricating a semiconductor device in accordance with the flow shown in FIG. 2, in accordance with an embodiment of the present invention.
  • a method of forming a semiconductor device in Fig. 2 will be specifically described with reference to Figs. 3 to 11. It is to be understood that the drawings of the embodiments of the present invention are intended for purposes of illustration
  • step S101 an SOI substrate 100 is provided, the SOI substrate 100 including a base layer 101, an insulating layer 102 over the base layer 101, and a device layer over the insulating layer 102. 103.
  • the base layer 101 is single crystal silicon.
  • the base layer 101 may also include other basic semiconductors such as germanium.
  • the base layer 101 may further include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide or indium phosphide.
  • the thickness of the base layer 101 can be, but is not limited to, a few hundred microns, such as from a thickness ranging from 0.5 mm to 1.5 mm.
  • the insulating layer 102 may be SiO 2 , silicon nitride or any other suitable insulating material. Typically, the insulating layer 102 has a thickness ranging from 200 nm to 300 nm.
  • the device layer 103 may be any one of the semiconductors included in the base layer 101.
  • the device layer 103 is monocrystalline silicon.
  • the device layer 103 may also include other base semiconductors or compound semiconductors.
  • the device layer 103 has a thickness greater than 20 nm.
  • the SOI substrate 100 is an ultra-thin SOI (Ultra-Thin-Body SOI, UTBSOI) substrate, which has an extremely thin device layer, and the thickness is usually less than 10 nm, which is beneficial to the control source. The depth formed by the /drain region, thereby reducing the short channel effect.
  • UTBSOI Ultra-Thin-Body SOI
  • an isolation region such as a shallow trench isolation (STI) structure 120, is formed in the SOI substrate 100 to electrically isolate the continuous semiconductor device.
  • STI shallow trench isolation
  • a gate stack is formed on the SOI substrate 100. Specifically, as shown in FIG. 4, a gate stack is formed over the SOI substrate 100, which includes a gate dielectric layer 210, a gate 220, and a cap layer 230.
  • the gate dielectric layer 210 is located on the SOI substrate 100 and may be a high K dielectric, for example, Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO One or a combination thereof.
  • the gate dielectric layer 104 may have a thickness of 2 nm to 10 nm, such as 5 nm or 8 nm.
  • a gate 220 is formed on the gate dielectric layer 210, and the gate 220 may be a metal gate, for example, by depositing TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x One or a combination thereof may be formed, and the thickness may be from 10 nm to 80 nm, such as 30 nm or 50 nm.
  • the gate 220 may also be a dummy gate, such as formed by depositing Poly-Si, Poly-SiGe, amorphous silicon, and/or oxide.
  • a capping layer 230 is formed on the gate electrode 220, for example, by depositing silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof to protect the top region of the gate 220 from subsequent processes. Damaged.
  • sidewall spacers 240 are formed on sidewalls of the gate stack for isolating the gate stack.
  • Sidewall 240 can be formed from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, combinations thereof, and/or other suitable materials.
  • the side wall 240 may have a multi-layered structure.
  • the sidewall spacer 240 may be formed by a deposition-etching process including a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm or 80 nm.
  • step S103 the device layer 103, the insulating layer 102, and the portion of the base layer 101 of the SOI substrate 100 are etched by using the gate stack as a mask, and recesses 104 are formed on both sides of the gate stack.
  • the device layer 103, the insulating layer 102, and a portion of the base layer 101 of the SOI substrate 100 are etched, and recesses 104 are formed on both sides of the gate stack.
  • the SOI substrate 100 on both sides of the gate stack is etched by anisotropic dry etching and/or wet etching to form a through-the-span.
  • the device layer 103 and the insulating layer 102 and the recess 104 deep inside the base layer 101 are described.
  • the depth of the recess 104 deep into the interior of the base layer 101 ranges from 100 nm to lum.
  • Wet etching process includes four Ammonium hydroxide (TMAH), potassium hydroxide (KOH) or other suitable etching solution; dry etching process includes sulfur hexafluoride (SF 6 ), hydrogen bromide (HBr), hydrogen iodide (HI) , chlorine, argon, helium and combinations thereof, and / or other suitable materials. According to the materials of the device layer 103, the insulating layer 102, and the base layer 101, etching may be performed in an appropriate manner.
  • TMAH Ammonium hydroxide
  • KOH potassium hydroxide
  • dry etching process includes sulfur hexafluoride (SF 6 ), hydrogen bromide (HBr), hydrogen iodide (HI) , chlorine, argon, helium and combinations thereof, and / or other suitable materials. According to the materials of the device layer 103, the insulating layer 102, and the base layer 101, etching may be performed in an appropriate manner.
  • the isotropic and anisotropic etching modes may be alternately used, not only etching the SOI substrate 100 on both sides of the gate stack, but also partially scanning the SOI substrate 100 under the sidewall 240.
  • Etching, particularly the device layer 103 in the SOI substrate 100 causes the recess formed after etching to be as close as possible to the center of the trench, for example, the recess 104 in Figure 5(b), or in Figure 5(c) Sigma-shaped recess 104".
  • etching the device layer 103 in the lower portion of the spacer 240, particularly the SOI substrate 100, so that the recess 104 is close to the center of the channel can also be performed when the source/drain regions are subsequently formed.
  • step S104 a crystalline dielectric layer 105 is formed in the recess 104, and an upper surface of the crystalline dielectric layer 105 is lower than an upper surface of the insulating layer 102 and not lower than the insulating layer 102. The lower surface.
  • the base layer 101 is seeded, and a crystalline insulating material 105 is formed in the recess 104 by epitaxial growth or solid phase phase change, wherein the crystal
  • the upper surface of the insulating material 105 is not higher than the bottom of the gate stack; then, as shown in FIG. 7, the crystalline insulating material 105 is engraved by dry etching and/or wet etching. Etching to form a crystalline dielectric layer 105. It is also possible to stop the growth of the crystalline insulating material 105 after growing to a desired height by, for example, controlling the growth time of the crystalline insulating material 105, to form the crystalline dielectric layer 105.
  • the upper surface of the crystalline dielectric layer 105 is lower than the upper surface of the insulating layer 102 and not lower than the lower surface of the insulating layer 102.
  • the material of the crystalline dielectric layer 105 includes, but is not limited to, one or any combination of Gd 2 0 3 , TrHf0 4 , Nd 2 0 3 , or other material having a lattice constant close to the base layer 101.
  • the dielectric constant of the crystalline dielectric layer 105 can be adjusted by, for example, adjusting the ratio of the components in the material of the crystalline dielectric layer 105, so that the crystalline dielectric layer 105 has good insulation properties.
  • step S105 source/drain regions 107 are formed over the crystalline dielectric layer 105.
  • the material of the crystalline dielectric layer 105 is seeded, and a doped source/drain region 107 is formed in the recess 104 by epitaxial growth or solid phase phase change. Filling the recess 104.
  • the source/drain regions 107 have a lattice constant that is not equal to the lattice constant of the material of the device layer 103.
  • the lattice constant of the source/drain region 107 is slightly larger or slightly smaller than the lattice constant of the material of the device layer 103, not only a certain stress is introduced into the channel, but also the source/drain region 107 is It is well grown on top of the crystalline dielectric layer 105.
  • the lattice constant of the source/drain region 107 is slightly larger than the lattice constant of the material of the device layer 103, thereby generating compressive stress on the channel.
  • the source/drain region 107 may be SiuGex.
  • X ranges from 0.1 to 0.7, such as 0.2, 0.3, 0.4, 0.5 or 0.6;
  • the lattice constant of the source/drain region 107 is slightly smaller than the lattice of the material of the device layer 103 a constant, thereby generating tensile stress on the channel.
  • the source/drain region 107 may be Si: C, and the atomic percentage of C may range from 0.2% to 2%, such as 0.5%, 1%, or 1.5%. .
  • the source/drain regions 107 may be formed by, for example, ion implantation or in-situ doping, or may be simultaneously implanted in the source/drain regions 107 during the growth process. Miscellaneous to form source/drain regions 107.
  • the doping impurity is boron; for Si:C, the doping impurity is phosphorus or arsenic.
  • the lifted may be formed by epitaxial growth.
  • the source/drain regions 108, that is, the tops of the source/drain regions are higher than the bottom of the gate stack.
  • the fabrication of the semiconductor device is then completed in accordance with the steps of a conventional semiconductor fabrication process. For example, a metal silicide layer is formed on the source/drain regions; an interlayer dielectric layer is deposited to cover the source/drain regions and the gate stack; and the interlayer dielectric layer is etched to expose the source/drain regions to form contact holes; A contact metal is filled in the contact hole.
  • the bottom of the source/drain region 107 is located in the insulating layer 102 of the SOI substrate 100, and a crystalline dielectric layer 105 is present between the source/drain region 107 and the base layer 101, which is effective.
  • the bottom of the embedded source/drain region 107 is isolated from the SOI substrate 100, thereby eliminating the leakage current path between the source/drain region 107 and the SOI substrate 100, and suppressing leakage current generation;
  • the source/drain region 107 penetrates the device layer 103 of the SOI substrate 100 and a portion of the insulating layer 102, the disadvantages of forming a thinner source/drain region in the device layer only in the prior art are effectively increased.
  • the depth of the source/drain regions reduces the contact resistance of the source/drain regions and improves the performance of the semiconductor device.
  • the present invention also provides a semiconductor device, with reference to FIG.
  • the semiconductor device includes an SOI substrate 100, a gate stack, source/drain regions 107, and a crystalline dielectric layer 105.
  • the SOI substrate 100 includes a base layer 101, an insulating layer 102 over the base layer 101, and a device layer 103 over the insulating layer 102.
  • the thickness of the device layer 103 Preferably, the thickness of the device layer 103.
  • the gate stack is formed on the SOI substrate 100, the gate stack includes a gate dielectric layer 210, a gate 220, and a cap layer 230; the source/drain region 107 is formed at the bottom of the SOI village 100 is located on both sides of the gate stack; the source/drain regions 107 are formed in the SOI substrate 100 on both sides of the gate stack, wherein the source/drain regions 107 penetrate the device a layer 103 extending between the upper surface and the lower surface of the insulating layer 102; the crystalline dielectric layer 105 being located between the source/drain region 107 and the base layer 101, wherein the crystal
  • the depth of the dielectric layer 105 deep into the base layer 101 ranges from 100 nm to lum; the crystalline dielectric layer 105 material includes, but is not limited to, one or any combination of Gd 2 0 3 , TrHf0 4 , Nd 2 0 3 , Or other material having a lattice constant close to the base layer 101.
  • the source/drain region 107 includes doping, wherein the lattice constant of the doped source/drain region 107 is slightly larger or slightly smaller than the lattice constant of the material of the device layer 103, so that the trench can be The track generates stress and improves the mobility of carriers in the channel.
  • the lattice constant of the source/drain region 107 is slightly larger than the lattice constant of the material of the device layer 103, thereby generating compressive stress to the channel.
  • the source/drain region 107 may be Si.
  • Gex, X ranges from 0.1 to 0.7, such as 0.2, 0.3, 0.4, 0.5 or 0.6; for NMOS devices, the source/drain region 107 has a lattice constant slightly smaller than that of the device layer 103 material. a lattice constant, thereby generating tensile stress on the channel, for example, the source/drain region 107 may be Si: C, C atomic number The percentage ranges from 0.2% to 2%, such as 0.5%, 1%, or 1.5%.
  • the source/drain regions may be source/drain regions 107 in the shape of Sigma, with reference to FIG. As shown, when the source/drain regions 107' are in the Sigma shape, the source/drain regions 107' may be closer to the channel center of the semiconductor device, thereby making the source/drain regions 107 better for the channel. The effect of stress.
  • the source/drain regions may be elevated source/drain regions, ie, the top of the source/drain regions is higher than the bottom of the gate stack, with reference to the source/drain of the boost in FIGS. 9 and 11. Area 108.
  • each part in each embodiment of the semiconductor device may be the same as those described in the foregoing method for forming a semiconductor device, and will not be further described. While the invention has been described with respect to the preferred embodiments and the embodiments of the present invention, it is understood that various changes, substitutions and modifications can be made to the embodiments without departing from the spirit and scope of the invention. For other examples, it will be readily understood by those skilled in the art that the order of the process steps may be varied while remaining within the scope of the invention.

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Abstract

本发明提供一种半导体器件的制造方法，包括：提供SOI衬底，所述SOI衬底包括基底层、位于所述基底层之上的绝缘层、以及位于所述绝缘层之上的器件层；在所述SOI衬底上形成栅堆叠；以所述栅堆叠为掩模，刻蚀所述SOI衬底的器件层、绝缘层以及部分基底层，在所述栅堆叠两侧形成凹陷；在所述凹陷内形成晶体介电层，所述晶体介电层的上表面低于所述绝缘层的上表面且不低于所述绝缘层的下表面；在所述晶体介电层之上形成源/漏区。本发明还提供一种半导体器件。本发明在消除了源/漏区与SOI衬底之间的漏电流路径的同时，也可以降低源/漏区的接触电阻。

Description

半导体器件及其制造方法
[0001]本申请要求了 2012年 8月 23 日提交的、 申请号为 201210304241.6、 发明名称为"半导体器件及其制造方法"的中国专利申请的优先权， 其全部 内容通过引用结合在本申请中。 技术领域
[0002]本发明涉及半导体制造技术，尤其涉及一种半导体器件及其制造方 法。 背景技术
[0003]在现有的半导体制造工艺中，提高半导体器件性能的一个重要手段 是在半导体器件内形成具有应力的源 /漏区， 对沟道产生压应力或者拉应 力， 以此改善沟道中载流子的迁移率。 下面将结合图 1(a)对实现该半导体 器件的具体方法进行描述： 提供一个具有栅堆叠的体硅村底 100, 首先刻 蚀该栅堆叠两侧的体硅村底 100 形成凹陷， 然后在该凹陷内嵌入例如掺 杂硼的 SiGe或掺杂磷或砷的 Si:C, 以形成具有应力的源 /漏区 110。
[0004]但是， 由于源 /漏区 110与体硅村底 100之间存在的漏电流会导致 半导体器件性能的下降，所以，在现有技术中采用 SOI(Silicon-On-Insulator) 村底代替体硅村底， 以减小源 /漏区与村底之间的漏电流。 请参考图 1(b), SOI村底 100，包括基底层 101、 绝缘层 102 以及器件层 103。 嵌入的源 / 漏区 110形成于 SOI村底 100，的器件层 103中， 由于绝缘层 102的存在， 将源 /漏区 110与基底层 101隔离开， 所以有效地削弱了漏电流路径 (请参 考图 l(a)、 图 1(b)中虚线所示的位置）， 从而使源 /漏区 110与村底 100，之 间的漏电流得到抑制。 但是， SOI村底器件层 103的厚度通常较薄， 所以 在 SOI村底 100，上形成的源 /漏区 110的深度由于受到器件层 103厚度的 限制也会较浅， 从而导致源 /漏区 110接触电阻的升高， 以及该半导体器 件性能的下降。 [0005]因此， 如何既可以降低源 /漏区的接触电阻， 又可以消除源 /漏区与 村底之间的漏电流， 是一个亟待解决的问题。 发明内容
[0006]本发明的目的是提供一种半导体器件及其制造方法， 在消除了源 / 漏区与 SOI村底之间的漏电流路径的同时， 也可以降低源 /漏区的接触电 阻。
[0007]根据本发明的一个方面， 提供一种半导体器件的制造方法， 该方法 包括以下步骤：
( a ) 提供 SOI村底， 所述 SOI村底包括基底层、 位于所述基底层之上的绝 缘层、 以及位于所述绝缘层之上的器件层；
( b ) 在所述 SOI村底上形成栅堆叠；
( c ) 以所述栅堆叠为掩模， 刻蚀所述 SOI村底的器件层、 绝缘层以及部 分基底层， 在所述栅堆叠两侧形成凹陷；
( d ) 在所述凹陷内形成晶体介电层， 所述晶体介电层的上表面低于所述 绝缘层的上表面且不低于所述绝缘层的下表面；
( e ) 在所述晶体介电层之上形成源 /漏区。
[0008]本发明另一方面还提出一种半导体器件， 包括：
[0009] SOI村底， 包括基底层、 位于所述基底层之上的绝缘层、 以及位于所 述绝缘层之上的器件层；
[0010]栅堆叠， 形成于所述 SOI村底之上；
[0011]源 /漏区， 形成于所述 SOI村底之中、 位于所述栅堆叠两侧， 其中所 述源 /漏区贯穿所述器件层， 并延伸至所述绝缘层的上表面和下表面之间； 以及
[0012]晶体介电层， 位于所述源 /漏区与所述基底层之间。
[0013]与现有技术相比， 本发明具有以下优点：
1)源 /漏区的底部位于 SOI村底的绝缘层内， 且在源 /漏区与 SOI村底 之间形成晶体介电层， 将源 /漏区的底部与 SOI村底隔离开， 从而有效地 消除了源 /漏区与 SOI村底之间的漏电流路径， 抑制了漏电流的产生；
2)通过在 SOI村底的器件层以及部分绝缘层内形成源 /漏区， 克服了 现有技术中仅仅在器件层中形成厚度较薄的源 /漏区的缺点， 有效地降低 了源 /漏区的接触电阻， 提高了半导体器件的性能。 附图说明
[0014]通过阅读参照以下附图所作的对非限制性实施例所作的详细描述， 本 发明的其它特征、 目的和优点将会变得更明显：
[0015]图 1(a)和图 1(b)为现有技术中半导体器件的剖面示意图；
[0016]图 2为根据本发明的半导体器件制造方法的流程图；
[0017]图 3至图 11为根据本发明的一个实施例按照图 2所示流程制造半 导体器件的各个阶段的剖面示意图。
[0018]附图中相同或相似的附图标记代表相同或相似的部件。 具体实施方式
[0019]下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类 似功能的元件。 下面通过参考附图描述的实施例是示例性的， 仅用于解 释本发明， 而不能解释为对本发明的限制。
[0020]下文的公开提供了许多不同的实施例或例子用来实现本发明的不 同结构。 为了筒化本发明的公开， 下文中对特定例子的部件和设置进行 描述。 当然， 它们仅仅为示例， 并且目的不在于限制本发明。 此外， 本 发明可以在不同例子中重复参考数字和 /或字母。 这种重复是为了筒化和 清楚的目的， 其本身不指示所讨论各种实施例和 /或设置之间的关系。 此 外， 本发明提供了的各种特定的工艺和材料的例子， 但是本领域普通技 术人员可以意识到其他工艺的可应用于性和 /或其他材料的使用。 另外， 以下描述的第一特征在第二特征之 "上"的结构可以包括第一和第二特征 形成为直接接触的实施例， 也可以包括另外的特征形成在第一和第二特 征之间的实施例， 这样第一和第二特征可能不是直接接触。 应当注意， 在附图中所图示的部件不一定按比例绘制。 本发明省略了对公知组件和 处理技术及工艺的描述以避免不必要地限制本发明。
[0021]图 2为根据本发明的半导体器件制造方法的流程图， 图 3至图 11 为根据本发明的一个实施例按照图 2 所示流程制造半导体器件的各个阶 段的剖面示意图。 下面， 将结合图 3至图 11对图 2中形成半导体器件的 方法进行具体地描述。 需要说明的是， 本发明实施例的附图仅是为了示 意的目的， 因此没有必要按比例绘制。
[0022]在步骤 S101中， 提供 SOI村底 100, 所述 SOI村底 100包括基底 层 101、 位于所述基底层 101 之上的绝缘层 102、 以及位于所述绝缘层 102之上的器件层 103。
[0023]具体地， 如图 3所示， 在本实施例中， 所述基底层 101为单晶硅。 在其他实施例中， 所述基底层 101 还可以包括其他基本半导体， 例如 锗。 或者， 所述基底层 101 还可以包括化合物半导体， 例如， 碳化硅、 砷化镓、 砷化铟或者磷化铟。 典型地， 所述基底层 101 的厚度可以约为 但不限于几百微米， 例如从 0.5mm- 1.5mm的厚度范围。
[0024]所述绝缘层 102可以为 Si02、 氮化硅或者其他任何适当的绝缘材 料， 典型地， 所述绝缘层 102的厚度范围为 200nm-300nm。
[0025]所述器件层 103 可以为所述基底层 101 包括的半导体中的任何一 种。 在本实施例中， 所述器件层 103 为单晶硅。 在其他实施例中， 所述 器件层 103 还可以包括其他基本半导体或者化合物半导体。 典型地， 所 述器件层 103的厚度大于 20nm。
[0026]在本实施例中， 所述 SOI村底 100为超薄体 SOI(Ultra-Thin-Body SOI, UTBSOI)村底， 其具有极薄的器件层， 厚度通常小于 10nm, 有利于 控制源 /漏区所形成的深度， 从而减小短沟道效应。
[0027]特别地， 在所述 SOI村底 100中形成隔离区， 例如浅沟槽隔离（STI) 结构 120, 以便电隔离连续的半导体器件。
[0028]在步骤 S102中， 在所述 SOI村底 100上形成栅堆叠。 [0029]具体地， 如图 4所示， 在所述 SOI村底 100之上形成栅堆叠， 其 包括栅介质层 210、 栅极 220 以及覆盖层 230。 所述栅介质层 210位于 SOI 村底 100 上， 可以为高 K介质， 例如， Hf02、 HfSiO、 HfSiON、 HfTaO、 HfTiO、 HfZrO, A1203、 La203、 Zr02、 LaAlO 中的一种或其组 合。 在另一个实施例中， 还可以是热氧化层， 包括氧化硅或氮氧化硅； 所述栅极介质层 104的厚度可以为 2nm -10nm, 如 5nm或 8nm。 而后在 所述栅介质层 210上形成栅极 220, 所述栅极 220可以是金属栅极， 例如 通过沉积 TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax 中的一种或其组合来形成， 厚度可以为 10nm -80nm, 如 30nm或 50nm。 在另一个实施例中， 所述栅极 220还可以是伪 栅极， 例如通过沉积 Poly-Si、 Poly-SiGe、 非晶硅和 /或氧化物而形成。 最后， 在栅极 220上形成覆盖层 230, 例如通过沉积氮化硅、 氧化硅、 氮 氧化硅、 碳化硅及其组合形成， 用以保护栅极 220 的顶部区域， 防止其 在后续的工艺中受到破坏。
[0030]优选地， 在所述栅堆叠的侧壁上形成侧墙 240, 用于将栅堆叠隔 开。 侧墙 240 可以由氮化硅、 氧化硅、 氮氧化硅、 碳化硅、 及其组合， 和 /或其他合适的材料形成。 侧墙 240可以具有多层结构。 侧墙 240可以 通过包括沉积-刻蚀工艺形成， 其厚度范围可以是 10nm -lOOnm , 如 30nm、 50nm或 80nm。
[0031]在步骤 S103中， 以所述栅堆叠为掩模， 刻蚀所述 SOI村底 100的 器件层 103、 绝缘层 102以及部分基底层 101 , 在所述栅堆叠两侧形成凹 陷 104。
[0032]如图 5(a)所示， 刻蚀所述 SOI村底 100的器件层 103、 绝缘层 102 以及部分基底层 101 , 在所述栅堆叠两侧形成凹陷 104。 具体地， 以所述 栅堆叠为掩模， 通过各向异性的干法刻蚀和 /或湿法刻蚀的方式， 刻蚀栅 堆叠两侧的所述 SOI村底 100, 以形成贯穿于所述器件层 103和绝缘层 102、 且深入至所述基底层 101 内部的凹陷 104。 所述凹陷 104深入至所 述基底层 101 内部的深度范围为 lOOnm至 lum。 湿法刻蚀工艺包括四甲 基氢氧化铵 (TMAH)、 氢氧化钾 (KOH)或者其他合适刻蚀的溶液； 干法刻 蚀工艺包括六氟化硫 (SF6)、 溴化氢 (HBr)、 碘化氢 (HI)、 氯、 氩、 氦及其 组合， 和 /或其他合适的材料。 根据所述器件层 103、 绝缘层 102以及基 底层 101的材料， 可以分别选择适当的方式进行刻蚀。
[0033]优选地， 可以交替使用各向同性和各向异性的刻蚀方式， 不但对 栅堆叠两侧的 SOI村底 100进行刻蚀， 还可以对侧墙 240下面的部分 SOI 村底 100进行刻蚀， 特别是 SOI村底 100中的器件层 103 , 使刻蚀后形成 的凹陷尽可能接近沟道中心， 例如， 图 5(b)中的凹陷 104，， 或者图 5(c) 中呈现 Sigma形状的凹陷 104"。 在后续的工艺中， 填充源 /漏区 107至所 述凹陷内， 所述源 /漏区 107越接近沟道中心， 对沟道中载流子所产生的 应力效果越好。 对所述侧墙 240下面部分、 特别是对 SOI村底 100中的 器件层 103进行刻蚀， 使凹陷 104接近沟道中心的步骤， 也可以在后续 形成源 /漏区的时候进行。
[0034]在步骤 S104中， 在所述凹陷 104内形成晶体介电层 105 , 所述晶 体介电层 105的上表面低于所述绝缘层 102的上表面且不低于所述绝缘 层 102的下表面。
[0035]具体地， 如图 6所示， 以所述基底层 101为籽晶， 通过外延生长或 者固态相变的方法， 在所述凹陷 104 内形成晶体绝缘材料 105，， 其中， 所述晶体绝缘材料 105，的上表面不高于所述栅堆叠的底部； 然后， 如图 7所示， 通过干法刻蚀和 /或湿法刻蚀的方式， 对所述晶体绝缘材料 105， 进行刻蚀， 以形成晶体介电层 105。 也可以通过例如控制所述晶体绝缘 材料 105，的生长时间等因素， 令所述晶体绝缘材料 105，生长到所需高度 后停止生长， 以形成所述晶体介电层 105。 所述晶体介电层 105的上表面 低于所述绝缘层 102的上表面， 且不低于所述绝缘层 102的下表面。 所 述晶体介电层 105材料包括但不限于 Gd203、 TrHf04 、 Nd203中的一种 或者任意组合， 或其它晶格常数与基底层 101 接近的材料。 所述晶体介 电层 105 的介电常数， 可以通过例如调整所述晶体介电层 105材料中成 分的比例进行调整， 从而使所述晶体介电层 105具有良好的绝缘性。 [0036]在步骤 S 105中， 在所述晶体介电层 105之上形成源 /漏区 107。
[0037]具体地， 如图 8所示， 以所述晶体介电层 105材料为籽晶， 通过外 延生长或者固态相变的方式在所述凹陷 104 内形成含掺杂的源 /漏区 107 , 填充所述凹陷 104。 在本发明的一个实施例中， 所述源 /漏区 107的 晶格常数不等于所述器件层 103材料的晶格常数。 当所述源 /漏区 107的 晶格常数稍大于或者稍小于所述器件层 103 材料的晶格常数时， 不但会 对沟道引入一定的应力， 还可以使所述源 /漏区 107很好地生长在所述晶 体介电层 105之上。 对于 PMOS器件来说， 所述源 /漏区 107的晶格常数 稍大于所述器件层 103 材料的晶格常数， 从而对沟道产生压应力， 例 如， 所述源 /漏区 107 可以为 SiuGex , X 的取值范围为 0.1 ~ 0.7 , 如 0.2、 0.3、 0.4、 0.5或 0.6; 对于 NMOS器件来说， 所述源 /漏区 107的晶 格常数稍小于所述器件层 103 材料的晶格常数， 从而对沟道产生拉应 力， 例如， 所述源 /漏区 107可以为 Si:C , C的原子数百分比的取值范围 为 0.2% ~ 2% , 如 0.5%、 1 %或 1.5 %。 在所述凹陷 104内形成源 /漏区 107 后， 可以通过例如离子注入或原位掺杂的方式形成源 /漏区 107 , 也可以 在源 /漏区 107生长过程中， 同时进行原位掺杂以形成源 /漏区 107。 对于 Si^Gex来说， 掺杂杂质为硼； 对于 Si:C来说， 掺杂杂质为磷或者砷。
[0038]优选地， 为了进一步提高该半导体器件的性能， 如图 9或图 1 1所 示， 在形成源 /漏区 107或源 /漏区 107，后， 可以通过外延生长的方式形成 提升的源 /漏区 108 , 即， 源 /漏区的顶部高于所述栅堆叠的底部。
[0039]随后按照常规半导体制造工艺的步骤完成该半导体器件的制造。 例如， 在源 /漏区上形成金属硅化物层； 沉积层间介质层以覆盖所述源 / 漏区以及栅堆叠； 刻蚀所述层间介质层暴露源 /漏区以形成接触孔； 然后 在所述接触孔内填充接触金属。
[0040]在上述步骤完成后， 源 /漏区 107的底部位于 SOI村底 100的绝缘 层 102中， 且在所述源 /漏区 107与基底层 101之间存在晶体介电层 105 , 有效地将嵌入的源 /漏区 107的底部与 SOI村底 100隔离开， 从而消除了 源 /漏区 107与 SOI村底 100之间的漏电流路径， 抑制了漏电流的产生； 此外， 由于源 /漏区 107贯穿 SOI村底 100的器件层 103以及部分绝缘层 102 , 克服了现有技术中仅仅在器件层中形成厚度较薄的源 /漏区的缺 点， 有效地增加了源 /漏区的深度， 从而降低了源 /漏区的接触电阻， 提 高了半导体器件的性能。
[0041]本发明还提供了一种半导体器件， 参考图 8。 如图所示， 所述半 导体器件包括 SOI村底 100、 栅堆叠、 源 /漏区 107以及晶体介电层 105。 其中， 所述 SOI村底 100包括基底层 101、 位于所述基底层 101之上的绝 缘层 102、 以及位于所述绝缘层 102之上的器件层 103 , 优选地， 所述器 件层 103的厚度小于 10nm; 所述栅堆叠形成于所述 SOI村底 100之上， 所述栅堆叠包括栅介质层 210、 栅极 220 以及覆盖层 230; 所述源 /漏区 107形成于所述 SOI村底 100之中、 位于所述栅堆叠两侧； 所述源 /漏区 107形成于所述 SOI村底 100之中、 位于所述栅堆叠两侧， 其中所述源 / 漏区 107贯穿所述器件层 103 , 并延伸至所述绝缘层 102的上表面和下表 面之间； 所述晶体介电层 105 , 位于所述源 /漏区 107 与所述基底层 101 之间， 其中， 所述晶体介电层 105 深入所述基底层 101 的深度范围为 lOOnm 至 lum ; 所述晶体介电层 105 材料包括但不限于 Gd203、 TrHf04 、 Nd203中的一种或者任意组合， 或其它晶格常数与基底层 101 接近的材料。 在其他实施例中， 所述半导体器件还包括侧墙 240, 形成于 所述栅堆叠的侧壁上。
[0042]所述源 /漏区 107包含掺杂， 其中， 该含掺杂的源 /漏区 107的晶格 常数稍大于或者稍小于所述器件层 103 材料的晶格常数， 从而可以对沟 道产生应力， 改善所述沟道中载流子的迁移率。 对于 PMOS器件来说， 所述源 /漏区 107的晶格常数稍大于所述器件层 103材料的晶格常数， 从 而对沟道产生压应力， 例如， 所述源 /漏区 107可以为 Si Gex, X的取 值范围为 0.1 - 0.7, 如 0.2、 0.3、 0.4、 0.5或 0.6; 对于 NMOS器件来说， 所述源 /漏区 107的晶格常数稍小于所述器件层 103材料的晶格常数， 从 而对沟道产生拉应力， 例如， 所述源 /漏区 107可以为 Si:C, C的原子数 百分比的取值范围为 0.2% ~ 2% , 如 0.5%、 1 %或 1.5%。
[0043]优选地， 所述源 /漏区可以是呈 Sigma形状的源 /漏区 107，， 参考图 10。 如图所示， 当所述源 /漏区 107'为 Sigma形状的时候， 源 /漏区 107' 可以更加接近半导体器件的沟道中心， 从而使源 /漏区 107，对沟道产生更 好的应力效果。
[0044]优选地， 所述源 /漏区可以为提升的源 /漏区， 即， 源 /漏区的顶部 高于所述栅堆叠的底部， 参考图 9和图 11中提升的源 /漏区 108。
[0045]其中， 对半导体器件各实施例中各部分的结构组成、 材料及形成 方法等均可与前述半导体器件形成方法实施例中描述的相同， 不再赘 述。 虽然关于示例实施例及其优点已经详细说明， 应当理解在不脱离本 发明的精神和所附权利要求限定的保护范围的情况下， 可以对这些实施 例进行各种变化、 替换和修改。 对于其他例子， 本领域的普通技术人员 应当容易理解在保持本发明保护范围内的同时， 工艺步骤的次序可以变 化。
[0046]此外， 本发明的应用范围不局限于说明书中描述的特定实施例的 工艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内 容， 作为本领域的普通技术人员将容易地理解， 对于目前已存在或者以 后即将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其 中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相 同的结果， 依照本发明可以对它们进行应用。 因此， 本发明所附权利要 求旨在将这些工艺、 机构、 制造、 物质组成、 手段、 方法或步骤包含在 其保护范围内。

Claims

权 利 要 求
1. 一种半导体器件的制造方法， 包括：
(a) 提供 SOI村底（100) , 所述 S0I村底（100)包括基底层（101)、 位于 所述基底层（101)之上的绝缘层（102)、 以及位于所述绝缘层（102)之上的器 件层（103) ;
(b) 在所述 SOI村底（100)上形成栅堆叠；
(c) 以所述栅堆叠为掩模， 刻蚀所述 S0I村底（100)的器件层（103)、 绝 缘层（102)以及部分基底层（101) , 在所述栅堆叠两侧形成凹陷（104)；
(d) 在所述凹陷（104)内形成晶体介电层（105) , 所述晶体介电层（105) 的上表面低于所述绝缘层（102)的上表面且不低于所述绝缘层（102)的下表 面；
(e) 在所述晶体介电层（105)之上形成源 /漏区（107)。
2. 根据权利要求 1 所述的制造方法， 其中， 在所述步骤 b)之后还包 括：
(f) 在所述栅堆叠侧壁上形成侧墙（240
3. 根据权利要求 1或 2所述的制造方法， 其中所述 S0I村底（100)的器 件层（103)的厚度小于 10nm。
4. 根据权利要求 1或 2所述的制造方法， 其中：
所述凹陷（104)嵌入所述基底层（101)内部的深度范围为 l OOnm至 1
5. 根据权利要求 1或 2所述的制造方法， 其中， 在所述凹陷（104)内形 成晶体介电层（105)的步骤包括：
通过外延生长或者固态相变的方法， 在所述凹陷（104)内形成晶体绝缘 材料（105， ) , 其中， 所述晶体绝缘材料（105， ）的上表面不高于所述栅堆 叠的底部； 以及
通过干法刻蚀和 /或湿法刻蚀的方式， 对所述晶体绝缘材料（105， ）进行 刻蚀， 以形成晶体介电层（105
6. 根据权利要求 5所述的制造方法， 其中： 所述晶体介电层（1 Q5)的材料包括 Gd203、 TrHf04 、 Nd203中的一种或者任 意组合， 或其它晶格常数与基底层（101)接近的材料。
7. 根据权利要求 4 所述的制造方法， 还包括所述凹陷（104)在器件层 (103)的侧壁形成 S igma形状。
8. 根据权利要求 1所述的制造方法， 其中：
所述源 /漏区（107)的晶格常数不等于所述器件层（103)材料的晶格常 数。
9. 根据权利要求 8所述的制造方法， 其中：
对于 N型器件， 所述源 /漏区（107)的晶格常数小于所述器件层（103)材 料的晶格常数； 对于 P型器件， 所述源 /漏区（107)的晶格常数大于所述器件 层（103)材料的晶格常数。
10. 根据权利要求 8或 9所述的制造方法， 其中：
所述源 /漏区（107)包括 S iGe或者 S i: C中的一种。
11. 根据权利要求 1所述的制造方法， 还包括在形成源 /漏区（107)后形 成提升的源 /漏区（108
12. 一种半导体器件， 包括：
S0I 村底（100) , 包括基底层（101)、 位于所述基底层（101)之上的绝缘 层（102)、 以及位于所述绝缘层（102)之上的器件层（103)；
栅堆叠， 形成于所述 S0I村底（100)之上；
源 /漏区（107) , 形成于所述 S0I 村底（100)之中、 位于所述栅堆叠两
(102)的上表面和下表面之间； 以及
晶体介电层（105) , 位于所述源 /漏区（107)与所述基底层（101)之间。
13. 根据权利要求 12所述的半导体器件， 还包括：
侧墙（240) , 形成于所述栅堆叠的侧壁上。
14. 根据权利要求 11或 12所述的半导体器件， 其中所述 S0I村底（100) 的器件层（103)的厚度小于 10
15. 根据权利要求 11或 12所述的半导体器件， 其中所述源 /漏区（107) 的形状为 S igma形状。
16. 根据权利要求 11或 12所述的半导体器件， 其中：
所述源 /漏区（107)的晶格常数不等于所述器件层（103)材料的晶格常 数。
17. 根据权利要求 16所述的半导体器件， 其中：
对于 N型器件， 所述源 /漏区（107)的晶格常数小于所述器件层（103)材 料的晶格常数； 对于 P型器件， 所述源 /漏区（107)的晶格常数大于所述器件 层（103)材料的晶格常数。
18. 根据权利要求 16或 17所述的半导体器件， 其中：
所述源 /漏区（107)包括 S iGe或者 S i: C中的一种。
19. 根据权利要求 11或 12所述的半导体器件， 其中， 所述源 /漏区为 提升源 /漏区。
20. 根据权利要求 11或 12所述的半导体器件， 其中：
所述晶体介电层（105)嵌入所述基底层（101)内部的深度范围为 1 OOnm至 1
21. 根据权利要求 20所述的半导体器件， 其中：
所述晶体介电层（1 Q5)的材料包括 Gd203 TrHf04 Nd203中的一种或者任 意组合， 或其它晶格常数与基底层 (101)接近的材料。
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101776926B1 (ko) * 2010-09-07 2017-09-08 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9721827B2 (en) * 2014-02-27 2017-08-01 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement with stress control and method of making
CN104599968B (zh) * 2015-01-09 2017-09-22 中航（重庆）微电子有限公司 场效应晶体管及其制备方法
US9768254B2 (en) * 2015-07-30 2017-09-19 International Business Machines Corporation Leakage-free implantation-free ETSOI transistors
FR3040538A1 (fr) 2015-08-24 2017-03-03 St Microelectronics Crolles 2 Sas Transistor mos et son procede de fabrication
US9929266B2 (en) 2016-01-25 2018-03-27 International Business Machines Corporation Method and structure for incorporating strain in nanosheet devices
US9685535B1 (en) 2016-09-09 2017-06-20 International Business Machines Corporation Conductive contacts in semiconductor on insulator substrate
CN106298778A (zh) * 2016-09-30 2017-01-04 中国科学院微电子研究所 半导体器件及其制造方法及包括该器件的电子设备
US10297675B1 (en) 2017-10-27 2019-05-21 Globalfoundries Inc. Dual-curvature cavity for epitaxial semiconductor growth
US10355104B2 (en) 2017-10-27 2019-07-16 Globalfoundries Inc. Single-curvature cavity for semiconductor epitaxy
US11824099B2 (en) * 2020-06-15 2023-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Source/drains in semiconductor devices and methods of forming thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060084235A1 (en) * 2004-10-15 2006-04-20 Freescale Semiconductor, Inc. Low rc product transistors in soi semiconductor process
CN1945854A (zh) * 2005-09-13 2007-04-11 英飞凌科技股份公司 应变半导体器件及其制造方法
CN101300670A (zh) * 2005-10-31 2008-11-05 先进微装置公司 在薄soi晶体管中嵌入的应变层以及其形成方法
CN102842493A (zh) * 2011-06-20 2012-12-26 中国科学院微电子研究所 一种半导体结构及其制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3621695B2 (ja) * 2002-07-29 2005-02-16 株式会社東芝 半導体装置及び素子形成用基板
US7309660B2 (en) * 2004-09-16 2007-12-18 International Business Machines Corporation Buffer layer for selective SiGe growth for uniform nucleation
US7592231B2 (en) * 2006-08-01 2009-09-22 United Microelectronics Corp. MOS transistor and fabrication thereof
US7691752B2 (en) * 2007-03-30 2010-04-06 Intel Corporation Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed thereby
US7951657B2 (en) * 2009-05-21 2011-05-31 International Business Machines Corporation Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor
CN102237396B (zh) * 2010-04-27 2014-04-09 中国科学院微电子研究所 半导体器件及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060084235A1 (en) * 2004-10-15 2006-04-20 Freescale Semiconductor, Inc. Low rc product transistors in soi semiconductor process
CN1945854A (zh) * 2005-09-13 2007-04-11 英飞凌科技股份公司 应变半导体器件及其制造方法
CN101300670A (zh) * 2005-10-31 2008-11-05 先进微装置公司 在薄soi晶体管中嵌入的应变层以及其形成方法
CN102842493A (zh) * 2011-06-20 2012-12-26 中国科学院微电子研究所 一种半导体结构及其制造方法

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