WO2011131053A1 - 一种源漏区、接触孔及其形成方法 - Google Patents

一种源漏区、接触孔及其形成方法 Download PDF

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Publication number
WO2011131053A1
WO2011131053A1 PCT/CN2011/071086 CN2011071086W WO2011131053A1 WO 2011131053 A1 WO2011131053 A1 WO 2011131053A1 CN 2011071086 W CN2011071086 W CN 2011071086W WO 2011131053 A1 WO2011131053 A1 WO 2011131053A1
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Prior art keywords
region
source
contact hole
substrate
semiconductor layer
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PCT/CN2011/071086
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English (en)
French (fr)
Inventor
尹海洲
朱慧珑
骆志炯
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中国科学院微电子研究所
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Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to GB1122081.1A priority Critical patent/GB2493226B/en
Priority to US13/119,074 priority patent/US8692335B2/en
Priority to CN2011900000533U priority patent/CN202585380U/zh
Publication of WO2011131053A1 publication Critical patent/WO2011131053A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66696—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a source/drain region, a contact hole, and a method of forming the same. Background technique
  • the source and drain regions 40 may be composed of a semiconductor material, and the source and drain regions 40 are located in a gate stack structure (the gate stack structure includes a gate dielectric layer 12 formed on the substrate 10, formed in the a gate electrode 14 on the gate dielectric layer 12, and two sides of the sidewall dielectric layer 12 surrounding the gate dielectric layer 12 and the gate electrode 14 are embedded in the substrate 10, the actual height and target of the source and drain regions 40 The difference between the heights is less than the error criterion.
  • the contact hole 30 connected to the source/drain region 40 is formed in the interlayer dielectric layer 20, after the contact hole 30 is formed, in the source/drain region 40
  • the surface layer forms a contact region 18 (e.g., a metal silicide) through which the contact hole 30 is connected to the source and drain regions 40, thereby reducing how the resistance of the contact region 18 is reduced.
  • a contact region 18 e.g., a metal silicide
  • the present invention provides a source and drain region and a method of forming the same, which may be formed when a contact region is formed on the source and drain regions to carry a contact hole having a certain size, and the contact hole and the contact region are increased.
  • Contact area reducing contact resistance;
  • the present invention provides a contact hole and a method of forming the same, which can have an increased contact area when the contact hole is connected to the source and drain regions via the contact region, and Small contact resistance.
  • a source and drain region provided by the present invention is composed of a semiconductor material, and the source and drain regions are located in a gate stack structure Both sides are embedded in the substrate, and the source and drain regions include:
  • the first region of at least a portion of the thickness being located within the substrate
  • the second zone being formed on the first zone, the material of the second zone being different from the material of the first zone.
  • the second region includes an auxiliary layer, and the auxiliary layer is configured to carry the contact hole when the embedded contact hole is formed on the source/drain region;
  • the stop layer being used to terminate the contact hole above a boundary between the gate stack structure and the substrate.
  • the first region material is SiGe
  • the stop layer is Si
  • the auxiliary layer is SiGe
  • the first region material is S. x C x
  • the stop layer is Si
  • the auxiliary layer is SiGe.
  • the first region provides a compressive stress to a channel region of the PMOS device, and the first region provides a tensile stress to a channel region of the NMOS device.
  • the material of the first region in the PMOS device is different from the material of the first region in the NMOS device.
  • the material of the second region in the PMOS device is the same material as the second region of the NMOS device.
  • the invention provides a contact hole, the contact hole is embedded in the source/drain region, and a boundary line between the bottom surface of the contact hole and the source/drain region is higher than or coincides with a boundary between the gate stack structure and the substrate. .
  • a boundary line between a bottom surface of the contact region and the source/drain region is higher than or coincides with the gate stack structure and the The boundary line of the substrate.
  • the invention provides a contact hole, the contact hole is embedded in a source/drain region, and a boundary line between a bottom surface of the contact hole and the source/drain region is higher than or coincides with a boundary line between the gate stack structure and the substrate;
  • the source and drain regions are composed of a semiconductor material, and the source and drain regions are located on both sides of the gate stack structure and embedded in the substrate, and an upper surface of the source and drain regions is between the gate stack structure and the substrate
  • the height difference is greater than the difference between the actual height of the source and drain regions and the target height.
  • a method for forming a source and drain region provided by the present invention includes:
  • a second semiconductor layer is formed on the first semiconductor layer, and a material of the second semiconductor layer is different from a material of the first semiconductor layer.
  • the step of forming the second semiconductor layer comprises: forming an auxiliary layer, wherein the auxiliary layer is configured to carry the contact hole when forming an embedded contact hole on the source/drain region;
  • a stop layer is formed, the stop layer being used to terminate the contact hole above a boundary between the gate stack structure and the substrate.
  • the first region material is SiGe
  • the stop layer is Si
  • the auxiliary layer is SiGe
  • the first region material is SiC
  • the stop layer is Si
  • the auxiliary layer is SiGe.
  • the first semiconductor layer provides a compressive stress to a channel region of the PMOS device, and the first semiconductor layer provides a tensile stress to a channel region of the NMOS device.
  • a material of the first semiconductor layer in the PMOS device is different from a material of the first semiconductor layer in the NMOS device.
  • a material of the second semiconductor layer in the PMOS device is the same as a material of the second semiconductor layer in the NMOS device.
  • a method for forming a contact hole provided by the present invention includes:
  • a contact hole is embedded in the source/drain region, and a boundary line between the bottom surface of the contact hole and the source/drain region is higher than or coincides with a boundary line between the gate stack structure and the substrate.
  • a boundary line between a bottom surface of the contact region and the source/drain region is higher than or coincides with the gate stack structure and the The boundary line of the substrate.
  • a method for forming a contact hole provided by the present invention includes: forming a trench on both sides of a gate stack structure in a substrate; Forming a semiconductor layer, a height difference between an upper surface of the semiconductor layer and a boundary line between the gate stack structure and the substrate being greater than a difference between an actual height of the semiconductor layer and a target height;
  • a contact hole is embedded in the semiconductor layer, and a boundary line between the bottom surface of the contact hole and the semiconductor layer is higher than or coincident with a boundary line between the gate stack structure and the substrate.
  • a boundary line between a bottom surface of the contact region and the source/drain region is higher than or coincides with the gate stack structure and the The boundary line of the substrate.
  • the technical solution provided by the present invention has the following advantages: by making the source/drain region include a first region having at least a portion of a thickness in the substrate and a portion formed on the first region a second region, and a material of the second region is different from a material of the first region (in other words, an upper surface of the source/drain region is higher than a boundary line between the gate stack structure and the substrate),
  • a groove is formed in the surface of the source/drain region, and a contact region is formed at the bottom wall and the sidewall of the groove, so that the contact hole is connected to the source via the bottom surface thereof.
  • the portion of the side surface adjacent to the bottom surface may be connected to the source and drain regions, and the contact area is increased compared to the technical solution of connecting the source and drain regions only through the bottom surface thereof, thereby facilitating the reduction.
  • a small contact resistance; _& can be formed in the second region by selecting a suitable etchant to stop on the first region, so that the thickness can be adjusted by adjusting the thickness of the second region The shape of the groove, with flexible adjustment Size of the area;
  • the contact hole on the source and drain regions can be synchronously formed on the CMOS device including the PMOS device and the NMOS device,
  • the small contact resistance also facilitates the process.
  • FIG. 1 is a schematic view showing the structure of a contact hole formed on a source/drain region in the prior art
  • FIG. 2 is a schematic structural view of a first embodiment of a source and drain region of the present invention
  • FIG. 3 is a schematic structural view of a second embodiment of a source and drain region of the present invention.
  • FIG. 4 is a schematic structural view of a first embodiment of a contact hole according to the present invention
  • Figure 5 is a schematic view showing the structure of a second embodiment of the contact hole of the present invention
  • FIG. 6 to FIG. 8 are schematic diagrams showing the intermediate structure when the steps of the first embodiment of the method for forming the source and drain regions of the present invention are performed;
  • Figure 9 is a schematic view showing the intermediate structure formed after the second embodiment of the method for forming the source and drain regions of the present invention.
  • Figures 10 to 11 are the middle portions of the first embodiment of the method for forming the contact holes of the present invention.
  • Fig. 12 is a view showing the structure of a second embodiment of the method for forming a contact hole of the present invention. detailed description
  • the present invention may repeat reference numerals and/or letters in different embodiments. This repetition is for the purpose of brevity and clarity and does not in itself indicate the relationship between the various embodiments and/or arrangements discussed.
  • the source and drain regions are composed of a semiconductor material, and the source and drain regions are located on both sides of the gate stack structure and embedded in the substrate 100, and the source and drain regions are included.
  • a first region 120 the first region 120 is located in the substrate 100;
  • a second region the second region is formed on the first region 120; wherein the second region comprises: an auxiliary layer 144, the auxiliary layer 144 is configured to carry the contact hole when the embedded contact hole is formed on the source and drain regions; the stop layer 142, the stop layer 142 is used to terminate the contact hole in the gate stack
  • the structure is above the boundary line of the substrate 100; in the CMOS device including the source and drain regions, the first region 120 provides a compressive stress to a channel region of the PMOS device, the first region 120 to the NMOS device The channel region provides tensile stress; the material of the first region 120 in the PMOS device is different from the material of the first region 120 in the NMOS device; the material
  • the target height refers to the theoretical height required for the process, eg, to meet the design needs
  • the height of the source and drain regions is 2000 angstroms, and the 2000 angstrom is the target height
  • the error standard means an error range that satisfies the process requirements, for example, under certain process conditions, the height of the source and drain regions is defined.
  • the deviation is less than or equal to ⁇ 5%, it is considered that the height of the source and drain regions meets the process requirement, and less than or equal to ⁇ 5% is the error criterion
  • the actual height means that in practice, the target is obtained.
  • the height obtained to meet the process requirements such as the target height of 2000 angstroms, the error standard is less than or equal to ⁇ 5%, for the source and drain zones with a height of 2050 angstroms that meet the process requirements, this 2050 The angstrom is the actual height of the source and drain regions.
  • the substrate 100 has undergone a processing operation including pre-cleaning, forming a well region, and forming a shallow trench isolation region.
  • the substrate 100 is silicon.
  • the substrate 100 may further include other compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide or antimony phosphide; further, the substrate 100 preferably includes an epitaxial layer;
  • the substrate 100 may also include a silicon-on-insulator (SOI) structure.
  • SOI silicon-on-insulator
  • the gate stack structure includes a gate dielectric layer 102 formed on the substrate 100, a gate electrode 104 formed on the gate dielectric layer 102, and a sidewall spacer surrounding the gate dielectric layer 102 and the gate 104 106.
  • the gate 104 includes a polysilicon gate, a polysilicon dummy gate, or a metal gate. (Note: In the present document, when the source/drain region embodiment is described, the gate 104 is a polysilicon gate or a polysilicon dummy gate; When describing a contact hole embodiment, the gate 104 can be a polysilicon gate or a metal gate).
  • the gate dielectric layer 102 may be selected from a ruthenium-based material such as one or a combination of Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO or HfZi'O.
  • the sidewall 106 may comprise one or a combination of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide.
  • the side wall 106 can have a multi-layered structure.
  • the gate dielectric layer 102 and the sidewall spacers 106 and the above-described processing operations can be formed or performed using conventional processes.
  • the semiconductor material constituting the source and drain regions includes Si, SiGe C Ge may have a percentage of atoms of 40%, and the Ge content may be flexibly adjusted according to process requirements, such as 30%-50%, which is not specifically described in this document.
  • the atomic percentage of Ge is the same as this, and will not be described again) or Si 1-x C x (the atomic percentage of C can be 0-2%, and the content of C can be flexibly adjusted according to the process needs, and there is no special in this document. At the description, the atomic percentage of C is the same, and will not be described again.
  • the semiconductor material may be a semiconductor material that has been ion-doped, for example, Si, SiGe or Si 1-x C x which may be N-type or P-type.
  • the ion doping operation may be directly formed in the process of generating the semiconductor material (eg, injecting a reactant containing a dopant ion component into a reactant that generates the semiconductor material); After the material is formed by an ion implantation process, the ion doping operation can be performed by any conventional ion implantation process, and will not be described again.
  • the material of the first region 120 in the PMOS device is SiGe
  • the material of the first region 120 in the NMOS device is SiL X Cx
  • the first region 120 can be made to provide compressive stress to the channel region of the PMOS device, and to provide tensile stress to the channel region of the NMOS device, which is advantageous for improving CMOS device performance.
  • the material of the first region 120 in the PMOS device and the NMOS device may also be selected from other different semiconductor materials.
  • the material of the first region 120 in the PMOS device may also be the same as the material of the first region 120 in the NMOS device.
  • the first region 120 is provided to the channel region of the PMOS device.
  • the compressive stress while providing a tensile stress to the channel region of the NMOS device, can be formed using different processes to form the material of the first region 120 in the PMOS device and the NMOS device.
  • the material of the second region in the PMOS device is the same as the material of the second region in the NMOS device, that is, the materials of the auxiliary layer 144 and the stop layer 142 are respectively the same;
  • the PMOS device is formed in synchronization with the second region of the NMOS device. In addition to reducing the contact resistance, it also facilitates the process.
  • the material of the first region 120 in the PMOS device is SiGe
  • the material of the auxiliary layer 144 is preferably SiGe.
  • the stop layer 142 may be Si (in practice, for a 32 nanometer process, the stop layer 142 may have a thickness of 5 nanometers).
  • the auxiliary layer 144 is configured to carry the contact hole when the embedded contact hole is formed on the source and drain regions; the stop layer 142 is used to terminate the contact hole in the gate stack structure and the Above the boundary line of the substrate.
  • the material of the second region in the PMOS device and the NMOS device may also be different, that is, the material of the auxiliary layer 144 and/or the stop layer 142 may be different; Time, The PMOS device and the second region of the NMOS device are separately formed.
  • a boundary line between the stop layer 142 and the first region 120 may coincide with a boundary line between the gate stack structure and the substrate 100, or may be located at the gate.
  • the stack structure is above the boundary line of the substrate 100.
  • the silicide layer may be formed by performing an annealing operation after depositing a metal on the source and drain regions, the metal material including one or a combination of Co, Ni, Mo, Pt or W) and the source and drain regions
  • a boundary line between the gate stack structure and the substrate 100 may be formed to reduce stress loss in the channel region of the device, thereby increasing carrier mobility.
  • the source and drain regions are composed of a semiconductor material, and the source and drain regions are located on both sides of the gate stack structure and embedded in the substrate 100, the source and drain regions.
  • the first region 120 includes at least a portion of the thickness of the first region 120 in the substrate 100; the second region 140, the second region 140 is formed on the first region 120, the second The material of zone 140 is different from the material of first zone 120.
  • the material of the first region 120 in the PMOS device is different from the material of the first region 120 in the NMOS device.
  • the material of the second region 140 in the PMOS device is the same as the material of the second region 140 in the NMOS device.
  • the description of the semiconductor material, the gate stack structure, the substrate 100, and the first region 120 is the same as the foregoing embodiment, and will not be described again.
  • the material of the second region 140 in the PMOS device is the same as the material of the second region 140 in the NMOS device; in other words, the PMOS device and the NMOS device are in the same manner.
  • the second zone 140 is formed synchronously. In addition to reducing the contact resistance, it also facilitates the process.
  • the material of the first region 120 in the PMOS device is SiGe
  • the material of the first region 120 in the NMOS device is Si ⁇ Cx
  • the PMOS device and the NMOS device are described.
  • the material of the second region 140 may be Si.
  • the material of the second region 140 is different from the material of the first region 120, so that the source is subsequently
  • a contact hole formed on the drain region terminates above a boundary line between the gate stack structure and the substrate.
  • the groove carrying the contact hole may be formed in the second region 140 to stop on the first region 120 by selecting a suitable etchant, so that the thickness of the second region 140 may be adjusted.
  • the topography of the groove is adjusted to flexibly adjust the size of the contact area.
  • a boundary line between the second region 140 and the first region 120 may coincide with a boundary line of the gate stack structure and the substrate, or may be located at a boundary line between the gate stack structure and the substrate 100.
  • the boundary between the second region 140 and the first region 120 and the boundary between the gate stack structure and the substrate 100 coincide, the technical solution provided by the present invention and the existing source/drain region forming process are facilitated.
  • the boundary line between the second region 140 and the first region 120 is located above the boundary line between the gate stack structure and the substrate 100, the embedding in the second region 140 may be formed by an adjustment process.
  • a boundary line between the contact region introduced to reduce the contact resistance between the conductive material (such as metal) filling the contact hole and the source/drain region and the source and drain regions may be formed in the Above the boundary between the gate stack structure and the substrate, it is advantageous to reduce the stress loss of the channel region of the device, thereby improving the mobility of carriers.
  • the present invention also provides a contact hole.
  • the interlayer dielectric layer 180 is patterned to form a through-through.
  • the interlayer dielectric layer 180 terminates in a contact hole 182 in the source and drain regions.
  • the boundary line 1824 of the contact hole 182 and the source and drain regions is higher than the gate stack.
  • a boundary line between the contact hole 182 and the source and drain regions may coincide with a boundary line between the gate stack structure and the substrate 100.
  • the technical solution provided by the present invention is compatible with the existing contact hole forming process.
  • the filling process may be performed to reduce the filling after the contact hole 182 is formed.
  • a boundary line between the contact region 184 introduced by the contact resistance between the conductive material (such as metal) of the contact hole 182 and the source/drain region and the source/drain region may be formed in the gate stack structure and Above the boundary line of the substrate, it is advantageous to reduce the stress loss in the channel region of the device, thereby increasing the mobility of carriers.
  • a boundary line between the contact region 184 and the source/drain region is higher than a boundary line between the gate stack structure and the substrate 100.
  • a boundary line between the contact region 184 and the source and drain regions may coincide with a boundary line between the gate stack structure and the substrate 100.
  • the contact region 184 means: a metal silicide formed to better contact silicon and a conductive material deposited subsequently in the contact hole 182 when a silicon substrate is selected;
  • the metal silicide may form a metal layer covering the substrate 100 (including one or a combination of Co, Ni, Mo, Pt or W) after forming the contact hole 182, and then forming the The substrate 100 of the metal layer is subjected to a heat treatment operation such as rapid heat treatment or rapid thermal annealing, which is formed after removing the unreacted metal layer.
  • the contact hole 182 is embedded in the source and drain regions, and SP is required to be in the source and drain when the contact hole 182 is formed.
  • the surface layer forms a groove, and a contact area is formed at the bottom wall 1822 and the side wall 1824 of the groove, such that the contact hole 182 is through the bottom surface thereof (in the present document, the bottom surface means the groove
  • the bottom wall 1822) is connected to the source/drain region, and may also be connected to the source/drain region via a portion of the side surface adjacent to the bottom surface, compared to the source/drain region only via the bottom surface thereof.
  • the technical solution increases the contact area and helps to reduce the contact resistance.
  • the topography of the sidewalls 1824 of the recess can be adjusted by using different etching processes.
  • the invention also provides a method of forming source and drain regions.
  • the method includes:
  • trenches 220 are formed on both sides of the gate stack structure in the substrate 200.
  • the substrate 200 has undergone a processing operation including pre-cleaning, forming a well region, and forming a shallow trench isolation region.
  • the substrate 100 is a silicon substrate, in other embodiments.
  • the substrate 100 may further include other compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide or indium phosphide; further, the substrate preferably includes an epitaxial layer; the substrate may also include an insulator Silicon on silicon (SOI) structure.
  • SOI Silicon on silicon
  • the gate stack structure includes a gate dielectric layer 202 formed on the substrate 200, a gate 204 formed on the gate dielectric layer 202, and a sidewall surrounding the gate dielectric layer 202 and the gate 204 206.
  • the gate 204 includes a polysilicon gate, a polysilicon dummy gate, or a metal gate. (Note: In this document, when describing a method of forming a source/drain region, the gate 204 is a polysilicon gate or a polysilicon dummy. Grid; In describing an embodiment of a method of forming a contact hole, the gate 204 may be a polysilicon gate or a metal gate).
  • the gate dielectric layer 202 may be selected from a germanium-based material such as one of Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO or HfZrO or a combination thereof.
  • Side wall 206 may include silicon nitride, silicon oxide, oxynitride One or a combination of silicon, silicon carbide.
  • the side wall 206 can have a multi-layered structure.
  • the gate dielectric layer 202 and the sidewall spacers 206 and the above-described processing operations can be formed or performed using conventional processes.
  • the trenches 220 may be formed by a wet and/or dry etch process.
  • the topography of the trenches 220 can be adjusted by using different etching processes.
  • a first semiconductor layer 222 is formed, and the first semiconductor layer 222 fills the trenches 220.
  • the material of the first semiconductor layer 222 includes Si, and the atomic percentage of SiGe C Ge may be 40%, and the content of Ge may be flexibly adjusted according to the process requirements, such as 30%-50%, which is not specifically described in this document.
  • the atomic percentage of Ge is the same as this, and will not be described again) or Si 1 ⁇ £ C x (The atomic percentage of C can be 0-2%, and the content of C can be flexibly adjusted according to the process requirements. At the description, the atomic percentage of C is the same, and will not be described again.
  • the material of the first semiconductor layer 222 may be a semiconductor material that has been ion-doped, for example, may be N-type or P-type Si, SiGe, or Si ⁇ C ⁇ .
  • Forming the material of the first semiconductor layer 222 directly eg, incorporating a reactant containing a dopant ion component in a reactant that generates the first semiconductor layer 222; or generating the source
  • the ion doping operation can be performed by any conventional ion implantation process, and will not be described again.
  • the first semiconductor layer 222 may be formed by pulsed laser deposition (PLD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or other suitable process.
  • PLD pulsed laser deposition
  • ALD atomic layer deposition
  • PEALD plasma enhanced atomic layer deposition
  • the material of the first semiconductor layer 222 in the PMOS device is SiGe
  • the material of the first semiconductor layer 222 in the NMOS device is Si 1 ⁇ c C x can cause the first semiconductor layer 222 to provide compressive stress to the channel region of the PMOS device, and provide tensile stress to the channel region of the NMOS device, which is advantageous for improving CMOS device performance.
  • the material of the first semiconductor layer 222 in the PMOS device and the NMOS device may also be selected from other different semiconductor materials.
  • the material of the first semiconductor layer 222 in the PMOS device may be the same as the material of the first semiconductor layer 222 in the NMOS device.
  • the first semiconductor layer 222 is trenched to the PMOS device.
  • the via region provides compressive stress while providing a tensile stress to the channel region of the NMOS device, and a different process can be used to form the material of the first semiconductor layer 222 in the PMOS device and the NMOS device.
  • the stop layer 240 and the auxiliary layer 242 are sequentially formed, and the auxiliary layer 242 is used.
  • the contact hole is carried when the embedded contact hole is formed on the source/drain region; the stop layer 240 is used to terminate the contact hole above a boundary between the gate stack structure and the substrate 200.
  • the stop layer 240 and the auxiliary layer 242 may be formed by pulsed laser deposition (PLD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or other suitable process.
  • PLD pulsed laser deposition
  • ALD atomic layer deposition
  • PEALD plasma enhanced atomic layer deposition
  • the material of the stop layer 240 and the auxiliary layer 242 in the PMOS device is the same as
  • the materials of the stop layer 240 and the auxiliary layer 242 are respectively the same in the NMOS device; in other words, the PMOS device is formed in synchronization with the stop layer 240 and the auxiliary layer 242 in the NMOS device. In addition to reducing the contact resistance, it also facilitates the process.
  • the material of the first semiconductor layer 222 in the PMOS device is SiGe.
  • the material of the auxiliary layer 242 is preferably SiGe. Is Si 1-x C x ; the stop layer 240 may be Si (in practice, for a 32 nm process, the stop layer 240 may have a thickness of 5 nm).
  • the stress of the channel region of the PMOS device and the NMOS device can still be adjusted, specifically
  • the adjustment method is the same as the method of adjusting the stress in the channel region of the device by using the first region, and will not be described again.
  • the materials of the stop layer 240 and the auxiliary layer 242 in the PMOS device and the NMOS device may also be different; in this case, the PMOS device and the NMOS device
  • the stop layer 240 and the auxiliary layer 242 are separately formed.
  • a boundary line between the stop layer 240 and the first semiconductor layer 222 may coincide with a boundary line between the gate stack structure and the substrate 200, or The gate stack structure is above the boundary line of the substrate 200.
  • the boundary between the stop layer 240 and the first semiconductor layer 222 and the boundary between the gate stack structure and the substrate 200 are coincident, the technical solution provided by the present invention and the existing source/drain region forming process are facilitated.
  • the boundary line between the stop layer 240 and the first semiconductor layer 222 is located above the boundary line between the gate stack structure and the substrate 200, the auxiliary layer 242 and the stop may be made by an adjustment process.
  • a contact region (such as a metal silicide layer) is introduced to reduce a contact resistance between a conductive material (such as a metal) filling the contact hole and the source/drain region.
  • the metal silicide layer may be formed by performing an annealing operation after depositing a metal on the source and drain regions, the metal material including one or a combination of Co, Ni, Mo, Pt or W) and the source and drain regions
  • a boundary line between the gate stack structure and the substrate 200 may be formed to reduce stress loss in the channel region of the device, thereby increasing carrier mobility.
  • the method includes - first, forming trenches on both sides of the gate stack structure in the substrate.
  • a first semiconductor layer is formed, the first semiconductor layer filling the trench.
  • a second semiconductor layer 260 is formed on the first semiconductor layer 222, and the material of the second semiconductor layer 260 and the first semiconductor The material of layer 222 is different.
  • the material of the second semiconductor layer 260 includes Si, SiGe or Sh_ x C x . It should be noted that the material of the second semiconductor layer 260 may be a semiconductor material that has been ion-doped, for example, Si, SiGe or S- X C X which may be N-type or P-type.
  • the ion doping operation may be directly formed in the process of generating the material of the second semiconductor layer 260 (eg, incorporating a reactant containing a dopant ion component in a reactant that generates the second semiconductor layer 260);
  • the ion doping operation may be performed by any conventional ion implantation process after the semiconductor material required to form the source and drain regions is formed, and then formed by an ion implantation process, and will not be described again.
  • the second semiconductor layer 260 can be formed by pulsed laser deposition (PLD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or other suitable process.
  • PLD pulsed laser deposition
  • ALD atomic layer deposition
  • PEALD plasma enhanced atomic layer deposition
  • the material of the first semiconductor layer 222 in the PMOS device is SiGe
  • the material of the first semiconductor layer 222 in the NMOS device is Si ⁇ C x
  • the PMOS and NMOS devices in the material of the second semiconductor layer 260 may be Si; i.e., the PMOS device in the second semiconductor material and the layer of the NMOS device 260
  • the material of the second semiconductor layer 260 is the same; in other words, the PMOS device is formed in synchronization with the second semiconductor layer 260 in the NMOS device. In addition to reducing the contact resistance, it also facilitates the process.
  • the material of the second semiconductor layer 260 is different from the material of the first semiconductor layer 222, so that a contact hole formed on the source/drain region may be terminated at a boundary between the gate stack structure and the substrate 200. Above the line.
  • the recess carrying the contact hole may be formed in the second semiconductor layer 260 to stop on the first semiconductor layer 222 by selecting a suitable etchant, so that the second semiconductor layer 260 may be adjusted.
  • the thickness of the groove is adjusted to flexibly adjust the contact area.
  • a boundary line of the second semiconductor layer 260 and the first semiconductor layer 222 may coincide with a boundary line of the gate stack structure and the substrate 200, or may be located in the gate stack structure and the substrate 200 Above the junction line.
  • the boundary line between the second semiconductor layer 260 and the first semiconductor layer 222 and the boundary line of the gate stack structure and the substrate 200 coincide, the technical solution provided by the present invention and the existing source and drain regions are facilitated. Forming process compatibility.
  • the second semiconductor layer 260 may be disposed in the second semiconductor layer 260 by an adjustment process.
  • a boundary line between the contact region introduced to reduce the contact resistance between the conductive material (such as metal) filling the contact hole and the source/drain region and the source and drain regions may be formed.
  • the conductive material such as metal
  • the method includes - first, forming trenches on both sides of the gate stack structure in the substrate.
  • a semiconductor layer 280 is formed, the semiconductor layer 280 filling the trench 220, and an upper surface of the semiconductor layer 280 and the gate stack structure and the The difference in height between the boundary lines of the substrate 200 is greater than the difference between the actual height of the semiconductor layer and the target height.
  • the material of the second semiconductor layer 260 is the same as the material of the first semiconductor layer 222 in comparison with the solution in the second embodiment of the above-described method of forming the source and drain regions.
  • the material of the source and drain regions in the PMOS device is SiGe
  • the material of the source and drain regions in the NMOS device is Sil-xCx.
  • the first semiconductor layer can be made to provide compressive stress to the channel region of the PMOS device, and to provide tensile stress to the channel region of the NMOS device, which is advantageous for improving CMOS device performance.
  • the technical solution provided by this embodiment can be better compatible with the existing source/drain region forming process.
  • the embodiment compared with the existing source/drain region forming process, it is only necessary to make the formed source and drain regions thicker, that is, the upper surface of the source and drain regions and the gate stack structure and the The difference in height between the boundary lines of the substrate 200 is greater than the difference between the actual height of the source and drain regions and the target height when the prior art is used. '
  • the present invention also provides a method of forming a contact hole.
  • a method of forming a contact hole On the basis of the embodiments of the method for forming the source and drain regions, after the interlayer dielectric layer 290 is formed on the source and drain regions and the interlayer dielectric layer 290 is planarized (as shown in FIG.
  • the interlayer dielectric layer 290 and the auxiliary layer 242 and the stop layer 240 (corresponding to the first embodiment of the method for forming the source/drain regions), or patterning the interlayer dielectric layer and the second semiconductor layer (corresponding to A second embodiment of the method of forming the source and drain regions), or, patterning the layers
  • the dielectric layer and a portion of the depth of the semiconductor layer form a contact hole that penetrates the interlayer dielectric layer 290 and terminates in the source and drain regions.
  • the method for forming the source and drain regions adopts the technical solution provided in the first embodiment, and it is obvious that the embodiment is also applicable to the source and drain.
  • the boundary between the bottom surface 2922 of the contact hole 292 and the source/drain region is higher than the gate stack structure and the substrate 200.
  • the boundary line By adjusting the process, a contact region and a source/drain region introduced to reduce a contact resistance between a conductive material (such as a metal) filling the contact hole and the source/drain region after forming the contact hole may be formed.
  • a boundary line between the gate stack structure and the substrate may be formed to reduce stress loss in the channel region of the device, thereby improving carrier mobility.
  • a boundary line between the bottom surface of the contact hole and the source/drain region may coincide with a boundary line between the gate stack structure and the substrate.
  • the source and drain regions adopt the technical solution provided in the first embodiment, it is obvious that the embodiment is also applicable to the source and drain regions.
  • the forming method uses the technical solutions provided in the second and third embodiments, and the bottom surface of the contact region 244 is formed after the surface of the source/drain region exposed by the contact hole 292 forms the contact region 244.
  • a boundary line between the 2924 and the source and drain regions is higher than a boundary line between the gate stack structure and the substrate 200.
  • a boundary line between the bottom surface of the contact region and the source and drain regions may coincide with a boundary line between the gate stack structure and the substrate. Both are beneficial to reduce the stress loss in the channel region of the device, thereby increasing the mobility of carriers.

Description

一种源漏区、 接触孔及其形成方法
技术领域
本发明涉及半导体技术领域， 特别涉及一种源漏区、 接触孔及其形成方法。 背景技术
随着半导体器件临界尺寸的逐渐减小， 各种微观效应开始显现， 优化半导体 器件的性能变得越来越困难， 其中， 颇具挑战性和实际意义的是如何减小源漏区 接触孔的接触电阻。
如图 1所示， 所述源漏区 40可由半导体材料构成， 所述源漏区 40位于栅堆 叠结构（所述栅堆叠结构包括形成于衬底 10上的栅介质层 12、形成于所述栅介质 层 12上的栅极 14， 以及， 环绕所述栅介质层 12和所述栅极 14的侧墙 16) 两侧 且嵌入衬底 10中， 所述源漏区 40的实际高度与目标高度之间的差值小于误差标 准。 为减小所述接触电阻， 在层间介质层 20中形成接于所述源漏区 40上的所述 接触孔 30时， 需在形成所述接触孔 30后， 在所述源漏区 40表层形成接触区 18 (如为金属硅化物） ， 使所述接触孔 30经由所述接触区 18接于所述源漏区 40， 由此， 如何减小所述接触区 18的电阻成为减小所述接触电阻的关键。
为减小所述接触区的电阻， 理论上， 可采用增加所述接触区的面积的技术方 案。 但是， 随着半导体器件临界尺寸的逐渐减小， 所述接触孔的临界尺寸也逐渐 减小， 如何在实践中增加所述接触区的面积成为本领域技术人员亟待解决的主要 问题。 发明内容
为了解决上述问题， 本发明提供了一种源漏区及其形成方法， 可以在所述源 漏区上形成接触区以承载具有确定尺寸的接触孔时， 增加所述接触孔与所述接触 区的接触面积， 减小接触电阻； 本发明提供了一种接触孔及其形成方法， 可以使 所述接触孔经由所述接触区接于所述源漏区时， 具有增加的接触面积， 而减小接 触电阻。
本发明提供的一种源漏区， 由半导体材料构成， 所述源漏区位于栅堆叠结构 两侧且嵌入衬底中， 所述源漏区包括：
第一区， 至少部分厚度的所述第一区位于所述衬底内；
第二区， 所述第二区形成于所述第一区上， 所述第二区的材料与所述第一区 的材料不同。
可选地， 所述第二区包括- 辅助层， 所述辅助层用以在所述源漏区上形成嵌入的接触孔时承载所述接触 孔；
停止层， 所述停止层用以使所述接触孔终止于所述栅堆叠结构与所述衬底的 交界线以上。
可选地， 在形成于硅衬底的 PMOS器件中， 所述第一区材料为 SiGe， 停止层 为 Si, 辅助层为 SiGe。
可选地， 在形成于硅衬底的 NMOS器件中， 所述第一区材料为 S .xCx， 停止 层为 Si， 辅助层为 SiGe。
可选地， 在包含所述源漏区的 CMOS器件中， 所述第一区对 PMOS器件的沟 道区提供压应力， 所述第一区对 NMOS器件的沟道区提供拉应力。
可选地，所述 PMOS器件中所述第一区的材料与所述 NMOS器件中所述第一 区的材料不同。
可选地，所述 PMOS器件中所述第二区的材料与所述 NMOS器件中所述第二 区的材料相同。
本发明提供的一种接触孔， 所述接触孔嵌入上述的源漏区中， 所述接触孔的 底面与所述源漏区的交界线高于或重合于栅堆叠结构与衬底的交界线。
可选地， 在所述接触孔暴露的所述源漏区表层形成接触区后， 所述接触区的 底面与所述源漏区的交界线高于或重合于所述栅堆叠结构与所述衬底的交界线。
本发明提供的一种接触孔， 所述接触孔嵌入源漏区中， 所述接触孔的底面与 所述源漏区的交界线高于或重合于栅堆叠结构与衬底的交界线； 所述源漏区由半 导体材料构成， 所述源漏区位于栅堆叠结构两侧且嵌入衬底中， 所述源漏区的上 表面与所述栅堆叠结构和所述衬底的交界线之间的高度差大于所述源漏区的实际 高度与目标高度之间的差值。
可选地， 在所述接触孔暴露的所述源漏区表层形成接触区后， 所述接触区的 底面与所述源漏区的交界线高于或重合于所述栅堆叠结构与所述衬底的交界线。 本发明提供的一种源漏区的形成方法， 包括：
在衬底中位于栅堆叠结构两侧形成沟槽；
形成第一半导体层， 至少部分所述第一半导体层填充所述沟槽；
在所述第一半导体层上形成第二半导体层， 所述第二半导体层的材料与所述 第一半导体层的材料不同。 可选地， 形成所述第二半导体层的步骤包括- 形成辅助层， 所述辅助层用以在所述源漏区上形成嵌入的接触孔时承载所述 接触孔；
形成停止层， 所述停止层用以使所述接触孔终止于所述栅堆叠结构与所述衬 底的交界线以上。
可选地， 在形成于硅衬底的 PMOS器件中， 所述第一区材料为 SiGe， 停止层 为 Si， 辅助层为 SiGe。
可选地， 在形成于硅衬底的 NMOS器件中， 所述第一区材料为 SiC， 停止层 为 Si， 辅助层为 SiGe。
可选地， 在包含所述源漏区的 CMOS器件中， 所述第一半导体层对 PMOS器 件的沟道区提供压应力， 所述第一半导体层对 NMOS器件的沟道区提供拉应力。
可选地，所述 PMOS器件中所述第一半导体层的材料与所述 NMOS器件中所 述第一半导体层的材料不同。
可选地，所述 PMOS器件中所述第二半导体层的材料与所述 NMOS器件中所 述第二半导体层的材料相同。 本发明提供的一种接触孔的形成方法， 包括：
以上述的方法形成源漏区；
在所述源漏区中嵌入接触孔， 所述接触孔的底面与所述源漏区的交界线高于 或重合于所述栅堆叠结构与衬底的交界线。
可选地， 在所述接触孔暴露的所述源漏区表层形成接触区后， 所述接触区的 底面与所述源漏区的交界线高于或重合于所述栅堆叠结构与所述衬底的交界线。
本发明提供的一种接触孔的形成方法， 包括- 在衬底中位于栅堆叠结构两侧形成沟槽； 形成半导体层， 所述半导体层的上表面与所述栅堆叠结构和所述衬底的交界 线之间的高度差大于所述半导体层的实际高度与目标高度之间的差值；
在所述半导体层中嵌入接触孔， 所述接触孔的底面与所述半导体层的交界线 高于或重合于所述栅堆叠结构与衬底的交界线。
可选地， 在所述接触孔暴露的所述源漏区表层形成接触区后， 所述接触区的 底面与所述源漏区的交界线高于或重合于所述栅堆叠结构与所述衬底的交界线。
与现有技术相比， 采用本发明提供的技术方案具有如下优点- 通过使所述源漏区包括至少部分厚度位于所述衬底内的第一区和形成于所述 第一区上的第二区， 且所述第二区的材料与所述第一区的材料不同 （换言之， 使 所述源漏区的上表面高于所述栅堆叠结构与所述衬底的交界线） ， 在后续形成接 触孔时， 需在所述源漏区表层形成凹槽， 并在所述凹槽的底壁和侧壁处均形成接 触区， 使所述接触孔在经由其底面接于所述源漏区之余， 还可经由其侧面中靠近 所述底面的部分接于所述源漏区， 相比于只经由其底面接于所述源漏区的技术方 案， 增加了接触面积， 利于减小接触电阻； _&可以通过选用适合的刻蚀剂使所述 凹槽形成于所述第二区中而停止于所述第一区上， 使得可以通过调节所述第二区 的厚度， 调节所述凹槽的形貌， 以灵活调节接触面积的大小；
通过使所述第二区包括辅助层和停止层， 利于在所述第二区与所述第一区的 刻蚀速率之差不明显时，使所述凹槽形成于所述第二区中而停止于所述第一区上， 进而， 可以通过调节所述第二区的厚度， 调节所述凹槽的形貌， 以灵活调节接触 面积的大小；
通过使 PMOS器件中所述第二区的材料与 NMOS器件中所述第二区的材料相 同， 可以对包含所述 PMOS器件和 NMOS器件的 CMOS器件同步形成源漏区上 的接触孔， 在减小接触电阻之余， 还利于简化工艺。 附图说明
图 1所示为现有技术中在源漏区上形成接触孔后的结构示意图；
图 2所示为本发明源漏区第一实施例的结构示意图；
图 3所示为本发明源漏区第二实施例的结构示意图；
图 4所示为本发明接触孔第一实施例的结构示意图； 图 5所示为本发明接触孔第二实施例的结构示意图；
图 6至图 8所示为施行本发明源漏区的形成方法第一实施例各步骤时的中间结构 示意图；
图 9所示为施行本发明源漏区的形成方法第二实施例后形成的中间结构示意图； 图 10至图 11所示为施行本发明接触孔的形成方法第一实施例各步骤时的中间结 构示意图；
图 12所示为施行本发明接触孔的形成方法第二实施例时的结构示意图。 具体实施方式
下文的公开提供了许多不同的实施例或例子用来实现本发明提供的技术方 案。 虽然下文中对特定例子的部件和设置进行了描述， 但是， 它们仅仅为示例， 并且目的不在于限制本发明。
此外， 本发明可以在不同实施例中重复参考数字和 /或字母。 这种重复是为了 简化和清楚的目的， 其本身不指示所讨论的各种实施例和 /或设置之间的关系。
本发明提供了各种特定工艺和 /或材料的例子， 但是， 本领域普通技术人员可 以意识到的其他工艺和 /或其他材料的替代应用， 显然未脱离本发明要求保护的范 围。 需强调的是， 本文件内所述的各种区域的边界包含由于工艺或制程的需要所 作的必要的延展。
如图 2所示， 在源漏区第一实施例中， 所述源漏区由半导体材料构成， 所述源 漏区位于栅堆叠结构两侧且嵌入衬底 100 中， 所述源漏区包括： 第一区 120， 所 述第一区 120位于所述衬底 100内； 第二区， 所述第二区形成于所述第一区 120 上； 其中， 所述第二区包括： 辅助层 144， 所述辅助层 144用以在所述源漏区上 形成嵌入的接触孔时承载所述接触孔； 停止层 142, 所述停止层 142用以使所述 接触孔终止于所述栅堆叠结构与所述衬底 100的交界线以上； 在包含所述源漏区 的 CMOS器件中， 所述第一区 120对 PMOS器件的沟道区提供压应力， 所述第一 区 120对 NMOS器件的沟道区提供拉应力； PMOS器件中所述第一区 120的材料 与 NMOS器件中所述第一区 120的材料不同；所述 PMOS器件中所述第二区的材 料与所述 NMOS器件中所述第二区的材料相同。
本文件中， 所述目标高度意指制程所需的理论高度， 如， 为满足设计需要， 需使 源漏区的高度为 2000埃， 此 2000埃即为所述目标高度； 所述误差标准意指满足工 艺要求的误差范围， 如， 在某一工艺条件下， 规定形成所述源漏区的高度偏差小 于或等于 ±5%时， 均认为所述源漏区的高度满足工艺要求， 此小于或等于 ±5%即 为所述误差标准； 所述实际高度意指在实践中为获得所述目标高度而获得的满足工 艺要求的现实高度，如，所述目标高度为 2000埃，所述误差标准为小于或等于 ±5% 时， 对于符合工艺要求的高度为 2050埃的源漏区， 此 2050埃即为所述源漏区的实 际高度。
具体地， 本文件中， 所述衬底 100均已经历处理操作， 所述处理操作包括预清洗、 形成阱区及形成浅沟槽隔离区， 在本实施例中， 所述衬底 100为硅衬底， 在其他实施 例中， 所述衬底 100还可以包括其他化合物半导体， 如碳化硅、 砷化镓、 砷化铟或磷 化锢； 此外， 所述衬底 100优选地包括外延层； 所述衬底 100也可以包括绝缘体上硅 ( SOI) 结构。
所述栅堆叠结构包括形成于衬底 100上的栅介质层 102、形成于所述栅介质层 102上的栅极 104， 以及， 环绕所述栅介质层 102和所述栅极 104的侧墙 106。 其 中， 所述栅极 104包括多晶硅栅极、 多晶硅伪栅或金属栅极 （说明： 本文件内， 在描述源漏区实施例时， 所述栅极 104为多晶硅栅极或多晶硅伪栅； 在描述接触 孔实施例时， 所述栅极 104可以为多晶硅栅极或金属栅极） 。 所述栅介质层 102 可以选用铪基材料， 如 Hf02、 HfSiO、 HfSiON, HfTaO、 HfTiO或 HfZi'O中的一 种或其组合。 侧墙 106可以包括氮化硅、 氧化硅、 氮氧化硅、 碳化硅中的一种或 其组合。 侧墙 106可以具有多层结构。 所述栅介质层 102和所述侧墙 106和上述处 理操作均可釆用传统工艺形成或执行。
构成所述源漏区的半导体材料包括 Si、 SiGe C Ge的原子数百分比可以为 40%, Ge的含量可以根据工艺需要灵活调节， 如 30%-50%， 本文件内未作特殊说明处， Ge的原子数百分比均与此相同， 不再赘述） 或 Si1-xCx ( C的原子数百分比可以为 0-2%, C的含量可以根据工艺需要灵活调节， 本文件内未作特殊说明处， C的原 子数百分比均与此相同， 不再赘述） 。 需说明的是， 所述半导体材料可以是已完 成离子掺杂的半导体材料， 如， 可以是 N型或 P型的 Si、 SiGe或 Si1-xCx。 所述离 子掺杂操作可以在生成所述半导体材料的过程中直接形成 （如在生成所述半导体 材料的反应物中掾入包含掺杂离子成分的反应物） ； 也可以在生成所述半导体材 料后， 再经由离子注入工艺形成， 可采用任何传统的离子注入工艺执行所述离子 掺杂操作， 不再赘述。
在本实施例中， 在包含所述源漏区的 CMOS器件中， 所述 PMOS器件中所述 第一区 120的材料为 SiGe， 所述 NMOS器件中所述第一区 120的材料为 SiLXCx， 可使所述第一区 120对所述 PMOS器件的沟道区提供压应力，而对 NMOS器件的 沟道区提供拉应力， 利于改善 CMOS器件性能。 在源漏区的其他实施例中， 所述 PMOS器件与 NMOS器件中所述第一区 120的材料还可以选用其他不同的半导体 材料。 所述 PMOS器件中所述第一区 120的材料与 NMOS器件中所述第一区 120 的材料也可以相同， 此时， 为使所述第一区 120对所述 PMOS器件的沟道区提供 压应力，而对 NMOS器件的沟道区提供拉应力，可采用不同的工艺形成所述 PMOS 器件和 NMOS器件中的所述第一区 120的材料。
在本实施例中， 所述 PMOS器件中所述第二区的材料与所述 NMOS器件中所 述第二区的材料相同， 即， 所述辅助层 144和停止层 142材料分别相同； 换言之， 所述 PMOS器件与所述 NMOS器件中所述第二区同步形成。在减小接触电阻之余， 还利于简化工艺。 具体地， 所述 PMOS器件中所述第一区 120的材料为 SiGe， 所 述 NMOS器件中所述第一区 120的材料为 Sh.xCx时，所述辅助层 144材料优选为 SiGe, 也可以为 S — XCX ; 所述停止层 142可以为 Si (实践中， 对于 32纳米工艺， 所述停止层 142的厚度可以为 5纳米）。此时，通过选取所述 PMOS器件和 NMOS 器件中所述第二区的材料或形成所述材料的工艺， 仍可调节所述 PMOS 器件和 NMOS器件沟道区的应力， 具体的调节方法与利用第一区调节器件沟道区中应力 的方式相同， 不再赘述。
此时， 所述辅助层 144用以在所述源漏区上形成嵌入的接触孔时承载所述接 触孔； 所述停止层 142用以使所述接触孔终止于所述栅堆叠结构与所述衬底的交 界线以上。 通过使所述第二区包括辅助层 144和停止层 142, 利于在所述第二区 与所述第一区 120的刻蚀速率之差不明显时， 使承载所述接触孔的凹槽形成于所 述第二区中而停止于所述第一区 120上， 进而， 可以通过调节所述第二区的厚度， 调节所述凹槽的形貌， 以灵活调节接触面积的大小。
在源漏区的不同的实施例中， 所述 PMOS器件与所述 NMOS器件中所述第二 区的材料也可以不同， 即， 所述辅助层 144和 /或停止层 142材料可以不同； 此时， 所述 PMOS器件与所述 NMOS器件中所述第二区需分别形成。
在源漏区的不同的实施例中， 所述停止层 142与所述第一区 120的交界线可 以与所述栅堆叠结构与所述衬底 100的交界线重合， 或者， 位于所述栅堆叠结构 与所述衬底 100的交界线上方。 所述停止层 142与所述第一区 120的交界线与所 述栅堆叠结构与所述衬底 100的交界线重合时， 利于本发明提供的技术方案与现 有的源漏区形成工艺的兼容。 所述停止层 142与所述第一区 120的交界线位于所 述栅堆叠结构与所述衬底 100的交界线上方时， 通过调节工艺， 可使在所述辅助 层 144和所述停止层 142中形成嵌入的接触孔后， 为减少填充所述接触孔的导电 材料 （如金属） 和所述源漏区之间的接触电阻而引入的接触区 （如为金属硅化物 层， 所述金属硅化物层可通过在所述源漏区上沉积金属后经历退火操作而形成， 所述金属材料包括 Co、 Ni、 Mo、 Pt或 W中的一种或其组合） 与所述源漏区之间 的交界线可以形成于所述栅堆叠结构与所述衬底 100的交界线以上， 利于减少器 件沟道区的应力损失， 进而提高载流子的迁移率。
如图 3 所示， 在源漏区的第二实施例中， 所述源漏区由半导体材料构成， 所述 源漏区位于栅堆叠结构两侧且嵌入衬底 100 中， 所述源漏区包括： 第一区 120， 至少部分厚度的所述第一区 120位于所述衬底 100内； 第二区 140, 所述第二区 140形成于所述第一区 120上， 所述第二区 140的材料与所述第一区 120的材料 不同。 在包含所述源漏区的 CMOS器件中， PMOS器件中所述第一区 120的材料 与 NMOS器件中所述第一区 120的材料不同。 所述 PMOS器件中所述第二区 140 的材料与所述 NMOS器件中所述第二区 140的材料相同。
在本实施例中， 对所述半导体材料、 栅堆叠结构、 衬底 100和第一区 120的说 明与前述实施例相同， 不再赘述。
在本实施例中， 所述 PMOS器件中所述第二区 140的材料与所述 NMOS器件 中所述第二区 140的材料相同； 换言之， 所述 PMOS器件与所述 NMOS器件中所 述第二区 140同步形成。 在减小接触电阻之余， 还利于简化工艺。 具体地， 所述 PMOS器件中所述第一区 120的材料为 SiGe, 所述 NMOS器件中所述第一区 120 的材料为 Si^Cx时， 所述 PMOS器件和所述 NMOS器件中所述第二区 140的材 料可以为 Si。
所述第二区 140的材料与所述第一区 120的材料不同， 可以使后续在所述源 漏区上形成的接触孔终止于所述栅堆叠结构与所述衬底的交界线以上。 可以通过 选用适合的刻蚀剂使承载所述接触孔的凹槽形成于所述第二区 140中而停止于所 述第一区 120上， 使得可以通过调节所述第二区 140的厚度， 调节所述凹槽的形 貌， 以灵活调节接触面积的大小。
所述第二区 140与所述第一区 120的交界线可以与所述栅堆叠结构与所述衬 底的交界线重合， 或者， 位于所述栅堆叠结构与所述衬底 100的交界线上方。 所 述第二区 140与所述第一区 120的交界线与所述栅堆叠结构与所述衬底 100的交 界线重合时， 利于本发明提供的技术方案与现有的源漏区形成工艺的兼容。 所述 第二区 140与所述第一区 120的交界线位于所述栅堆叠结构与所述衬底 100的交 界线上方时， 通过调节工艺， 可使在所述第二区 140中形成嵌入的接触孔后， 为 减少填充所述接触孔的导电材料 （如金属） 和所述源漏区之间的接触电阻而引入 的接触区与所述源漏区之间的交界线可以形成于所述栅堆叠结构与所述衬底的交 界线以上， 利于减少器件沟道区的应力损失， 进而提高载流子的迁移率。
本发明还提供了一种接触孔。 在上述源漏区的各实施例的基础上， 如图 4 所 示， 在所述源漏区上形成层间介质层 180后， 图形化所述层间介质层 180， 即可 形成穿通所述层间介质层 180并终止于所述源漏区内的接触孔 182。
在所述接触孔 182 的第一实施例中 （此时， 源漏区采用第一实施例中提供的 技术方案）， 所述接触孔 182与所述源漏区的交界线 1824高于栅堆叠结构与衬底 100的交界线。 在所述接触孔 182的其他实施例中， 所述接触孔 182与所述源漏 区的交界线可以重合于栅堆叠结构与衬底 100的交界线。
所述接触孔 182与所述源漏区的交界线与所述栅堆叠结构与所述衬底 100的 交界线重合时， 利于本发明提供的技术方案与现有的接触孔形成工艺的兼容。 所 述接触孔 182与所述源漏区的交界线高于所述栅堆叠结构与所述衬底 100的交界 线时， 通过调节工艺， 可使在形成所述接触孔 182后， 为减少填充所述接触孔 182 的导电材料 （如金属） 和所述源漏区之间的接触电阻而引入的接触区 184与所述 源漏区之间的交界线可以形成于所述栅堆叠结构与所述衬底的交界线以上， 利于 减少器件沟道区的应力损失， 进而提高载流子的迁移率。
具体地， 如图 5所示， 在所述接触孔 182的第二实施例中 （此时， 源漏区采 用第一实施例中提供的技术方案） ， 在所述接触孔 182暴露的所述源漏区表层形 成接触区 184后， 所述接触区 184与所述源漏区的交界线高于所述栅堆叠结构与 所述衬底 100的交界线。 在所述接触孔 182的其他实施例中， 所述接触区 184与 所述源漏区的交界线可以重合于栅堆叠结构与衬底 100的交界线。
本文件内， 所述接触区 184意指： 在选用硅衬底时， 为使硅和随后在所述接触 孔 182内淀积的导电材料更好地接触， 而形成的金属硅化物； 所述金属硅化物可在形 成所述接触孔 182后， 先形成覆盖所述衬底 100的金属层 （包括 Co、 Ni、 Mo、 Pt或 W中的一种或其组合）， 再对形成有所述金属层的所述衬底 100执行热处理 操作 （如快速热处理或快速热退火） ， 在去除未反应的所述金属层后形成。
需说明的是， 在本发明提供的接触孔的各实施例中， 所述接触孔 182均嵌入 到所述源漏区中， SP， 在形成所述接触孔 182时， 需在所述源漏区表层形成凹槽， 并在所述凹槽的底壁 1822和侧壁 1824处均形成接触区， 使所述接触孔 182在经 由其底面（本文件内， 所述底面意指所述凹槽的底壁 1822 )接于所述源漏区之余， 还可经由其侧面中靠近所述底面的部分接于所述源漏区， 相比于只经由其底面接 于所述源漏区的技术方案， 增加了接触面积， 利于减小接触电阻。 此外， 所述凹 槽的侧壁 1824的形貌可通过釆用不同的刻蚀工艺进行调节。
本发明还提供了一种源漏区的形成方法。
在所述源漏区的形成方法的第一实施例中， 所述方法包括：
首先， 如图 6所示， 在衬底 200中位于栅堆叠结构两侧形成沟槽 220。
所述衬底 200均已经历处理操作， 所述处理操作包括预清洗、 形成阱区及形成浅 沟槽隔离区，在本实施例中，所述衬底 100为硅衬底，在其他实施例中，所述衬底 100 还可以包括其他化合物半导体， 如碳化硅、 砷化镓、 砷化铟或磷化铟； 此外， 所述衬 底优选地包括外延层； 所述衬底也可以包括绝缘体上硅 （SOI) 结构。
所述栅堆叠结构包括形成于衬底 200上的栅介质层 202、形成于所述栅介质层 202上的栅极 204， 以及， 环绕所述栅介质层 202和所述栅极 204的侧墙 206。 其 中， 所述栅极 204包括多晶硅栅极、 多晶硅伪栅或金属栅极 （说明： 本文件内， 在描述源漏区的形成方法实施例时， 所述栅极 204为多晶硅栅极或多晶硅伪栅； 在描述接触孔的形成方法实施例时， 所述栅极 204 可以为多晶硅栅极或金属栅 极） 。 所述栅介质层 202可以选用铪基材料， 如 Hf02、 HfSiO、 HfSiON、 HfTaO、 HfTiO或 HfZrO中的一种或其组合。 侧墙 206可以包括氮化硅、 氧化硅、 氮氧化 硅、 碳化硅中的一种或其组合。 侧墙 206可以具有多层结构。 所述栅介质层 202 和所述侧墙 206和上述处理操作均可采用传统工艺形成或执行。
可釆用湿法和 /或干法刻蚀工艺形成所述沟槽 220。 所述沟槽 220的形貌可通 过采用不同的刻蚀工艺进行调节。
随后， 如图 7所示， 形成第一半导体层 222， 所述第一半导体层 222填充所述 沟槽 220。
所述第一半导体层 222的材料包括 Si、 SiGe C Ge的原子数百分比可以为 40%, Ge的含量可以根据工艺需要灵活调节， 如 30%-50%， 本文件内未作特殊说明处， Ge的原子数百分比均与此相同， 不再赘述） 或 Si1→£Cx ( C的原子数百分比可以为 0-2%, C的含量可以根据工艺需要灵活调节， 本文件内未作特殊说明处， C的原 子数百分比均与此相同， 不再赘述） 。 需说明的是， 所述第一半导体层 222材料 可以是已完成离子掺杂的半导体材料，如，可以是 N型或 P型的 Si、SiGe或 Si^C^ 所述离子掺杂操作可以在生成所述第一半导体层 222材料的过程中直接形成 （如 在生成所述第一半导体层 222的反应物中掺入包含掺杂离子成分的反应物） ； 也 可以在生成为形成所述源漏区所需的半导体材料后， 再经由离子注入工艺形成， 可釆用任何传统的离子注入工艺执行所述离子掺杂操作， 不再赘述。
可采用脉冲激光沉积 （PLD ) 、 原子层淀积 （ALD ) 、 等离子体增强原子层淀 积 （PEALD ) 或其他适合的工艺形成所述第一半导体层 222。
在本实施例中， 在包含所述源漏区的 CMOS器件中， 所述 PMOS器件中所述 第一半导体层 222的材料为 SiGe，所述 NMOS器件中所述第一半导体层 222的材 料为 Si1→cCx，可使所述第一半导体层 222对所述 PMOS器件的沟道区提供压应力， 而对 NMOS器件的沟道区提供拉应力， 利于改善 CMOS器件性能。在源漏区的其 他实施例中，所述 PMOS器件与 NMOS器件中所述第一半导体层 222的材料还可 以选用其他不同的半导体材料。 所述 PMOS器件中所述第一半导体层 222的材料 与 NMOS器件中所述第一半导体层 222的材料也可以相同， 此时， 为使所述第一 半导体层 222对所述 PMOS器件的沟道区提供压应力，而对 NMOS器件的沟道区 提供拉应力，可釆用不同的工艺形成所述 PMOS器件和 NMOS器件中的所述第一 半导体层 222的材料。
再后， 如图 8所示， 顺次形成停止层 240和辅助层 242， 所述辅助层 242用以 在所述源漏区上形成嵌入的接触孔时承载所述接触孔； 所述停止层 240用以使所 述接触孔终止于所述栅堆叠结构与所述衬底 200的交界线以上。
可采用脉冲激光沉积 （PLD ) 、 原子层淀积 （ALD ) 、 等离子体增强原子层淀 积 （PEALD) 或其他适合的工艺形成所述停止层 240和辅助层 242。
在本实施例中，所述 PMOS器件中所述停止层 240和辅助层 242的材料与所述
NMOS器件中所述停止层 240和辅助层 242的材料分别相同；换言之，所述 PMOS 器件与所述 NMOS器件中所述停止层 240和辅助层 242同步形成。在减小接触电 阻之余， 还利于简化工艺。 具体地， 所述 PMOS器件中所述第一半导体层 222的 材料为 SiGe， 所述 NMOS器件中所述第一半导体层 222的材料为 SinCx时， 所 述辅助层 242材料优选为 SiGe, 也可以为 Si1-xCx； 所述停止层 240可以为 Si (实 践中， 对于 32纳米工艺， 所述停止层 240的厚度可以为 5纳米） 。 此时， 通过选 取所述 PMOS器件和 NMOS器件中所述停止层 240和辅助层 242的材料或形成所 述材料的工艺， 仍可调节所述 PMOS器件和 NMOS器件沟道区的应力， 具体的调 节方法与利用第一区调节器件沟道区中应力的方式相同， 不再赘述。
在源漏区的不同的实施例中， 所述 PMOS器件与所述 NMOS器件中所述停止 层 240和辅助层 242的材料也可以不同； 此时， 所述 PMOS器件与所述 NMOS器 件中所述停止层 240和辅助层 242需分别形成。
在源漏区的不同的实施例中， 所述停止层 240与所述第一半导体层 222的交 界线可以与所述栅堆叠结构与所述衬底 200的交界线重合， 或者， 位于所述栅堆 叠结构与所述衬底 200的交界线上方。 所述停止层 240与所述第一半导体层 222 的交界线与所述栅堆叠结构与所述衬底 200的交界线重合时， 利于本发明提供的 技术方案与现有的源漏区形成工艺的兼容。 所述停止层 240与所述第一半导体层 222 的交界线位于所述栅堆叠结构与所述衬底 200 的交界线上方时， 通过调节工 艺， 可使在所述辅助层 242和所述停止层 240中形成嵌入的接触孔后， 为减少填 充所述接触孔的导电材料 （如金属） 和所述源漏区之间的接触电阻而引入的接触 区 （如为金属硅化物层， 所述金属硅化物层可通过在所述源漏区上沉积金属后经 历退火操作而形成， 所述金属材料包括 Co、 Ni、 Mo、 Pt或 W中的一种或其组合） 与所述源漏区之间的交界线可以形成于所述栅堆叠结构与所述衬底 200的交界线 以上， 利于减少器件沟道区的应力损失， 进而提高载流子的迁移率。 在所述源漏区的形成方法的第二实施例中， 所述方法包括- 首先， 在衬底中位于栅堆叠结构两侧形成沟槽。
随后， 形成第一半导体层， 所述第一半导体层填充所述沟槽。
涉及的相关工艺与上述实施例中描述的相同， 不再赘述。
再后， 如图 9所示， 并结合图 6及图 7所示， 在所述第一半导体层 222上形成 第二半导体层 260， 所述第二半导体层 260的材料与所述第一半导体层 222的材 料不同。
所述第二半导体层 260的材料包括 Si、 SiGe或 Sh_xCx。 需说明的是， 所述第 二半导体层 260材料可以是已完成离子掺杂的半导体材料， 如， 可以是 N型或 P 型的 Si、 SiGe或 S — XCX。 所述离子掺杂操作可以在生成所述第二半导体层 260材 料的过程中直接形成 （如在生成所述第二半导体层 260的反应物中掺入包含掺杂 离子成分的反应物） ； 也可以在生成为形成所述源漏区所需的半导体材料后， 再 经由离子注入工艺形成，可采用任何传统的离子注入工艺执行所述离子掺杂操作， 不再赘述。
可釆用脉冲激光沉积 （PLD ) 、 原子层淀积 （ALD ) 、 等离子体增强原子层淀 积 （PEALD) 或其他适合的工艺形成所述第二半导体层 260。
在本实施例中， 在包含所述源漏区的 CMOS器件中， 所述 PMOS器件中所述 第一半导体层 222的材料为 SiGe,所述 NMOS器件中所述第一半导体层 222的材 料为 Si^Cx，所述 PMOS器件和 NMOS器件中的所述第二半导体层 260的材料可 以为 Si; 即， 所述 PMOS器件中所述第二半导体层 260的材料与所述 NMOS器件 中所述第二半导体层 260的材料相同； 换言之， 所述 PMOS器件与所述 NMOS器 件中所述第二半导体层 260同步形成。 在减小接触电阻之余， 还利于简化工艺。
所述第二半导体层 260的材料与所述第一半导体层 222的材料不同， 可以使 后续在所述源漏区上形成的接触孔终止于所述栅堆叠结构与所述衬底 200的交界 线以上。 可以通过选用适合的刻蚀剂使承载所述接触孔的凹槽形成于所述第二半 导体层 260中而停止于所述第一半导体层 222上， 使得可以通过调节所述第二半 导体层 260的厚度， 调节所述凹槽的形貌， 以灵活调节接触面积的大小。
所述第二半导体层 260与所述第一半导体层 222的交界线可以与所述栅堆叠 结构与所述衬底 200的交界线重合， 或者， 位于所述栅堆叠结构与所述衬底 200 的交界线上方。 所述第二半导体层 260与所述第一半导体层 222的交界线与所述 栅堆叠结构与所述衬底 200的交界线重合时， 利于本发明提供的技术方案与现有 的源漏区形成工艺的兼容。 所述第二半导体层 260与所述第一半导体层 222的交 界线位于所述栅堆叠结构与所述衬底的交界线上方时， 通过调节工艺， 可使在所 述第二半导体层 260中形成嵌入的接触孔后， 为减少填充所述接触孔的导电材料 (如金属） 和所述源漏区之间的接触电阻而引入的接触区与所述源漏区之间的交 界线可以形成于所述栅堆叠结构与所述衬底 200的交界线以上， 利于减少器件沟 道区的应力损失， 进而提高载流子的迁移率。
在所述源漏区的形成方法的第三实施例中， 所述方法包括- 首先， 在衬底中位于栅堆叠结构两侧形成沟槽。
涉及的相关工艺与上述实施例中描述的相同， 不再赘述。
随后， 如图 10所示， 并结合图 6所示， 形成半导体层 280， 所述半导体层 280 填充所述沟槽 220， 且所述半导体层 280的上表面与所述栅堆叠结构和所述衬底 200的交界线之间的高度差大于所述半导体层的实际高度与目标高度之间的差值。
相比于上述源漏区的形成方法第二实施例中的方案， 本实施例相当于所述第二半 导体层 260的材料与所述第一半导体层 222的材料相同。 此时， 在包含所述源漏 区的 CMOS器件中， 所述 PMOS器件中所述源漏区的材料为 SiGe， 所述 NMOS 器件中所述源漏区的材料为 Sil-xCx。 可使所述第一半导体层对所述 PMOS器件 的沟道区提供压应力， 而对 NMOS 器件的沟道区提供拉应力， 利于改善 CMOS 器件性能。 本实施例提供的技术方案可以与现有的源漏区形成工艺较好地兼容。 采用本实施例提供的技术方案， 相对于现有的源漏区形成工艺， 只需使形成的源 漏区厚些， 即， 使所述源漏区的上表面与所述栅堆叠结构与所述衬底 200的交界 线之间的高度差大于采用现有技术时所述源漏区的实际高度与目标高度之间的差 值。 '
本发明还提供了一种接触孔的形成方法。 在上述源漏区的形成方法各实施例 的基础上， 再在所述源漏区上形成层间介质层 290并平坦化所述层间介质层 290 后 （如图 1 1所示） ， 图形化所述层间介质层 290和上述辅助层 242及停止层 240 (对应源漏区的形成方法的第一实施例） ， 或者， 图形化所述层间介质层和上述 第二半导体层 （对应源漏区的形成方法的第二实施例） ， 或者， 图形化所述层间 介质层和部分深度的上述半导体层 （对应源漏区的形成方法的第三实施例） ， 即 可形成穿通所述层间介质层 290并终止于所述源漏区内的接触孔。
如图 12所示， 在所述接触孔的形成方法第一实施例中 （此时， 源漏区的形成 方法采用第一实施例中提供的技术方案， 显然， 本实施例也适用于源漏区的形成 方法采用第二及第三实施例中提供的技术方案时， 不再赘述） ， 所述接触孔 292 的底面 2922与所述源漏区的交界线高于栅堆叠结构与衬底 200的交界线。通过调 节工艺， 可使在形成所述接触孔后， 为减少填充所述接触孔的导电材料（如金属） 和所述源漏区之间的接触电阻而引入的接触区与所述源漏区之间的交界线可以形 成于所述栅堆叠结构与所述衬底的交界线以上，利于减少器件沟道区的应力损失， 进而提高载流子的迁移率。
在所述接触孔的形成方法其他实施例中， 所述接触孔的底面与所述源漏区的 交界线可以重合于栅堆叠结构与衬底的交界线。 利于本发明提供的技术方案与现 有的接触孔形成工艺的兼容。
具体地， 如图 13所示， 在所述接触孔的第二实施例中 （此时， 源漏区采用第 一实施例中提供的技术方案， 显然， 本实施例也适用于源漏区的形成方法釆用第 二及第三实施例中提供的技术方案时， 不再赘述） ， 在所述接触孔 292暴露的所 述源漏区表层形成接触区 244后，所述接触区 244的底面 2924与所述源漏区的交 界线高于所述栅堆叠结构与所述衬底 200的交界线。 在所述接触孔的其他实施例 中， 所述接触区的底面与所述源漏区的交界线可以重合于栅堆叠结构与衬底的交 界线。 均利于减少器件沟道区的应力损失， 进而提高载流子的迁移率。
此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工艺、 结构、 制 造、 物质组成、 手段、 方法及步骤。 根据本发明的公开内容， 本领域技术人员将容易 地理解， 对于目前已存在或者以后即将开发出的工艺、 机构、制造、物质组成、 手段、 方法或步骤， 它们在执行与本发明描述的对应实施例大体相同的功能或者获得大体相 同的结果时， 依照本发明的教导， 可以对它们进行应用， 而不脱离本发明所要求保护 的范围。

Claims

权 利 要 求
1、 一种源漏区， 由半导体材料构成， 所述源漏区位于栅堆叠结构两侧且嵌入 衬底中， 其特征在于， 所述源漏区包括- 第一区， 至少部分厚度的所述第一区位于所述衬底内；
第二区， 所述第二区形成于所述第一区上， 所述第二区的材料与所述第一区 的材料不同。
2、 根据权利要求 1所述的源漏区， 其特征在于， 所述第二区包括- 辅助层， 所述辅助层用以在所述源漏区上形成嵌入的接触孔时承载所述接触 孔；
停止层， 所述停止层用以使所述接触孔终止于所述栅堆叠结构与所述衬底的 交界线以上。
3、 根据权利要求 2 所述的源漏区， 其特征在于： 在形成于硅衬底的 PMOS 器件中， 所述第一区材料为 SiGe, 停止层为 Si， 辅助层为 SiGe。
4、 根据权利要求 3 所述的源漏区， 其特征在于： 在形成于硅衬底的 NMOS 器件中， 所述第一区材料为 Si^Cx, 停止层为 Si, 辅助层为 SiGe。
5、 根据权利要求 1 或 2所述的源漏区， 其特征在于： 在包含所述源漏区的
CMOS 器件中， 所述第一区对 PMOS 器件的沟道区提供压应力， 所述第一区对
NMOS器件的沟道区提供拉应力。
6、 根据权利要求 5所述的源漏区， 其特征在于： 所述 PMOS器件中所述第 一区的材料与所述 NMOS器件中所述第一区的材料不同。
7、 根据权利要求 6所述的源漏区， 其特征在于： 所述 PMOS器件中所述第 二区的材料与所述 NMOS器件中所述第二区的材料相同。
8、 一种接触孔， 其特征在于： 所述接触孔嵌入如权利要求 1至 7中任一项所 述的源漏区中， 所述接触孔的底面与所述源漏区的交界线高于或重合于栅堆叠结 构与衬底的交界线。
9、 根据权利要求 8所述的接触孔， 其特征在于： 在所述接触孔暴露的所述源 漏区表层形成接触区后， 所述接触区的底面与所述源漏区的交界线高于或重合于 所述栅堆叠结构与所述衬底的交界线。
10、 一种接触孔， 其特征在于： 所述接触孔嵌入源漏区中， 所述接触孔的底 面与所述源漏区的交界线高于或重合于栅堆叠结构与衬底的交界线； 所述源漏区 由半导体材料构成， 所述源漏区位于栅堆叠结构两侧且嵌入衬底中， 所述源漏区 的上表面与所述栅堆叠结构和所述衬底的交界线之间的高度差大于所述源漏区的 实际高度与目标高度之间的差值。
11、 根据权利要求 10所述的接触孔， 其特征在于： 在所述接触孔暴露的所述 源漏区表层形成接触区后， 所述接触区的底面与所述源漏区的交界线高于或重合 于所述栅堆叠结构与所述衬底的交界线。
12、 一种源漏区的形成方法， 其特征在于， 包括- 在衬底中位于栅堆叠结构两侧形成沟槽；
形成第一半导体层， 至少部分所述第一半导体层填充所述沟槽；
在所述第一半导体层上形成第二半导体层， 所述第二半导体层的材料与所述 第一半导体层的材料不同。
13、 根据权利要求 12所述的方法， 其特征在于， 形成所述第二半导体层的步 骤包括：
形成辅助层， 所述辅助层用以在所述源漏区上形成嵌入的接触孔时承载所述 接触孔；
形成停止层， 所述停止层用以使所述接触孔终止于所述栅堆叠结构与所述衬 底的交界线以上。
14、 根据权利要求 13 所述的方法， 其特征在于： 在形成于硅衬底的 PMOS 器件中， 所述第一区材料为 SiGe, 停止层为 Si， 辅助层为 SiGe。
15、 根据权利要求 14所述的方法， 其特征在于： 在形成于硅衬底的 NMOS 器件中， 所述第一区材料为 Si1-xCx， 停止层为 Si， 辅助层为 SiGe。
16、 根据权利要求 12或 13所述的方法， 其特征在于： 在包含所述源漏区的 CMOS器件中， 所述第一半导体层对 PMOS器件的沟道区提供压应力， 所述第一 半导体层对 NMOS器件的沟道区提供拉应力。
17、 根据权利要求 16所述的方法， 其特征在于： 所述 PMOS器件中所述第 一半导体层的材料与所述 NMOS器件中所述第一半导体层的材料不同。
18、 根据权利要求 17所述的方法， 其特征在于： 所述 PMOS器件中所述第 二半导体层的材料与所述 NMOS器件中所述第二半导体层的材料相同。
19、 一种接触孔的形成方法， 其特征在于， 包括- 以如权利要求 12至 18中任一项所述的方法形成源漏区；
在所述源漏区中嵌入接触孔， 所述接触孔的底面与所述源漏区的交界线高于 或重合于所述栅堆叠结构与衬底的交界线。
20、 根据权利要求 19所述的方法， 其特征在于： 在所述接触孔暴露的所述源 漏区表层形成接触区后， 所述接触区的底面与所述源漏区的交界线高于或重合于 所述栅堆叠结构与所述衬底的交界线。
21、 一种接触孔的形成方法， 其特征在于， 包括：
在衬底中位于栅堆叠结构两侧形成沟槽；
形成半导体层， 所述半导体层的上表面与所述栅堆叠结构和所述衬底的交界 线之间的高度差大于所述半导体层的实际高度与目标高度之间的差值；
在所述半导体层中嵌入接触孔， 所述接触孔的底面与所述半导体层的交界线 高于或重合于所述栅堆叠结构与衬底的交界线。
22、 根据权利要求 21所述的方法， 其特征在于： 在所述接触孔暴露的所述源 漏区表层形成接触区后， 所述接触区的底面与所述源漏区的交界线高于或重合于 所述栅堆叠结构与所述衬底的交界线。
PCT/CN2011/071086 2010-04-21 2011-02-18 一种源漏区、接触孔及其形成方法 WO2011131053A1 (zh)

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