WO2012055198A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2012055198A1
WO2012055198A1 PCT/CN2011/071253 CN2011071253W WO2012055198A1 WO 2012055198 A1 WO2012055198 A1 WO 2012055198A1 CN 2011071253 W CN2011071253 W CN 2011071253W WO 2012055198 A1 WO2012055198 A1 WO 2012055198A1
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Prior art keywords
semiconductor substrate
source
forming
sidewall
layer
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PCT/CN2011/071253
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English (en)
French (fr)
Inventor
朱慧珑
骆志炯
尹海洲
梁擎擎
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中国科学院微电子研究所
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Priority to US13/144,375 priority Critical patent/US20120217583A1/en
Publication of WO2012055198A1 publication Critical patent/WO2012055198A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to the field of semiconductor manufacturing technology, and more particularly to a semiconductor structure having a source/drain stress layer and shallow trench isolation and a method of forming the same. Background technique
  • Figure la is an ideal structure in which the top of the STI 10 is above the top of the source/drain stress layer 20, thereby maintaining the channel 30 in strong stress.
  • Figure lb the process of over-cleaning, dry or wet etching in the preparation process results in high STI loss, when the top of the STI 10 is lower than the top of the source/drain stress layer 20, Stress relief, ie channel stress loss.
  • the object of the present invention is to solve at least one of the above technical problems, in particular, to solve the problem that the channel stress of a MOSFET device is lost due to the boundary effect between the STI and the source/drain stress layer, and the semiconductor structure and method proposed by the present invention. It is also conducive to the quality of the source/drainage area.
  • the present invention provides a semiconductor structure including: a semiconductor substrate; a gate stack on the semiconductor substrate; a source located on both sides of the gate stack and embedded in the semiconductor substrate /drain stress layer; shallow trench isolation embedded in the semiconductor substrate, the top of the shallow trench isolation being higher or flatter than the top of the source/drain stress layer, the shallow trench isolation Isolating the semiconductor substrate into different active regions; the top of the shallow trench isolation is formed with a dummy gate, the sidewall of the dummy gate is formed with a first sidewall, and the first sidewall portion is located On the active area.
  • the source/drain stress layer includes SiGe having a Ge content of 15% to 70%; and for an nMOS field effect transistor, the source/drain stress layer includes a C content of 0.2%-2 % Si: C.
  • the sidewall of the gate stack is formed with a second sidewall.
  • the first sidewall portion is located on the active region of the semiconductor substrate, and on the one hand, the shallow trench isolation may be completely covered to protect it in subsequent processes of over-cleaning and etching. Without being destroyed, on the other hand, a part of the substrate may be left on the side of the shallow trench isolation, and thus the source/drain regions may be formed by epitaxial growth of the seed layer, thereby improving the source/drain region quality.
  • the present invention provides a method of forming the above semiconductor structure, comprising the steps of: A. providing a semiconductor substrate; B. embedding the semiconductor substrate to form shallow trench isolation to form the semiconductor substrate with each other An isolated active region, wherein a top of the shallow trench isolation is higher or flatter than a top of the active region; C. forming a gate stack on the active region, on the shallow trench isolation Forming a dummy gate; D. forming a first spacer on a sidewall of the dummy gate, the first sidewall portion being located on the active region; E. embedding the semiconductor liner on both sides of the gate stack The bottom forms a source/drain stress layer, the top of the shallow trench isolation being higher or flatter than the top of the source/drain stress layer.
  • forming the shallow trench isolation in step B includes the steps of: forming a hard mask layer on the semiconductor substrate; etching the hard mask layer and the semiconductor substrate to form a trench; filling the The trench forms an insulating layer; the insulating layer is etched back such that the top of the insulating layer is higher or flatter than the top of the active region; the hard mask layer is removed.
  • the step D further includes: simultaneously forming a second sidewall spacer on the sidewall of the gate stack.
  • the method before forming the first sidewall spacer and the second sidewall spacer, the method further includes: performing oblique ion implantation on the active region of the semiconductor substrate to form a halo implant region, and/or performing Tilt ion implantation to form source/drain extensions.
  • the forming the source/drain stress layer in step E includes: using the first sidewall and the second side The wall is etched for the mask to form a recess on both sides of the gate stack in the semiconductor substrate, wherein a portion of the semiconductor substrate remains between the EJ trench and the shallow trench isolation; In the EJ trench, a source/drain stress layer is formed by epitaxial growth of the partial semiconductor substrate as a seed layer.
  • the epitaxially growing the source/drain stress layer comprises: for a pMOS field effect transistor, epitaxially growing SiGe having a Ge content of 15% to 70%; and for the nMOS field effect transistor, Si:C having an C content of 0.2% to 2% is epitaxially grown in the groove.
  • the present invention can form an STI which is higher or flatter than a source/drain stress layer in a MOSFET device, and a device structure for forming a dummy gate and a sidewall on the STI and a method of forming the same, which can effectively prevent the height of the STI from being Subsequent process reductions such as over-cleaning and etching reduce or avoid channel stress loss, which is beneficial to enhance device performance.
  • the added dummy gate sidewall portion is located on the active region of the semiconductor substrate, and a portion of the substrate may be left on the STI-side when the source/drain region recess is formed by etching, and thus the seed layer may be epitaxially grown.
  • the source/drain regions are formed to improve the source/drain region quality.
  • FIG. 1 is a schematic diagram showing the structural relationship between STI and source/drain stress layers in a prior art MOSFET device, wherein diagrams la and lb are schematic diagrams of ideal conditions and actual conditions, respectively.
  • FIG. 2 is a cross-sectional view showing a semiconductor structure according to an embodiment of the present invention.
  • 3-12 are schematic diagrams of intermediate steps in a method of forming a semiconductor structure in accordance with an embodiment of the present invention. detailed description
  • the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. The embodiment, such that the first and second features may not be in direct contact.
  • 2 is a cross-sectional view showing a semiconductor structure according to an embodiment of the present invention, the structure including: a semiconductor substrate 100; a gate stack 200 on the semiconductor substrate 100; a source located on both sides of the gate stack 200 and embedded in the semiconductor substrate 100 / drain stress layer 300; STI 400 embedded in the semiconductor substrate 100, the top of the STI 400 is higher or flatter than the top of the source/drain stress layer 300, and the top of the STI 400 is formed with a dummy gate 500, the sidewall of the dummy gate 500 A first side wall 600 is formed.
  • the first side wall 600 is partially located on the active area 900 of the semiconductor substrate 100, and the purpose is: on the one hand, the STI 400 under the dummy gate 500 can be completely covered to protect it from subsequent over-cleaning and engraving. In the process of etching or the like, it is not destroyed; on the other hand, a part of the substrate may be left on the side of the shallow trench isolation when the source/drain regions are formed by etching, and thus the seed layer may be epitaxially grown to improve the source. / leak zone quality.
  • the meaning of "flat" in the present invention means: It means that the difference in height between the two planes is within the range allowed by the process or process.
  • the sidewall of the gate stack 200 is formed with a second spacer 700;
  • the source/drain stress layer 300 may include SiGe having a Ge content of 15% to 70% to generate compressive stress on the channel (compressive stress)
  • the source/drain stress layer 300 includes Si:C having a C content of 0.2% to 2% to generate tensile stress to the channel, and can be in situ for both SiGe and Si:C. Doping to increase the stress effect; the gate stack 200, the dummy gate 500, and the top of the source/drain stress layer 300 are respectively formed with a metal silicide 1800, which may be, for example, NiPtSi.
  • a method of forming a semiconductor structure according to an embodiment of the present invention includes the following steps: Step A: A semiconductor substrate 100 is provided.
  • the substrate 100 is exemplified by bulk silicon, but in practical applications, the substrate may include any suitable semiconductor substrate material, specifically but not limited to silicon, germanium, silicon germanium, soi (silicon on insulator), silicon carbide, Gallium arsenide or any m/v compound semiconductor or the like.
  • the substrate 100 can include various doping configurations in accordance with design requirements well known in the art (e.g., p-type or n-type substrates). Additionally, substrate 100 can optionally include an epitaxial layer that can be altered by stress to enhance performance.
  • Step B Embedding the semiconductor substrate 100 to form the STI 400 to form the semiconductor substrate 100 into mutually isolated active regions 900, wherein the top of the STI 400 is higher or flatter than the top of the active region 900.
  • an oxide liner 800 such as silicon oxide
  • a hard mask layer is formed on the oxide liner 800.
  • 1000 e.g., silicon nitride
  • a patterned photoresist 1100 is formed on the nitride layer 1000 using a mask of a predetermined STI pattern.
  • the method for forming the medium in the embodiment of the present invention, if not In particular, they can be formed by conventional deposition processes such as sputtering, pulsed laser deposition (PLD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and plasma enhanced atomic layer deposition (PEALD). ), plasma enhanced chemical vapor deposition (PECVD) or other suitable method.
  • PLD pulsed laser deposition
  • MOCVD metal organic chemical vapor deposition
  • ALD atomic layer deposition
  • PEALD plasma enhanced atomic layer deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the hard mask layer 1000 and the oxide liner 800 are sequentially etched. And a semiconductor substrate 100 to form trenches 1200, as shown in FIG.
  • the etching may be performed by reactive ion etching (RIE), and the etching depth may be 100-500 nm.
  • an insulating layer 1300 is formed in the trench 1200.
  • an oxide such as silicon oxide
  • CMP chemical mechanical polishing
  • the insulating layer 1300 is etched back so that its surface is higher or flatter than the surface of the active region 900, as shown in FIG.
  • the hard mask layer 1000 (silicon nitride) is removed to form the STI 400, thereby forming the semiconductor substrate 100 into mutually isolated active regions 900, wherein the top of the STI 400 is higher or flatter than the top of the active region 900.
  • the top of the STI 400 is higher than the surface of the active region, as shown in FIG.
  • the removal of the nitride layer 1000 can be performed by selectively etching the nitride relative to the underlying oxide.
  • Step C A gate stack 200 is formed on the active region 900, and a dummy gate 500 is formed on the STI 400.
  • the oxide liner 800 is first partially etched to form a thinner oxide layer as the gate dielectric layer 1400.
  • the gate dielectric layer 1400 may also be a high-k dielectric. In this case, the oxide liner 800 is completely etched away, and then a high-k dielectric is formed as the gate dielectric layer 1400.
  • the thickness of the high-k dielectric layer may be L-3nm
  • high-k dielectric materials include, for example, germanium-based materials such as hafnium oxide (Hf0 2 ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium oxide (HfTaO), niobium oxide (HfTiO) , yttria-yttria (HfZrO), combinations thereof and/or other suitable materials.
  • germanium-based materials such as hafnium oxide (Hf0 2 ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium oxide (HfTaO), niobium oxide (HfTiO) , yttria-yttria (HfZrO), combinations thereof and/or other suitable materials.
  • a gate conductive layer not shown in FIG.
  • the gate dielectric layer 1400 which may be a metal layer, such as PVD (physical vapor deposition, including evaporation, sputtering, electron beam, etc.), CVD (chemical vapor phase) Deposited, plated or otherwise formed.
  • a polysilicon layer 1500 having a thickness of 50-150 nm may be deposited, and a nitride layer 1600 may be deposited, which may have a thickness of 20-50 nm.
  • the gate stack 200 and the dummy gate 500 are formed by a conventional process.
  • the patterned photoresist can be formed as a mask according to a preset mask, and then the nitride layer 1600 and the polysilicon layer 1500 are sequentially etched, the gate dielectric layer 1400 is used as a stop surface, and then the photoresist is removed to form a mask.
  • the gate stack 200 and the dummy gate 500 are as shown in FIG. 9, wherein the gate stack 200 is on the active region 900 and the dummy gate 500 is on the STI 400.
  • Step D forming a first sidewall 800 on a sidewall of the dummy gate 500, the first sidewall 600 being partially located on the active region 900 of the semiconductor substrate, optionally forming a second side on the sidewall of the gate stack 200 Wall 700, as shown in FIG.
  • the material of the first side wall and the second side wall may be the same, for example, one of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, fluoride doped silicon glass, low k dielectric material, or a combination thereof. And / or other suitable materials are formed.
  • the sidewall spacers may be formed by first depositing a dielectric material and then performing reactive ion etching with the gate dielectric layer 1400 as a stop surface.
  • the first sidewall 600 is partially over the STI 400 and partially on the active region 900 of the semiconductor substrate, as shown in FIG.
  • the purpose of forming the structure is: on the one hand, the STI 400 can be completely covered to protect it from being damaged in subsequent processes of over-cleaning and etching, and on the other hand, source/drain regions can be formed in subsequent etching.
  • the source/drain regions can be formed by epitaxial growth of the seed layer, thereby improving the source/drain region quality.
  • oblique ion implantation may be performed on the active region 900 of the semiconductor substrate to form a halo implant region (not shown). And/or performing oblique ion implantation to form source/drain extensions (not shown), for example, for nMOSFETs, tilt ion implantation may be performed using p-type dopants such as B, BF 2 or a combination thereof to form halo
  • the implantation region is subjected to oblique ion implantation using an n-type dopant such as As, P or a combination thereof to form a source/drain extension region; for a pMOSFET, an oblique ion implantation is performed using an n-type dopant such as As, P or a combination thereof to form
  • the halo implant region may be subjected to oblique ion implantation using a p-type dopant such as B, BF 2 or a
  • Step E A source/drain stress layer 300 is formed on the semiconductor substrate 100 on both sides of the gate stack 200, and the top of the STI 400 is higher or flatter than the top of the source/drain stress layer 300.
  • the gate dielectric layer 1400 and the semiconductor substrate 100 are etched by RIE using the first sidewall spacer 600 and the second spacer 700 as a mask to form a recess 1700 in the semiconductor substrate 100 on both sides of the gate stack 200. Wherein, a portion of the semiconductor substrate remains between the recess 1700 and the STI 400, as shown in FIG.
  • the etching of this step may not require a mask, but directly with the nitride layer and the sidewall spacer. Mask.
  • a source/drain stress layer 300 is epitaxially grown in the EJ trench 1700 with the partial semiconductor substrate as a seed layer, thereby generating stress on both sides of the channel to improve carrier mobility of the channel.
  • the first sidewall 600 is partially formed on the active region 900 of the semiconductor substrate, a portion of the semiconductor substrate, that is, the recess 1700, remains between the recess 1700 and the STI 400 after RIE etching.
  • the sidewalls are semiconductor substrate materials instead of STI materials, so that source/drain regions (ie, source/drain stress layers 300 in the embodiment of the present invention) can be formed by epitaxial growth of the seed layer, thereby improving source/drain regions. quality.
  • the method of epitaxially growing the source/drain stress layer 300 includes: for example, for an nMOSFET, a source/drain stress layer having a tensile stress may be formed by epitaxially growing Si: C in a specific ratio, wherein Si: C The content of C is preferably 0.2% to 2%, and may be doped with phosphorus or arsenic in situ as needed; for pMOSFET, a source/drain stress layer having compressive stress may be formed by epitaxially growing SiGe with a specific ratio of Ge. Among them, the Ge content in SiGe is preferably 15% to 70%, and in-situ boron doping can be performed as needed.
  • step E further comprising: forming a metal silicide 1800 on top of the gate stack 200, the dummy gate 500, and the source/drain stress layer 300, as shown in FIG.
  • the formation of the metal silicide may be performed by a method known to those skilled in the art.
  • the embodiment of the present invention is illustrated by taking NiPtSi as an example. First, the RIE covers the nitride layer 1600 over the gate stack 200 and the dummy gate 500 to expose the gate stack 200.
  • the top of the dummy gate 500 depositing metal materials such as Ni and Pt, and annealing, metal Ni and Pt with the silicon substrate (ie, the polysilicon in the gate stack 200 and the dummy gate 500) or the silicon-containing substrate (ie, the source)
  • the silicon in the /drain stress layer 300 reacts to form NiPtSi, and then the unreacted Ni and Pt are dry or wet etched, that is, the metal silicide NiPtSi is formed.
  • the present invention can effectively prevent the STI height from being over-cleaned by subsequent formation of STIs in the MOSFET device that are higher or flatter than the source/drain stress layer, and the addition of dummy gates and sidewall spacers on the STI.
  • Process reductions such as etching can reduce or avoid channel stress loss, which is beneficial to enhance device performance.
  • the added dummy gate sidewall portion is located on the active region of the semiconductor substrate, and a portion of the substrate may be left on the STI-side when the source/drain region recess is formed by etching, and thus the seed layer may be epitaxially grown. Source/drain regions are formed to improve source/drain region quality.

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Description

半导体结构及其形成方法
本申请要求于 2010 年 10 月 28 日提交中国专利局、 申请号为 201010529707.3、 发明名称为"半导体结构及其形成方法"的中国专利申请的优 先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及半导体制造技术领域， 特别涉及一种具有源 /漏应力层和浅沟 槽隔离的半导体结构及其形成方法。 背景技术
随着半导体技术的持续发展， 半导体器件尺寸不断减小， 尤其是集成 电路中间距（IC pitch ) 的减小， 有利于降低制造成本。 但是， 如何在缩小 尺寸的同时保持甚至增强器件性能， 是当前半导体技术面临的一大挑战。
例如， 当 MOSFET (金属氧化物半导体场效应晶体管） 的器件间距低 于 150nm时， STI (浅沟槽隔离） 与源 /漏应力层之间的很容易产生负面边 界效应而导致沟道应力损耗， 从而降低器件性能， 如图 1所示。 图 la为理 想情况下， STI 10的顶部高于源 /漏应力层 20的顶部， 从而使沟道 30保持 强应力的理想结构。 但实际情况下， 如图 lb 所示， 制备过程中的过度清 洗、 干法或湿法刻蚀等工艺而导致 STI高度损耗， 当 STI 10顶部低于源 / 漏应力层 20的顶部时， 产生应力释放， 即沟道应力损耗。 发明内容
本发明的目的旨在至少解决上述技术问题之一， 特别是解决 MOSFET 器件的沟道应力由于 STI与源 /漏应力层之间的边界效应而损耗的问题， 同 时本发明提出的半导体结构和方法， 还有利于善源 /漏区质量。
为达到上述目的， 一方面， 本发明提出一种半导体结构， 包括： 半导 体衬底； 位于所述半导体衬底上的栅堆叠； 位于所述栅堆叠两侧且嵌入所 述半导体衬底中的源 /漏应力层； 嵌入所述半导体衬底中的浅沟槽隔离， 所 述浅沟槽隔离的顶部高于或持平于所述源 /漏应力层的顶部， 所述浅沟槽隔 离将所述半导体衬底隔离为不同的有源区； 所述浅沟槽隔离的顶部形成有 虚拟栅， 所述虚拟栅的侧壁形成有第一侧墙， 所述第一侧墙部分位于所述 有源区上。
可选地， 对于 pMOS场效应晶体管， 所述源 /漏应力层包括 Ge含量为 15%-70%的 SiGe; 对于 nMOS场效应晶体管， 所述源 /漏应力层包括 C含 量为 0.2%-2%的 Si:C。
可选地， 所述栅堆叠侧壁形成有第二侧墙。
其中， 所述第一侧墙部分位于所述半导体衬底的有源区上， 一方面， 可以对所述浅沟槽隔离形成完全覆盖， 以保护其在后续的过度清洗及刻蚀 等工艺中不被破坏， 另一方面， 可以在所述浅沟槽隔离一侧保留部分衬底， 进而可以以此为种晶层外延生长形成源 /漏区， 从而改善源 /漏区质量。
另一方面， 本发明提出一种上述半导体结构的形成方法， 包括以下步 骤： A. 提供半导体衬底； B. 嵌入所述半导体衬底形成浅沟槽隔离， 以 使所述半导体衬底形成相互隔离的有源区， 其中， 所述浅沟槽隔离的顶部 高于或持平于所述有源区的顶部； C. 在所述有源区上形成栅堆叠， 在所 述浅沟槽隔离上形成虚拟栅； D. 在所述虚拟栅的侧壁形成第一侧墙， 所 述第一侧墙部分位于所述有源区上； E. 在所述栅堆叠两侧、 嵌入所述半 导体衬底形成源 /漏应力层， 所述浅沟槽隔离的顶部高于或持平于所述源 / 漏应力层的顶部。
可选地， 步骤 B所述形成浅沟槽隔离包括以下步骤： 在所述半导体衬 底上形成硬掩膜层； 刻蚀所述硬掩膜层及半导体衬底以形成沟槽； 填充所 述沟槽形成绝缘层； 回刻 （etch back ) 所述绝缘层， 以使所述绝缘层的顶 部高于或持平于所述有源区的顶部； 去除所述硬掩膜层。
可选地， 步骤 D还包括： 同时在所述栅堆叠侧壁形成第二侧墙。
可选地， 在形成所述第一侧墙和第二侧墙之前， 还包括： 在所述半导体 衬底的有源区进行倾角离子注入以形成晕圈 （ halo ) 注入区， 和 /或进行倾 角离子注入以形成源 /漏延伸区。
可选地， 步骤 E形成所述源 /漏应力层包括： 以所述第一侧墙和第二侧 墙为掩膜进行刻蚀， 以在所述半导体衬底中、 所述栅堆叠两侧形成凹槽， 其中， 所述 EJ槽与所述浅沟槽隔离之间保留部分半导体衬底； 在所述 EJ槽 内、 以所述部分半导体衬底为种晶层外延生长形成源 /漏应力层。
可选地， 所述外延生长形成源 /漏应力层包括： 对于 pMOS场效应晶体 管，在所述凹槽内外延生长 Ge含量为 15%-70%的 SiGe;对于 nMOS场效应 晶体管， 在所述凹槽内外延生长 C含量为 0.2%-2%的 Si:C。
本发明通过在 MOSFET器件中，形成高于或持平于源 /漏应力层的 STI, 以及在 STI上增加虚拟栅和侧墙的器件结构及其形成方法， 该结构可以有 效地阻止 STI的高度被后续的过度清洗及刻蚀等工艺削减， 从而降低或者 避免沟道应力损耗， 有利于增强器件性能。 并且， 增加的虚拟栅侧墙部分 位于半导体衬底的有源区上， 可以在刻蚀形成源 /漏区凹槽时在 S T I—侧保 留部分衬底， 进而可以以此为种晶层外延生长形成源 /漏区， 从而改善源 / 漏区质量。
本发明附加的方面和优点将在下面的描述中部分给出， 部分将从下面 的描述中变得明显， 或通过本发明的实践了解到。
附图说明 通过附图所示， 本发明的上述及其它目的、 特征和优势将更加清晰。 在全 部附图中相同的附图标记指示相同的部分。并未刻意按实际尺寸等比例缩放绘 制附图， 重点在于示出本发明的主旨。
图 1为现有技术的 MOSFET器件中 STI与源 /漏应力层之间的结构关系 示意图， 其中， 图 la 和图 lb分别为理想情况和实际情况的结构示意图。
图 2为本发明实施例的半导体结构剖面图；
图 3- 12为形成本发明实施例的半导体结构的方法的中间步骤示意图。 具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂， 下面结合附图对 本发明的具体实施方式做详细的说明。 下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结 构。 为了筒化本发明的公开， 下文中对特定例子的部件和设置进行描述。 当然， 它们仅仅为示例， 并且目的不在于限制本发明。 此外， 本发明可以 在不同例子中重复参考数字和 /或字母。 这种重复是为了筒化和清楚的目 的， 其本身不指示所讨论各种实施例和 /或设置之间的关系。 此外， 本发明 提供了的各种特定的工艺和材料的例子， 但是本领域普通技术人员可以意 识到其他工艺的可应用于性和 /或其他材料的使用。 另外， 以下描述的第一 特征在第二特征之 "上" 的结构可以包括第一和第二特征形成为直接接触 的实施例， 也可以包括另外的特征形成在第一和第二特征之间的实施例， 这样第一和第二特征可能不是直接接触。 图 2所示为本发明实施例的半导体结构剖面图， 该结构包括： 半导体 衬底 100; 位于半导体衬底 100上的栅堆叠 200; 位于栅堆叠 200两侧且嵌 入半导体衬底 100中的源 /漏应力层 300;嵌入半导体衬底 100中的 STI 400, STI 400的顶部高于或持平于源 /漏应力层 300的顶部， STI 400的顶部形成 有虚拟栅 500 , 虚拟栅 500 的侧壁形成有第一侧墙 600。 其中， 第一侧墙 600部分位于半导体衬底 100的有源区 900上， 目的在于： 一方面， 可以 对虚拟栅 500之下的 STI 400形成完全覆盖， 以保护其在后续的过度清洗 及刻蚀等工艺中不被破坏； 另一方面， 可以在刻蚀形成源 /漏区时在所述浅 沟槽隔离一侧保留部分衬底， 进而可以此为种晶层外延生长形成， 从而改 善源 /漏区质量。 另外， 本发明所述 "持平" 的含义为： 意指两平面之间的 高度之差在工艺或制程允许的范围内。
可选地， 栅堆叠 200的侧壁形成有第二侧墙 700; 对于 pMOSFET, 源 /漏应力层 300可以包括 Ge含量为 15%-70%的 SiGe , 以对沟道产生压应力 ( compressive stress ) , 而对于 nMOSFET, 源 /漏应力层 300包括 C含量为 0.2%-2%的 Si:C , 以对沟道产生拉应力 （tensile stress ) , 并且对 SiGe和 Si:C均可以进行原位掺杂以提高其应力效果； 栅堆叠 200、 虚拟栅 500以 及源 /漏应力层 300顶部分别形成有金属硅化物 1800 , 例如可以是 NiPtSi。 以上已经根据附图描述根据本发明的实施例的半导体结构。 需要注意 的是， 本领域技术人员能够根据上述的场效应晶体管结构可以选择多种工 艺进行制造， 例如不同类型的产品线， 不同的工艺流程等等， 但是这些工 艺制造的场效应晶体管结构只要具有与本发明基本相同的结构， 达到基本 相同的效果， 那么也应包含在本发明的保护范围之内。 为了能够更清楚的 理解本发明， 以下将具体描述形成本发明上述场效应晶体管的方法及工艺， 还需要说明的是， 以下步骤仅是示意性的， 并不是对本发明的限制， 本领 域技术人员还可通过其他工艺实现。 以下实施例是本发明的优选实施例， 能够有效降低制造成本。
根据本发明实施例的半导体结构的形成方法， 包括以下步骤： 步骤 A: 提供半导体衬底 100。 衬底 100以体硅为例， 但实际应用中， 衬底可以包括任何适合的半导体衬底材料， 具体可以是但不限于硅、 锗、 锗化硅、 soi (绝缘体上硅） 、 碳化硅、 砷化镓或者任何 m/v族化合物半 导体等。 根据现有技术公知的设计要求 （例如 p型衬底或者 n型衬底） ， 衬底 100可以包括各种掺杂配置。 此外， 衬底 100可以可选地包括外延层， 可以被应力改变以增强性能。
步骤 B: 嵌入半导体衬底 100形成 STI 400 , 以使半导体衬底 100形成 相互隔离的有源区 900 , 其中， STI 400的顶部高于或持平于有源区 900的 顶部。 具体地， 首先如图 3所示， 在半导体衬底 100上形成一氧化物衬垫 800 (如氧化硅） ， 其厚度可以为 10-20nm, 接着在氧化物衬垫 800上形成 硬掩膜层 1000 (如氮化硅）， 其厚度可以为 30-150nm, 然后利用预设 STI 图 案的掩膜板在氮化物层 1000上形成图案化的光刻胶 1100。 需指出地是， 本发 明实施例中的介质 （如氧化物衬垫 800、 氮化物层 1000、 高 k介质层 1400、 第一侧墙 600及第二侧墙 700等）的形成方法， 若无特别说明， 均可以采用 常规沉积工艺形成， 如溅射、 脉冲激光淀积（PLD ) 、 金属有机化学气相淀 积（ MOCVD )、原子层淀积（ ALD )、 等离子体增强原子层淀积（ PEALD ) 、 等离子体增强化学气相淀积（PECVD ) 或其他合适的方法。
然后， 以光刻胶 1100为掩膜， 依次刻蚀硬掩膜层 1000、 氧化物衬垫 800 以及半导体衬底 100 , 以形成沟槽 1200, 如图 4所示。 其中， 刻蚀可以采 用反应离子刻蚀 （ RIE ) , 刻蚀深度可以为 100-500nm。
接着， 去除光刻胶 1100 , 在沟槽 1200内形成绝缘层 1300 , 例如可以 淀积氧化物（如氧化硅） ， 并进行平坦化处理， 如化学机械抛光（CMP ) , 以氮化物层 1000为停止面， 如图 5所示。
接着， 回刻绝缘层 1300 , 以使其表面高于或持平于所述有源区 900的 表面， 如图 6所示。
最后， 去除硬掩膜层 1000 (氮化硅）， 形成 STI 400, 从而使半导体衬底 100形成相互隔离的有源区 900 , 其中， STI 400的顶部高于或持平于有源 区 900的顶部， 优选地， STI 400的顶部高于有源区表面， 如图 7所示。 氮 化物层 1000的去除可以通过相对于其下的氧化物选择性刻蚀氮化物。
步骤 C:在有源区 900上形成栅堆叠 200,在 STI 400上形成虚拟栅 500。 具体地， 如图 8所示， 首先部分刻蚀氧化物衬垫 800 , 以形成一层更薄的 氧化物作为栅介质层 1400。 可选地， 栅介质层 1400也可以是高 k介质， 这种情况下， 先完全刻蚀掉氧化物衬垫 800 , 再形成高 k介质作为栅介质 层 1400 , 高 k介质层的厚度可以为 l-3nm, 高 k介质材料包括例如铪基材 料， 如氧化铪 ( Hf02 ) , 氧化铪硅（HfSiO ) , 氮氧化铪硅 ( HfSiON ) , 氧化铪钽（ HfTaO ) , 氧化铪钛（ HfTiO ) , 氧化铪锆 （ HfZrO ) , 其组合 和 /或者其它适当的材料。 然后， 在栅介质层 1400 上形成栅导电层 （图 8 中未示出）， 可以是金属层， 通过如 PVD (物理气相淀积， 包括蒸发、 溅射、 电子束等）、 CVD (化学气相淀积）、 电镀或其他合适的方法形成。 接着， 淀 积多晶硅层 1500, 其厚度可以为 50-150nm, 再淀积氮化物层 1600 , 其厚 度可以为 20-50nm。
然后， 采用传统工艺形成栅堆叠 200及虚拟栅 500。 具体地， 可以按照 预设掩膜板形成图案化的光刻胶作为掩膜， 然后依次刻蚀氮化物层 1600、 多晶硅层 1500 , 以栅介质层 1400为停止面， 接着去除光刻胶， 形成如图 9 所示的栅堆叠 200和虚拟栅 500, 其中， 栅堆叠 200位于有源区 900上， 虚 拟栅 500位于 STI 400上。 步骤 D: 在虚拟栅 500的侧壁形成第一侧墙 600 , 第一侧墙 600部分位 于半导体衬底的有源区 900上， 可选地， 同时在栅堆叠 200的侧壁形成第 二侧墙 700, 如图 10所示。 第一侧墙和第二侧墙的材料可以相同， 例如可 以由氮化硅、 氧化硅、 氮氧化硅、 碳化硅、 氟化物掺杂硅玻璃、 低 k电介 质材料中的一种或其组合， 和 /或其他合适的材料形成。 侧墙的形成可以通 过先淀积介质材料然后进行反应离子刻蚀， 以栅介质层 1400为停止面。 需 注意地是， 所述第一侧墙 600部分位于 STI 400之上、 部分位于半导体衬 底的有源区 900上， 如图 10所示。 形成该结构的目的在于： 一方面， 可以 对 STI 400形成完全覆盖， 以保护其在后续的过度清洗及刻蚀等工艺中不 被破坏， 另一方面， 可以在后续刻蚀形成源 /漏区时在 STI 400—侧保留部 分衬底，进而可以此为种晶层外延生长形成源 /漏区，从而改善源 /漏区质量。
可选地， 在形成第一侧墙和第二侧墙之前， 可以根据需要， 在半导体衬 底的有源区 900进行倾角离子注入以形成晕圈（halo )注入区（图中未示出 ), 和 /或进行倾角离子注入以形成源 /漏延伸区 （图中未示出） ， 例如， 对于 nMOSFET, 可以采用 p型掺杂剂例如 B、 BF2 或其组合进行倾角离子注入以 形成 halo注入区， 采用 n型掺杂剂例如 As、 P或其组合进行倾角离子注入 以形成源 /漏延伸区； 对于 pMOSFET, 采用 n型掺杂剂例如 As、 P或其组合 进行倾角离子注入以形成 halo注入区， 可以采用 p型掺杂剂例如 B、 BF2 或 其组合进行倾角离子注入以形成源 /漏延伸区。
步骤 E:在栅堆叠 200两侧、嵌入半导体衬底 100形成源 /漏应力层 300, STI 400的顶部高于或持平于源 /漏应力层 300的顶部。 具体地， 以第一侧 墙 600和第二侧墙 700为掩膜，通过 RIE刻蚀栅介质层 1400以及半导体衬 底 100, 以在半导体衬底 100中、 栅堆叠 200两侧形成凹槽 1700 , 其中， 凹槽 1700与 STI 400之间保留部分半导体衬底， 如图 11所示。 需指出地 是， 由于有氮化物层 1600和第一侧墙 600及第二侧墙 700的保护， 此步骤 的刻蚀可以不需要掩膜板， 而直接以所述氮化物层和侧墙为掩膜。
接着， 在 EJ槽 1700内、 以所述部分半导体衬底为种晶层外延生长形成 源 /漏应力层 300 , 从而对沟道两侧产生应力以提高沟道的载流子迁移率， 如图 12所示。 需指出地是， 由于第一侧墙 600部分形成于半导体衬底的有 源区 900上， 故经 RIE刻蚀后， 凹槽 1700与 STI 400之间保留了部分半导 体衬底， 即凹槽 1700的侧壁为半导体衬底材料而非 STI材料， 因此可以以 此为种晶层外延生长形成源 /漏区（即本发明实施例中的源 /漏应力层 300 ) , 从而改善源 /漏区质量。具体地，外延生长形成源 /漏应力层 300的方法包括： 例如， 对于 nMOSFET , 可以采用外延生长 C含量为特定比例的 Si:C形成 具有拉应力的源 /漏应力层， 其中， Si:C中 C含量优选的为 0.2%-2% , 并且 可以根据需要进行原位磷或砷掺杂； 对于 pMOSFET , 可以采用外延生长 Ge含量为特定比例的 SiGe形成具有压应力的源 /漏应力层， 其中， SiGe中 Ge含量优选的为 15%-70% , 并且可以根据需要进行原位硼掺杂。
可选地， 步骤 E之后还包括： 在栅堆叠 200、 虚拟栅 500以及源 /漏应 力层 300的顶部分别形成金属硅化物 1800 , 如图 2所示。 金属硅化物的形 成可以采用本领域技术人员所公知的方法， 本发明实施例以 NiPtSi为例说 明， 首先 RIE覆盖在栅堆叠 200和虚拟栅 500之上的氮化物层 1600 , 以暴 露栅堆叠 200和虚拟栅 500的顶部， 然后沉积金属材料如 Ni和 Pt, 并进行 退火， 金属 Ni和 Pt与硅衬底 （即栅堆叠 200和虚拟栅 500中的多晶硅 ) 或含硅的衬底 （即源 /漏应力层 300中的硅）反应生成 NiPtSi, 接着干法或 湿法刻蚀掉未反应的 Ni和 Pt, 即形成金属硅化物 NiPtSi。
本发明通过在 MOSFET器件中，形成高于或持平于源 /漏应力层的 STI, 以及在 STI上增加虚拟栅和侧墙的器件结构， 该结构可以有效地阻止 STI 的高度被后续的过度清洗及刻蚀等工艺削减， 从而降低或者避免沟道应力 损耗， 有利于增强器件性能。 并且， 增加的虚拟栅侧墙部分位于半导体衬 底的有源区上， 可以在刻蚀形成源 /漏区凹槽时在 STI—侧保留部分衬底， 进而可以以此为种晶层外延生长形成源 /漏区， 从而改善源 /漏区质量。 虽然本发明已以较佳实施例披露如上， 然而并非用以限定本发明。任何熟 悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭 示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为 等同变化的等效实施例。 因此， 凡是未脱离本发明技术方案的内容， 依据本发 明的技术实质对以上实施例所做的任何筒单修改、等同变化及修饰， 均仍属于 本发明技术方案保护的范围内。
本发明说明书中各个实施例采用递进的方式描述，每个实施例重点说明的 都是与其他实施例的不同之处， 各个实施例之间相同相似部分互相参见即可。 对所公开的实施例的上述说明， 使本领域专业技术人员能够实现或使用本发 明。 对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的， 本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它 实施例中实现。 因此， 本发明将不会被限制于本文所示的这些实施例， 而是要 符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims

权 利 要 求
1、 一种半导体结构， 包括：
半导体衬底；
位于所述半导体衬底上的栅堆叠；
位于所述栅堆叠两侧且嵌入所述半导体衬底中的源 /漏应力层； 嵌入所述半导体衬底中的浅沟槽隔离， 所述浅沟槽隔离的顶部高于或 持平于所述源 /漏应力层的顶部， 所述浅沟槽隔离将所述半导体衬底隔离为 不同的有源区；
所述浅沟槽隔离的顶部形成有虚拟栅， 所述虚拟栅的侧壁形成有第一 侧墙， 所述第一侧墙部分位于所述有源区上。
2、 如权利要求 1所述的半导体结构， 其特征在于：
对于 pMOS场效应晶体管， 所述源 /漏应力层包括 Ge含量为 15%-70% 的 SiGe;
对于 nMOS场效应晶体管，所述源 /漏应力层包括 C含量为 0.2%-2%的 Si:C。
3、 如权利要求 1所述的半导体结构， 其特征在于： 所述栅堆叠侧壁形 成有第二侧墙。
4、 一种半导体结构的形成方法， 包括以下步骤：
A. 提供半导体衬底；
B. 嵌入所述半导体衬底形成浅沟槽隔离， 以使所述半导体衬底形成相 互隔离的有源区， 其中， 所述浅沟槽隔离的顶部高于或持平于所述有源区 的顶部；
C. 在所述有源区上形成栅堆叠， 在所述浅沟槽隔离上形成虚拟栅；
D. 在所述虚拟栅的侧壁形成第一侧墙，所述第一侧墙部分位于所述有 源区上；
E. 在所述栅堆叠两侧、 嵌入所述半导体衬底形成源 /漏应力层， 所述 浅沟槽隔离的顶部高于或持平于所述源 /漏应力层的顶部。
5、 如权利要求 4所述的形成方法， 其特征在于， 所述步骤 B形成浅沟 槽隔离包括以下步骤：
在所述半导体衬底上形成硬掩膜层；
刻蚀所述硬掩膜层及半导体衬底以形成沟槽；
填充所述沟槽形成绝缘层；
回刻所述绝缘层， 以使所述绝缘层的顶部高于或持平于所述有源区的 顶部；
去除所述硬掩膜层。
6、 如权利要求 4所述的形成方法， 其特征在于， 所述步骤 D还包括： 同时在所述栅堆叠侧壁形成第二侧墙。
7、 如权利要求 6所述的形成方法， 其特征在于， 在形成所述第一侧墙 和第二侧墙之前， 还包括：
在所述半导体衬底的有源区进行倾角离子注入以形成晕圈注入区， 和 / 或进行倾角离子注入以形成源 /漏延伸区。
8、 如权利要求 6所述的形成方法， 其特征在于， 所述步骤 E形成源 / 漏应力层包括以下步骤：
以所述第一侧墙和第二侧墙为掩膜进行刻蚀， 以在所述半导体衬底中、 所述栅堆叠两侧形成 EJ槽， 其中， 所述 EJ槽与所述浅沟槽隔离之间保留部 分半导体衬底；
在所述 EJ槽内、 以所述部分半导体衬底为种晶层外延生长形成源 /漏应 力层。
9、 如权利要求 8所述的形成方法， 其特征在于， 所述外延生长形成源 /漏应力层包括：
对于 pMOS场效应晶体管，在所述凹槽内外延生长 Ge含量为 15%-70% 的 SiGe;
对于 nMOS场效应晶体管， 在所述凹槽内外延生长 C含量为 0.2%-2% 的 Si:C。
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