CN103137624A - 高栅极密度器件和方法 - Google Patents

高栅极密度器件和方法 Download PDF

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CN103137624A
CN103137624A CN2012100367810A CN201210036781A CN103137624A CN 103137624 A CN103137624 A CN 103137624A CN 2012100367810 A CN2012100367810 A CN 2012100367810A CN 201210036781 A CN201210036781 A CN 201210036781A CN 103137624 A CN103137624 A CN 103137624A
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semiconductor substrate
semiconductor device
epitaxial growth
isolated
dummy gate
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CN103137624B (zh
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谢铭峰
张长昀
陈欣志
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了一种具有隔离部件的半导体器件。所述半导体器件包括多个设置在半导体衬底上的栅极结构、形成在所述多个栅极结构的各个侧壁上的多个电介质材料的侧壁间隔件、设置在所述半导体衬底和所述栅极结构上的层间电介质(ILD)、嵌入所述半导体衬底并延伸至所述ILD的隔离部件以及设置在所述隔离部件的延伸部的侧壁上的电介质材料的侧壁间隔件。本发明还公开了高栅极密度器件和方法。

Description

高栅极密度器件和方法
技术领域
本发明涉及半导体技术领域，更具体地，涉及高栅极密度器件和方法。
背景技术
当诸如金属氧化物半导体场效应晶体管(MOSFET)的半导体器件通过各技术节点减小尺寸时，为改进器件性能已采用了多种方式，诸如使用高-K(HK)电介质材料和金属栅极(MG)电极结构、应变工程、3-D栅极晶体管和超薄体(UTB)绝缘上的半导体(SOI)结构。例如，通过实施应变的衬底技术，更好的器件性能通常可通过调节晶体管沟道内的应力来实现，这增强迁移率(例如，电子或空穴的迁移率)以及沟道内的电导率。作为应变技术的一个例子，外延硅锗(SiGe)层或者硅磷(SiP)层分别形成在p型场效应晶体管(PFET)器件或n型场效应晶体管(PFET)器件中的源极区和漏极区。
随着器件尺寸缩小以及器件密度增加，相邻结构的一致性可能受到影响。因此，尽管目前的方法总体上足以适合他们的预期目的，然而他们并不是在各个方面都令人完全满意。例如，当浅沟槽隔离(STI)在附近的硅锗外延结构形成之前形成时，最后得到的硅锗外延结构可能与远离STI的另一硅锗外延结构有很大区别。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，涉及具有隔离部件的半导体器件。示例性的半导体器件包括多个设置在半导体衬底上的栅极结构、在所述多个栅极结构的各个侧壁上形成的多个由电介质材料制成的栅极侧壁间隔件、设置在半导体衬底和栅极结构上的层间电介质(ILD)、嵌入半导体衬底并延伸至所述ILD的隔离部件以及设置在所述隔离部件的延伸部的侧壁上的由电介质材料制成的侧壁间隔件。
在可选实施方式中，半导体器件进一步包括靠近所述隔离部件和靠近所述栅极结构的外延生长区。
在可选实施方式中，所述外延生长区彼此具有相同的形状。
在可选实施方式中，所述外延生长区彼此具有相同的晶面。
在可选实施方式中，所述外延生长区包括硅锗。
在可选实施方式中，所述隔离部件包括在所述隔离部件的上部上的侧壁间隔件。
在可选实施方式中，所述隔离部件的轮廓与所述侧壁间隔件的边缘对准。
在可选实施方式中，所述侧壁间隔件包括氮化硅。
在可选实施方式中，所述隔离部件包括一种或多种电介质材料。
在可选实施方式中，所述隔离部件的电介质材料包括氧化硅衬里。
在可选实施方式中，所述隔离部件的电介质材料包括在所述氧化硅衬里上方的氧化硅。
在本发明一方面的另一种实施方式中，半导体器件包括硅衬底；设置在衬底上的两个高-k/金属栅极(HK/MG)部件；形成在所述HK/MG部件的各个侧壁上的多个电介质材料的栅极间隔件；形成在所述两个HK/MG部件间的多个外延生长硅锗区，其中所述外延生长区彼此间具有相同的形状和相同的晶面；设置在半导体衬底和HK/MG部件上的ILD；嵌入所述半导体衬底中并延伸至所述ILD的隔离部件以及设置在所述隔离部件的延伸部的侧壁上的电介质材料的侧壁间隔件。
本发明的另一方面涉及使用“后隔离”方法形成半导体器件的方法。该方法包括提供半导体衬底，在所述衬底上形成多个伪栅极结构，在伪栅极结构的侧壁上形成栅极侧壁间隔件，在所述伪栅极结构之间形成多个外延生长区，在形成多个外延生长区后去除所述伪栅极结构中之一来形成隔离沟槽，用电介质层填充所述隔离沟槽从而形成隔离部件，去除剩余的伪栅极结构来形成栅极沟槽以及在所述栅极沟槽内形成栅极结构。
在可选实施方式中，所述隔离沟槽的上部具有与所述伪栅极结构相似的轮廓。
在可选实施方式中，所述隔离沟槽蚀刻包括第一部分，所述第一部分为去除所述伪栅极部件并且暴露所述半导体衬底以形成所述隔离沟槽的上部。
在可选实施方式中，所述方法进一步包括蚀刻的第二部分，所述第二部分为蚀刻所述半导体衬底从而形成所述隔离部件的下部。
在可选实施方式中，所述蚀刻的第二部分使所述侧壁间隔件的边缘自对准。
在可选实施方式中，所述隔离沟槽形成有上部和下部，其中所述上部在所述ILD内，所述下部在所述半导体衬底内。
在可选实施方式中，所述隔离沟槽用多层电介质层和氧化硅衬里填充。
在可选实施方式中，所述多层电介质层中的一层为设置在所述氧化硅衬里上的氧化硅层。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的数量和尺寸可以被任意增加或减少。
图1是根据本发明各方面的制造具有隔离部件的半导体器件的方法实例的流程图；
图2至图6是根据本发明各方面的具有隔离部件的半导体器件在实施的制造阶段的示例实施方式的截面图。
具体实施方式
可以理解的是，以下公开的内容提供了多种不同实施例或实例，用于实现本发明的不同部件。以下将描述组件和布置的具体实例以简化本发明。当然，这些仅是实例并且不旨在限制本发明。另外，描述中在另一工艺之前实施一工艺可包括在紧接一工艺之后实施另一工艺的实施例，还可包括在一工艺和另一工艺之间增加额外工艺的实施例。为了简单和清楚起见，各种部件可被任意地以不同尺寸绘制。此外，以下描述的一部件在另一部件上形成可以包括这些部件以直接接触方式形成，也可以包括额外部件介于这些部件之间使得它们以不直接接触方式形成的实施例。
图1是根据本发明的各个方面的方法100的一种示例实施方式的流程图，该方法用于制造具有隔离部件的半导体器件。结合图2至图6描述方法100。在“后栅极”(或替换栅极)方案中，首先形成伪(牺牲的)栅极结构，其后是正常的互补的金属氧化物半导体(CMOS)工艺流程直至层间电介质(ILD)沉积。然后可去除一些伪栅极结构以形成沟槽隔离部件。剩下的伪栅极可用金属栅极结构替换。因而，所述栅极在高温工序已在诸如源区和漏区的形成中采用之后形成。
参考图1和图2，方法100开始于步骤102：提供半导体衬底210。半导体衬底210包括硅。可选地或另外地，衬底210可包括其他基本的半导体，例如锗，诸如碳化硅SiC、砷化镓、砷化铟、或磷化铟的化合物半导体，或诸如硅锗SiGe、硅锗碳化物、镓砷磷化物或镓铟磷化物的合金半导体。
在一种实施方式中，衬底210包括外延层。所述衬底可具有覆盖在块状半导体(bulk semiconductor)上的外延层。进一步地，为了提高性能，可使衬底210产生应变。例如，所述外延层可包括不同于那些块状半导体的半导体材料，例如通过包括选择性外延生长(SEG)的工艺形成覆盖在块状硅上的硅锗层或覆盖在块状硅锗上的硅层。此外，衬底210可包括绝缘体上的半导体(SOI)结构。在一种实施方式中，所述衬底可包括通过诸如注氧隔离(SIMOX)方法或其他诸如晶片接合和研磨的合适技术形成的嵌入氧化物(BOX)层。实际上，各种实施方式可包括多种衬底结构和材料中的任何一种。在所描述的实施方式中，衬底210包括硅衬底。
继续参考图2，衬底210还包括通过沉积、图案化和蚀刻技术形成的栅极结构220。栅极结构220包括伪栅极结构。伪栅极结构指的是在后续工艺中用金属栅极替换的栅极结构。在所描述的实施方式中，栅极结构220包括伪栅极结构。伪栅极结构220包括伪栅极层221，诸如多晶硅、非晶硅或其他合适的材料。伪栅极层221通过沉积技术沉积在衬底210上。例如，在化学气相沉积(CVD)工艺中可使用硅烷(SiH4)、乙硅烷(Si2H6)或二氯化硅烷(SiCl2H4)作为化学气体来形成多晶硅层。可选地以及另外地，诸如二氧化硅(SiO2)或氮氧化硅(SiON)的伪氧化物层(未示出)通过热氧化、化学氧化、CVD、原子层沉积(ALD)或任何合适方法沉积在衬底210上。此后，伪栅极层221沉积在伪氧化物层上。
另外，蚀刻停止层(ESL)223可形成在伪栅极层221的顶部上。在一种实施方式中，ESL223包括接触蚀刻停止层(CESL)。ESL223可包括氮化硅、氧化硅、氮氧化硅SiON和/或其他合适材料。ESL223可通过等离子增强化学气相沉积(PECVD)、物理气相沉积(PVD)和/或本领域熟知的其他沉积工艺形成。在所描述的实施方式中，伪栅极层221包括多晶硅以及ESL223包括氮化硅。如图2所示，用常规方法图案化和蚀刻ESL223和伪栅极层221来形成伪栅极结构220。
衬底210还可包括通过注入技术形成的诸如p阱和n阱(未示出)的各种掺杂区。作为一个例子，衬底210的一部分是p型掺杂并且形成n沟道器件将在此构造的p阱。相似地，衬底210的另一部分是n型掺杂并且形成p沟道器件将在此构造的n阱。所述掺杂区用p型掺杂物诸如硼或二氟化鹏(BF2)掺杂和/或n型掺杂物诸如磷或砷掺杂。所述掺杂区可直接形成在衬底210上，p阱结构、n阱结构、双阱结构中或使用突起结构形成。
衬底210可进一步包括通过适当技术，例如一种或多种离子注入技术，形成的源极和漏极(S/D)区(未示出)。所述S/D区可进一步包括与伪栅极结构220大体对准的轻掺杂源/漏区(LDD)，以及与相关的栅极侧壁间隔件230大体对准的重掺杂S/D区(未示出)，这将在下文描述。
通常，在形成所述S/D区后，施行一种或多种退火工艺以激活所述S/D区。所述退火工艺包括快速热退火(RTA)、激光退火工艺或其他合适的退火工艺。作为一个例子，高温热退火步骤可施加在900℃至1100℃范围内的任何温度，然而其他实施方式可使用在不同范围内的温度。可选地，高温退火可包括使用600℃以上温度的热工艺。这种实施方式可进一步包括具有很短时间段的“脉冲”退火工艺。
参考图2，栅极侧壁间隔件230形成在栅极结构220的侧壁上。栅极侧壁间隔件230通常包括诸如氧化硅的电介质材料。可选地，栅极侧壁间隔件230可包括氮化硅、碳化硅SiC、氮氧化硅SiON或它们的组合物。用于栅极侧壁间隔件230的典型形成方法包括在栅极结构220上沉积电介质材料以及随后各向异性地回蚀刻电介质材料。在所描述的实施方式中，栅极侧壁间隔件230包括氮化硅。
如图3所示，方法100进入步骤104，在步骤104中实施外延生长工艺来形成外延生长区240。作为一个例子，可首先实施蚀刻工艺来在衬底210上形成凹槽，然后应用外延生长工艺在该凹槽区中生长外延生长区240。外延生长区240可包括在衬底210的p型金属氧化物半导体(PMOS)晶体管区内的硅锗SiGe(而n型金属氧化物(NMOS)晶体管区可由图案掩膜层保护)。在一种实施方式中，外延生长区240可包括在NMOS晶体管区内的SiP(而PMOS晶体管区可由图案掩膜层保护)。可选地，许多外延生长材料的实施方式适合于工艺，例如硅、锗、砷化镓、磷化铟、碳化硅、磷化硅、磷碳化硅和/或其他合适材料。
此外，外延生长区240可成形为突起在衬底210的表面上。在一些实施方式中，外延生长区240可使用诸如硼或铟的p型杂质进行原位掺杂以形成PMOS器件的S/D区。
外延生长区240可给PFET和NFET的相关沟道提供适当的应力效应以增强载流子迁移率并改善器件性能。为了在所有相关沟道上具有一致的应变效应，期望在所有相关的区域中具有相同的外延生长区240。
继续参考图3，层间电介质(ILD)层250形成在衬底210和伪栅极结构220上。层间电介质(ILD)层250可通过CVD、高密度等离子体CVD、旋转涂覆法、溅射和/或其他合适方法形成。层间电介质(ILD)层250通常包括氧化硅，氮氧化硅SiON，低k材料，原硅酸四乙酯(TEOS)氧化物，未掺杂的硅玻璃或掺杂的氧化硅诸如硼磷硅玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸玻璃(PSG)、掺硼硅玻璃(BSG)和/或其他适合材料。在所描述的实施方式中，层间电介质(ILD)层250包括氧化硅。随后可实施化学机械抛光(CMP)工艺以去除过量的ILD层250从而使得伪栅极结构220的ESL223暴露。如图3所示，所述CMP工艺可为栅极结构220和ILD层250提供大致平坦的表面。
如图4所示，方法100进入步骤106：采用图案化和蚀刻技术形成隔离沟槽260。隔离沟槽260形成在需要电隔离的位置以隔离每个有源区或每个器件。光刻工艺形成图案化的光刻胶层255，此后通过使用光刻胶层255作为蚀刻掩膜来实施蚀刻。典型的光刻工艺可包括以下工艺步骤：对光刻胶层255进行涂覆、软烘烤、掩膜对准、曝光图案、曝光后烘烤、光刻胶显影、硬烘烤。该光刻工艺还可通过其他适当方法诸如无掩膜光刻、电子书写入、离子束写入或分子印迹来实施或替换。
参考图4，实施蚀刻工艺以形成隔离沟槽260。蚀刻工艺可包括几个蚀刻部分。多部分的蚀刻工艺可提供多个蚀刻阶段，并且每个蚀刻阶段可实现自己的蚀刻选择比和蚀刻轮廓，蚀刻选择比描述的是不同的被蚀刻的材料之间的蚀刻速率。可通过选择蚀刻类型和蚀刻条件来选择蚀刻选择比。
所述蚀刻刻工艺可包括干法蚀刻、湿法蚀刻或干法蚀刻和湿法蚀刻的组合。例如，湿法蚀刻工艺可包括暴露于含氢氧化物的溶液(例如氢氧化铵)、去离子水和或其他合适的蚀刻溶液中。在另一实施例中，干法蚀刻工艺可利用配备有电容耦合等离子体源的中密度等离子体蚀刻系统、配备有感应等离子体、螺旋波等离子体或电子回旋共振(ECR)等离子体的高密度等离子体蚀刻系统，其中暴露的材料通过等离子体各向异性地去除。
在每个干法蚀刻工艺中，蚀刻机制可具有物理机制(例如，辉光放电溅射或离子研磨)或化学机制(例如，纯等离子体蚀刻)或二者的组合(例如，反应离子蚀刻或RIE)。溅射依靠入射高能离子的指向性来以高度各向异性的方式蚀刻。纯等离子体蚀刻、化学机制蚀刻可对掩膜材料及其在下面的层实现非常高的选择性并且通常以各向同性方式蚀刻。组合物理和化学两种机制的蚀刻提供一种具有适当选择比的可控各向异性蚀刻。
例如，第一蚀刻部分可去除暴露的伪栅极结构220中的ESL223和伪栅极层221。作为另一个例子，第一蚀刻部分可设计为去除部分ILD250以为隔离沟槽260的上部形成宽开口。在其上部具有宽开口的隔离沟槽的轮廓可增强后续膜层填充工艺的顺应性。在所描述的实施方式中，第一蚀刻部分包括含氟等离子体蚀刻，例如与O2和He结合的CF4和SF6。
所述蚀刻工艺继续第二蚀刻部分以通过由第一蚀刻部分限定的开口蚀刻衬底210。第二蚀刻部分可具有不同的选择比以在蚀刻期间最小化ILD250的损失。同时，随着栅极侧壁间隔件230减慢侧面蚀刻，第二蚀刻部分按自对准工艺实施并且槽外形与栅极侧壁间隔件230对准。
第二蚀刻部分可包括使用HBr/Cl2/O2/He的组合的不同的干法蚀刻工艺。所述干法蚀刻去除衬底210未受保护的部分或在隔离沟槽260内暴露的部分。因此，第二蚀刻部分通过定向蚀刻或各向异性蚀刻可形成与栅极侧壁间隔件230的边缘大体对准的沟槽轮廓。隔离沟槽260包括上部和下部。隔离沟槽260的上部在ILD层250内，隔离沟槽260的下部在半导体衬底210内。此后，通过诸如湿法剥膜或者O2等离子体灰化的工艺去除光刻胶层255。
如图5和图6所示，方法100进入步骤108：形成隔离部件275。隔离部件275通过用诸如氧化硅、氮化硅或氮氧化硅的电介质材料填充隔离沟槽260形成。隔离部件275可具有多层结构，例如用氮化硅或氧化硅填充的热氧化物衬里层。在进一步的实施方式中，隔离部件275可包括由ALD形成并通过CVD、PVD、热氧化或它们的组合用电介质膜填充的沟槽衬里。在所描述的实施方式中，如图5所示，隔离部件275包括通过ALD技术形成的氧化硅衬里(未示出)和通过CVD技术形成的氧化硅层270。隔离部件275嵌入半导体衬底210内并延伸至ILD250。隔离部件275包括作为其延伸部的栅极侧壁间隔件230。
通常实施CMP工艺来去除过剩的氧化硅层270和隔离部件275的上部的部分。所述CMP工艺可为栅极结构220、ILD250和隔离部件275的剩余部分提供大体平坦的表面。如图6所示，蚀刻工艺可去除伪栅极层221的剩余部分以形成栅极沟槽280。剩余的伪栅极层221可按常规方式通过干法蚀刻、湿法蚀刻或干法蚀刻和湿法蚀刻的组合去除。
方法100进入步骤110：根据替换栅极(RPG)工艺流程形成栅极结构。在RPG工艺流程中典型的栅极结构形成包括在栅极沟槽280上形成界面层(IL)、HK电介质层、盖层、功函数金属层、势垒层和电极金属层。可实施CMP工艺来去除额外的金属层。所述CMP工艺可具有金属层比电介质层250的高选择比。所述CMP工艺为金属栅极堆叠和ILD层250提供大体平坦的表面。
方法100可进一步包括形成多层互连件。所述多层互连件(未示出)可包括垂直互连件诸如常规通孔或触点和水平互连件诸如金属线。各种互连部件可实施为各种导电材料，包括铜、钨和硅化物。在一个实施例中，大马氏革制程(damascene process)被用于形成与铜相关的多层互连结构。在另一种实施方式中，邬用于形成在接触孔内的邬插塞。
参考图6，在所描述的实施方式中，方法100形成具有与栅极侧壁间隔件230自对准的轮廓的隔离部件275。它可为器件布局和工艺控制窗留下更多空余以用于构建的高栅极密度器件，诸如CMOS或鳍式场效晶体管(FinFET)。隔离部件275在外延生长区240形成之后形成。因而，方法100可称为后隔离方法。在这种后隔离方法中，每个外延生长区240都可在完全相似的外延生长环境下形成在所有相关位置。外延生长环境包括外延生长间隔尺寸、用于外延生长形成的材料类型，现有的与外延生长区240一同生长的相邻部件(例如，栅极侧壁间隔件230)。
一致的外延生长环境在外延生长区240的尺寸、形状、晶面和晶体取向方面增强所有相关位置内的外延生长区240的均匀性。在所有相关位置内的均匀的外延生长区240可增强在所有相关位置内的应变沟道的均匀性，这可增强在所有相关位置内的一致沟道性能诸如载流子迁移率。它还可为在所有相关位置形成将来的S/D接触提供相同的着陆(landing)条件，因此它可改善接触阻力(对硅化物)的均匀性和可靠性。本发明的另一种实施方式涉及在FinFET器件中应用后隔离方法来形成隔离部件。通过应用后隔离方法，OD(有源区)线末端可与栅极侧壁间隔件230大体自对准并且可为相关沟道提供均匀应变。所述外延生长工艺可具有完全相似的源-漏(SA)宽度，并在所有相关位置内产生均匀的外延生长区。也可优化器件布局和工艺窗口的空余。
上面概述了若干实施例的部件，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他工艺和结构以用于达到与这里所介绍实施例相同的目的和/或实现相同优点。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，所述半导体器件包括：
多个栅极结构，设置在半导体衬底上；
多个电介质材料的栅极侧壁间隔件，形成在所述多个栅极结构的各个侧壁上；
层间电介质(ILD)，设置在所述半导体衬底和所述栅极结构上；
隔离部件，嵌入所述半导体衬底内并延伸至所述ILD；以及
电介质材料的侧壁间隔件，设置在所述隔离部件的延伸部的侧壁上。
2.根据权利要求1所述的半导体器件，进一步包括靠近所述隔离部件和靠近所述栅极结构的外延生长区。
3.根据权利要求2所述的半导体器件，其中所述外延生长区彼此具有相同的形状。
4.根据权利要求2所述的半导体器件，其中所述外延生长区彼此具有相同的晶面。
5.根据权利要求2所述的半导体器件，其中所述外延生长区包括硅锗。
6.一种形成半导体器件的方法，该方法包括：
提供半导体衬底；
在所述半导体衬底中形成多个伪栅极结构；
在所述伪栅极结构的侧壁上形成侧壁间隔件；
在所述伪栅极结构之间形成多个外延生长区；
在形成所述多个外延生长区后，去除所述伪栅极结构中之一来形成隔离沟槽；
用电介质层填充所述隔离沟槽来形成隔离部件；
去除剩余的所述伪栅极结构来形成栅极沟槽；
在所述栅极沟槽内形成栅极结构。
7.根据权利要求6所述的方法，其中所述隔离沟槽的上部具有与所述伪栅极结构相似的轮廓。
8.根据权利要求6所述的方法，其中所述隔离沟槽蚀刻包括第一部分，所述第一部分为去除所述伪栅极部件并且暴露所述半导体衬底以形成所述隔离沟槽的上部。
9.根据权利要求8所述的方法，进一步包括蚀刻的第二部分，所述第二部分为蚀刻所述半导体衬底从而形成所述隔离部件的下部。
10.一种半导体器件，所述半导体器件包括：
硅衬底；
两个设置在所述衬底上的高k/金属栅极(HK/MG)部件；
形成在所述HK/MG部件的各个侧壁上的多个电介质材料的栅极间隔件；
形成在所述两个HK/MG部件之间的多个外延生长硅锗区，其中，所述外延生长区彼此具有相同的形状和相同的晶面；以及
设置在所述半导体衬底和所述HK/MG部件上的ILD；
嵌入所述半导体衬底并延伸至所述ILD的隔离部件；以及，
设置在所述隔离部件的延伸部的侧壁上的电介质材料的侧壁间隔件。
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US20140256107A1 (en) 2014-09-11
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