FR3036846B1 - Procede d'isolation locale entre des transistors realises sur un substrat soi, en particulier fdsoi, et circuit integre correspondant - Google Patents
Procede d'isolation locale entre des transistors realises sur un substrat soi, en particulier fdsoi, et circuit integre correspondant Download PDFInfo
- Publication number
- FR3036846B1 FR3036846B1 FR1554853A FR1554853A FR3036846B1 FR 3036846 B1 FR3036846 B1 FR 3036846B1 FR 1554853 A FR1554853 A FR 1554853A FR 1554853 A FR1554853 A FR 1554853A FR 3036846 B1 FR3036846 B1 FR 3036846B1
- Authority
- FR
- France
- Prior art keywords
- fdsoi
- integrated circuit
- soi substrate
- corresponding integrated
- transistors made
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000002955 isolation Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
- Element Separation (AREA)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1554853A FR3036846B1 (fr) | 2015-05-29 | 2015-05-29 | Procede d'isolation locale entre des transistors realises sur un substrat soi, en particulier fdsoi, et circuit integre correspondant |
CN201520976019.XU CN205542782U (zh) | 2015-05-29 | 2015-11-30 | 集成电路 |
CN201510860495.XA CN106206455B (zh) | 2015-05-29 | 2015-11-30 | 用于在soi衬底特别是fdsoi衬底上制造的晶体管之间局部隔离的方法以及对应的集成电路 |
US14/956,594 US9876076B2 (en) | 2015-05-29 | 2015-12-02 | Method for local isolation between transistors produced on an SOI substrate, in particular an FDSOI substrate, and corresponding integrated circuit |
DE102015121913.1A DE102015121913B4 (de) | 2015-05-29 | 2015-12-16 | Verfahren zur lokalen Isolierung zwischen Transistoren, die auf einem Substrat SOI, insbesondere FDSOI, verwirklicht sind, und entsprechende integrierte Schaltung |
US15/845,930 US10283588B2 (en) | 2015-05-29 | 2017-12-18 | Method for local isolation between transistors produced on an SOI substrate, in particular an FDSOI substrate, and corresponding integrated circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1554853A FR3036846B1 (fr) | 2015-05-29 | 2015-05-29 | Procede d'isolation locale entre des transistors realises sur un substrat soi, en particulier fdsoi, et circuit integre correspondant |
FR1554853 | 2015-05-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3036846A1 FR3036846A1 (fr) | 2016-12-02 |
FR3036846B1 true FR3036846B1 (fr) | 2018-06-15 |
Family
ID=54199786
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1554853A Expired - Fee Related FR3036846B1 (fr) | 2015-05-29 | 2015-05-29 | Procede d'isolation locale entre des transistors realises sur un substrat soi, en particulier fdsoi, et circuit integre correspondant |
Country Status (4)
Country | Link |
---|---|
US (2) | US9876076B2 (fr) |
CN (2) | CN205542782U (fr) |
DE (1) | DE102015121913B4 (fr) |
FR (1) | FR3036846B1 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3036846B1 (fr) * | 2015-05-29 | 2018-06-15 | Stmicroelectronics (Crolles 2) Sas | Procede d'isolation locale entre des transistors realises sur un substrat soi, en particulier fdsoi, et circuit integre correspondant |
JP6594261B2 (ja) * | 2016-05-24 | 2019-10-23 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20230260994A1 (en) * | 2022-02-17 | 2023-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Checkerboard dummy design for epitaxial open ratio |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6303962B1 (en) * | 1999-01-06 | 2001-10-16 | Advanced Micro Devices, Inc. | Dielectrically-isolated transistor with low-resistance metal source and drain formed using sacrificial source and drain structures |
JP4698793B2 (ja) * | 2000-04-03 | 2011-06-08 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US6713335B2 (en) | 2002-08-22 | 2004-03-30 | Chartered Semiconductor Manufacturing Ltd. | Method of self-aligning a damascene gate structure to isolation regions |
US7834662B2 (en) | 2006-12-13 | 2010-11-16 | Apple Inc. | Level shifter with embedded logic and low minimum voltage |
US9349655B2 (en) * | 2008-08-29 | 2016-05-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for mechanical stress enhancement in semiconductor devices |
JP2010251344A (ja) * | 2009-04-10 | 2010-11-04 | Hitachi Ltd | 半導体装置およびその製造方法 |
US8502316B2 (en) | 2010-02-11 | 2013-08-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned two-step STI formation through dummy poly removal |
US9263339B2 (en) * | 2010-05-20 | 2016-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective etching in the formation of epitaxy regions in MOS devices |
US8492210B2 (en) * | 2010-12-17 | 2013-07-23 | Institute of Microelectronics, Chinese Academy of Sciences | Transistor, semiconductor device comprising the transistor and method for manufacturing the same |
US8546208B2 (en) * | 2011-08-19 | 2013-10-01 | International Business Machines Corporation | Isolation region fabrication for replacement gate processing |
CN103050525B (zh) * | 2011-10-12 | 2015-06-17 | 中国科学院微电子研究所 | Mosfet及其制造方法 |
US8735991B2 (en) | 2011-12-01 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | High gate density devices and methods |
FR3036846B1 (fr) * | 2015-05-29 | 2018-06-15 | Stmicroelectronics (Crolles 2) Sas | Procede d'isolation locale entre des transistors realises sur un substrat soi, en particulier fdsoi, et circuit integre correspondant |
-
2015
- 2015-05-29 FR FR1554853A patent/FR3036846B1/fr not_active Expired - Fee Related
- 2015-11-30 CN CN201520976019.XU patent/CN205542782U/zh not_active Withdrawn - After Issue
- 2015-11-30 CN CN201510860495.XA patent/CN106206455B/zh active Active
- 2015-12-02 US US14/956,594 patent/US9876076B2/en active Active
- 2015-12-16 DE DE102015121913.1A patent/DE102015121913B4/de active Active
-
2017
- 2017-12-18 US US15/845,930 patent/US10283588B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
DE102015121913A1 (de) | 2016-12-01 |
US9876076B2 (en) | 2018-01-23 |
US20180108731A1 (en) | 2018-04-19 |
FR3036846A1 (fr) | 2016-12-02 |
DE102015121913B4 (de) | 2023-12-07 |
CN106206455B (zh) | 2020-11-13 |
CN205542782U (zh) | 2016-08-31 |
US20160351660A1 (en) | 2016-12-01 |
CN106206455A (zh) | 2016-12-07 |
US10283588B2 (en) | 2019-05-07 |
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