TWI527103B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI527103B
TWI527103B TW102126415A TW102126415A TWI527103B TW I527103 B TWI527103 B TW I527103B TW 102126415 A TW102126415 A TW 102126415A TW 102126415 A TW102126415 A TW 102126415A TW I527103 B TWI527103 B TW I527103B
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substrate
adjacent
gate structure
semiconductor device
forming
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TW102126415A
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TW201407675A (zh
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莊學理
吳欣樺
費中豪
朱鳴
楊寶如
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台灣積體電路製造股份有限公司
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    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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Description

半導體裝置及其製造方法
本發明係有關於一種半導體裝置及其製造方法。
半導體積體電路(integrated circuit,IC)工業經歷了快速的發展。在IC的發展過程中，IC的功能(functional)密度(例如，每一晶片面積中的裝置互連數)隨著幾何尺寸(例如，能以製程製作的最小元件/線路)的縮小而增加。一般來說，此微縮(scaling down)製程提供增加產能效率與降低成本等優勢。微縮製程也增加了加工與生產積體電路的複雜度，為了實現這些優勢，相關IC製造技術的發展是必需的。
舉例來說，半導體裝置，例如，金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field-effect transistors,MOSFESs)之尺寸縮小經歷了不同的技術世代(technology nodes)，利用了應變(strained)源/汲元件(例如，壓力源區域(stressor region))以增強載體遷移率(carrier mobility)並提升裝置的效能。雖然現有形成IC裝置之壓力源區域的方法足以滿足其預期的使用目的，然而，還未能完全滿足各方面的需求。
本發明提供一種半導體裝置的製造方法，包括： 形成一閘疊於一基板上，基板具有一表面；形成一非晶區域於基板中，且非晶區域相鄰於閘疊的一邊緣，其中非晶區域具有一深度D1；形成一應力膜於基板上；進行一製程以形成帶有一夾止點(pinchoff point)的一錯位(dislocation)於基板中，其中錯位形成一角度θ1，角度θ1係對應到垂直於基板之表面的參考水平而測得，且其中夾止點以一距離W與閘疊的邊緣隔開，且夾止點相對於基板之表面具有一深度D2；移除至少一部分的錯位，以形成帶有一尖端的一凹槽於基板中，其中凹槽相對於基板之表面具有一深度D3，且凹槽以一距離S與閘疊之邊緣隔開；以及形成一源/汲元件於凹槽內。
本發明又一種半導體裝置的製造方法，包括：形成一第一閘結構與一第二閘結構於一基板上；形成一第一非晶區域與一第二非晶區域於基板中，第一非晶區域相鄰於第一閘結構且第二非晶區域相鄰於第二閘結構；沉積一應力膜於第一與第二非晶區域上；進行一退火製程以在基板內形成一第一錯位與一第二錯位，第一錯位相鄰於第一閘結構且第二錯位相鄰於第二閘結構；移除第二錯位以形成相鄰於第二閘結構的一凹槽，而保留第一錯位相鄰於第一閘結構；形成一源/汲元件於凹槽中。
本發明亦一種半導體裝置，包括：一半導體基板，其具有一表面；一第一閘結構與一第二閘結構，於半導體基板之上；帶有一夾止點(pinchoff point)的一錯位(dislocation)，於半導體基板中且相鄰於第一閘結構之一邊緣，其中錯位形成一角度θ1，角度θ1係對應到垂直於基板之表面的參考水平而測 得，且其中夾止點以一距離W與閘疊的邊緣隔開並以一深度D2與基板之表面隔開；以及帶有一尖端的一源/汲元件，於半導體基板中，且源/汲元件相鄰於第二閘結構的一邊緣，其中尖端相對於基板之表面具有一深度D3，且尖端以一距離S與第二閘結構之邊緣隔開，且其中W>|D2-D3|×tan θ1+S。
200‧‧‧半導體裝置
202‧‧‧基板
204‧‧‧隔離元件
206‧‧‧閘介電層
208‧‧‧閘電極層
210‧‧‧硬遮罩層
212‧‧‧側壁間隔物
214‧‧‧預非晶佈植製程
216‧‧‧非晶化區域
218‧‧‧應力膜
218’‧‧‧間隔物
220‧‧‧退火製程
222‧‧‧錯位
224‧‧‧夾止點
226‧‧‧保護器
228‧‧‧凹槽
230‧‧‧源/汲元件
232‧‧‧蓋層
240‧‧‧NMOS閘疊
250‧‧‧PMOS閘疊
W、S‧‧‧距離
D1、D2、D3‧‧‧深度
θ 1‧‧‧角度
第1圖係根據本發明不同實施例繪示出半導體裝置的製造方法之流程圖。
第2~8圖係根據本發明一或多個實施例與第1圖中的方法繪示出半導體裝置在不同製造階段的剖面示意圖。
要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化發明的說明。當然，這些特定的範例並非用以限定本發明。例如，若是本說明書以下的揭露內容敘述了將一第一特徵形成於一第二特徵之上或上方，即表示其包含了所形成的上述第一特徵與上述第二特徵是直接接觸的實施例，亦包含了尚可將附加的特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與上述第二特徵可能未直接接觸的實施例。另外，本發明的說明中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。應被瞭解 的是，任何所屬技術領域中具有通常知識者將會瞭解本發明能夠在沒有這些特定細節情形下實行。
本發明一或多個實施例有利於具有場效電晶體的半導體裝置。例如，互補式金屬氧化物半導體(complementary metal-oxide-semiconductor,CMOS)場效電晶體。以下將會以此裝置做為範例以說明本發明之實施例。然而，應被瞭解的是，本發明並不侷限於特定種類的裝置，除非明確地作如此聲明。
請參照第1、2~8圖，以下將說明方法100與半導體裝置200。半導體裝置200係關於積體電路或其部份，積體電路可包括主動裝置，例如，金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field-effect transistors,MOSFESs)、互補式金屬氧化物半導體(complementary metal-oxide-semiconductor,CMOS)場效電晶體、高電壓電晶體、及/或上述之組合。半導體裝置200可額外地包括被動元件，例如電阻器、電容器、電感器(inductors)、及/或熔絲(fuse)。應被理解的是，可藉由CMOS加工技術形成半導體裝置200，因此，在此不再詳述。可在實施方法100之前、期間、或之後施加額外的步驟，且下述的一些步驟可以被取代或省略。更應被理解的是，一些額外的半導體裝置200之實施例中，可加入額外的元件至半導體裝置200中，且下述的一些元件可以被取代或省略。
請參照第1圖，第1圖根據本發明不同的形式繪示出半導體裝置之製造方法100。方法100由步驟102開始，其中在基板上形成NMOS閘疊(gate stack)與PMOS閘疊。方法 100持續進行到步驟104，在基板上實施預非晶佈植(pre-amorphous implantation,PAI)製程。方法100進行步驟106，在基板上沉積應力膜。方法100持續進行至步驟108，在基板上實施退火(annealing)製程。方法100進行至步驟110，在基板中形成凹槽(recess cavity)，且凹槽相鄰於PMOS閘疊。方法100持續進行到步驟112，在凹槽中形成源/汲元件。方法100進行至步驟114，在源/汲元件上形成一蓋(capping)層。以下將對可用第1圖中的方法100製得的半導體裝置200之不同實施例作說明。
第2~8圖係根據第1圖中的方法100繪示出半導體裝置200在不同製造階段的剖面示意圖。請參照第1圖與第2圖，方法100開始於步驟102，在基板202上形成NMOS閘疊240與PMOS閘疊250，且NMOS閘疊240與PMOS閘疊250各自在基板下方定義通道(channel)區域。在本實施例中，基板202為半導體基板，包括矽。在其他實施例中，基板202包括：元素(elementary)半導體，其包括矽、及/或鍺晶體；化合物(compound)半導體，其包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦；合金半導體，其包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP；或上述基板之組合。當基板202為合金半導體，合金半導體基板可具有梯度SiGe元件，其中SiGe元件的Si與Ge之比例隨著位置而改變。可在矽基板上形成SiGe合金，且/或SiGe基板為應變的(strained)。又一實施例中，半導體基板可為半導體覆絕緣體(semiconductor on insulator,SOI)。
廣為所知的，依照設計需求，基板202包括不同的摻雜區域(例如，p型井或n型井)。以p型掺質(例如，硼或BF2)及/或n型掺質(例如，磷或砷)摻雜摻雜區域。可直接在基板202上形成摻雜區域，摻雜區域可為p井結構、n井結構、雙井(dual-well)結構、或凸起(raised)結構。基板202可包括隔離(isolation)元件204，其定義且隔離基板202的不同的主動(active)區域。隔離元件204利用隔離技術(例如，淺溝隔離(shallow treach isolation,STI)、局部矽氧化(local oxidation of silicon,LOCOS))以定義與電性隔離不同的區域。隔離元件204包括氧化矽、氮化矽、氮氧化矽、其他合適材料、或上述之組合。
請參照第2圖，一些實施例中，藉由相繼沉積與圖案化基板202上的閘介電層206、閘電極層208及硬遮罩層210以形成NMOS閘疊240與PMOS閘疊250。在一個例子中，閘介電層206為薄膜，其包括氧化矽、氮化矽、氮氧化矽、高介電常數材料、其他合適介電材料、或上述之組合。高介電常數材料包括金屬氧化物。用於高介電材料的金屬氧化物之例子包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu、或上述之混合的氧化物。本實施例中，閘介電層206為高介電常數材料層，其厚度為約10埃~30埃。可使用合適的製程形成閘介電層206，例如，原子層沉積(atomic layer deposition,ALD)、化學氣相沉積(chemical vapor depositon,CVD)、物理氣相沉積(physical vapor depostion,PVD)、熱氧化(thermal oxidation)、紫外光臭氧氧化(UV-ozone oxidation)、或上述之組合。閘介電層206可更包括界面(interfacial)層(未顯示)，界面層可降低閘介電層206與基板之間的損壞。界面層包括氧化矽。接著，在閘介電層206上形成閘電極層208。一些實施例中，閘電極層208包括單層或多層結構。本發明實施例中，閘電極層208包括多晶矽(polysilicon)。再者，閘電極層208可為帶有相同或不同的摻雜種類的經摻雜的多晶矽。在一實施例中，閘電極層208之厚度為約30~60nm。可使用一製程形成閘電極層208，例如，低壓化學氣相沉積(low-pressure chemical vapor deposition,LPCVD)、電漿增強化學氣相沉積(plasma enhanced chemical vapor deposition,PECVD)、其他合適製程、或上述之組合。接著，在閘電極層208上形成硬遮罩層210與在硬遮罩層210上形成圖案感光(patterned photo-sensitive)層(未顯示)。將感光層之圖案轉移到硬遮罩層210，接著轉移到硬遮罩層210與閘介電層206以形成NMOS閘疊240與PMOS閘疊250。一些實施例中，硬遮罩層210包括氧化矽。在另一實施例中，硬遮罩層210包括氮化矽、氮氧化矽、及/或其他合適的介電材料，且可使用如CVD和PVD的方式形成硬遮罩層210。硬遮罩層210之厚度為約100~800埃。之後，藉由濕及/或乾去除(stripping)製程移除感光層。
請進一步參考第2圖，形成側壁間隔物(spacer)(或稱為閘間隔物)212，其鄰接NMOS閘疊240與PMOS閘疊250的相反的(opposite)側壁。一些實施例中，側壁間隔物212包括單層或多層結構。本實施例中，藉由沉積製程在NMOS閘疊 240、PMOS閘疊250、及基板202上形成間隔材料(未顯示)的毯覆(blanket)層，沉積製程包括CVD、PVD、ALD、或其他合適製程。一些實施例中，間隔材料包括氧化矽、氮化矽、氮氧化矽、其他合適材料、或上述之組合。一些實施例中，間隔材料的沉積層之厚度為約10~60埃。接著，在間隔材料上施加異向蝕刻製程以形成側壁間隔物212。側壁間隔物212能保護NMOS閘疊240與PMOS閘疊250之側壁。此外，可用側壁間隔物212偏移後續形成的摻雜區域，例如重摻雜的源/汲區域。
請參照第1圖與第3圖，方法100進行至步驟104，在基板202上實施預非晶佈植製程214。一些實施例中，預非晶佈植製程214植入基板202且對基板202之晶格(lattice)結構造成損傷，以形成非晶化(amorphized)區域216。本實施例中，非晶化區域216形成於半導體裝置200的源/汲區域中。非晶化區域216具有深度D1(從基板202之上表面測量)。深度D1係根據設計規格而形成的。一些實施例中，深度D1為約10~150nm。本實施例中，深度D1小於約100nm。因為側壁間隔物212用來集中PAI製程214的佈植能量，因此可藉由側壁間隔物212之厚度控制深度D1。同樣地，亦可藉由PAI製程214控制深度D1，例如，植入能量、植入種類、及/或植入劑量。在至少一實施例中，PAI製程214以矽或鍺植入基板202。在另一實施例中，PAI製程214能使用其他植入種類，例如，Ar、Xe、C、BF2、As、In、其他合適的植入種類、或上述之組合。本實施例中，視佈植溫度而定，PAI製程214以約15~50KeV的植入能量及約1×1014~2×1015atoms/cm2的植入 劑量植入Si或Ge。至少一實施例中，PAI製程214是在室溫(例如，25℃)下進行。在另一實施例中，PAI製程214是藉由轉換離子佈植機(implanter)的低溫(Cryo)功能在低溫(例如，-60℃~-100℃)下進行，以加強非晶佈植的效率。一些實施例中，以傾斜角度(約0~20度)進行PAI製程214。
在另一些實施例中，PAI製程214可為多階段(multiple-step)佈植製程，其包括佈植製程的第一階段與第二階段至少其一。分別使用第一與第二植入能階、第一與第二植入劑量、及第一與第二植入傾斜角度進行佈植製程的第一與第二階段。至少一實施例中，第一與第二植入能階為約15~50KeV。另一實施例中，第一植入能階大於第二植入能階。在至少一實施例中，第一與第二植入劑量為約1×1014~2×1015atoms/cm2。另一實施例中，第一植入劑量大於第二植入劑量。在一些實施例中，第一與第二植入劑量的組合為約1×1014~2×1015atoms/cm2，且第一與第二植入劑量的比例為約1：1~7：3。在一實施例中，第一與第二傾斜角度為約0~20度。另一實施例中，第一植入傾斜角度大於第二植入傾斜角度。
一些實施例中，非晶(amorphized)區域216以鄰接NMOS閘疊240與PMOS閘疊250之相反邊緣的方式形成，使用PAI製程形成非晶區域216的期間未使用任何圖案化光阻層或硬遮罩層。因此，可省去形成圖案化光阻層或圖案化硬遮罩層的圖案化製程，從而降低成本。
請參照第1圖與第4圖，方法100進行至步驟106，在NMOS閘疊240、PMOS閘疊250、及基板202上沉積 應力膜(stress film)218。可藉由，化學氣相沉積(chemical vapor depositon,CVD)、物理氣相沉積(physical vapor depostion,PVD)、原子層沉積(atomic layer deposition,ALD)、高密度電漿CVD(high density plasma CVD,HDPCVD)、電鍍、其他合適方法、及/或上述之組合形成應力膜218。應力膜218包括介電材料。一些實施例中，應力膜包括氮化矽、氮氧化矽、SiCN、及/或上述之組合。另一實施例中，應力膜包括氧化矽。一些實施例中，應力膜218之厚度大於形成側壁間隔物212的間隔材料之厚度。在一些實施例中，應力膜218之厚度為約100~300埃。一些實施例中，使用應力膜218以提供拉伸(tensile)應力給隨後將非晶區域216再結晶(recrystallize)的退火(annealing)製程。
請參照第1圖與第5圖，方法100進行至步驟108，在基板202上實施退火製程220。一些實施例中，退火製程220為快速熱退火(rapid thermal annealing,RTA)製程、尖波(spike)熱退火製程、或毫秒(millisecond)熱退火製程(例如，毫秒雷射熱退火製程)。在至少一實施例中，退火製程220包括以400~750℃，例如600~750℃的溫度持續約10秒~5分鐘進行RTA製程。在另一實施例中，退火製程220包括以990~1050℃的溫度持續約0.1~2秒進行尖波RTA製程。又一實施例中，退火製程220可更包括預熱步驟以最小化(或甚至消除)佈植終點(End of Range,EOR)的缺陷。一些實施例中，可進行預熱步驟約10秒~5分鐘。本實施例中，在約500℃下持續進行預熱步驟約30秒。
在進行退火製程220期間，當非晶區域216變成再結晶的(re-crystallized)，非晶區域216的再結晶對應體(counterpart)之錯位(dislocation)222形成於基板202中。一些實施例中，錯位222以鄰接NMOS閘疊240與PMOS閘疊250的邊緣的方式形成。一些實施例中，基板202被稱為(100)基板，而錯位222延著<111>方向形成。一些實施例中，<111>方向具有角度θ 1，角度θ 1係以垂直於基板202之表面的參考水平測得，其值為約25~45度。本實施例中，錯位222沿著<111>方向的角度θ 1之值為約35度。錯位222從夾止(pinchoff)點224開始形成。夾止點224具有深度D2，深度D2係從基板202之上表面測量。一些實施例中，夾止點224之深度D2為約10~150nm。本實施例中，夾止點224之深度D2為約10~30nm。夾止點224具有從NMOS閘疊240或PMOS閘疊250之相鄰閘邊緣測得的水平緩衝W(接近點(proximity))。水平緩衝W與深度D2係根據設計規格而形成，且水平緩衝W與深度D2為退火製程220之函數。一些實施例中，夾止點224的水平緩衝W為約-5~10nm(“-”代表夾止點224位於NMOS閘疊240或PMOS閘疊250下方)。可使夾止點224不形成於NMOS閘疊240或PMOS閘疊250定義在基板220中之通道(channel)區域內。
請參照第1圖與第6圖，方法100進行至步驟110，在基板202中形成凹槽(recess cavities)228。一些實施例中，凹槽228相鄰於PMOS閘疊250的相反邊緣。另一些實施例中，凹槽228為PMOS閘疊250的源/汲凹槽。本實施例中， 形成凹槽228的製程包括多道蝕刻製程，以使用等向性(isotropic)乾蝕刻製程開始，接著使用異相性乾或濕蝕刻製程。一些實施例中，提供一保護器(protector)226以覆蓋NMOS閘疊240，從而防止相鄰於NMOS閘疊240的基板202被蝕刻製程移除。舉例來說，保護器226為光阻圖案。
一些實施例中，實施等向性乾蝕刻製程以移除應力膜218覆在基板202上且相鄰於PMOS閘疊250的部分，從而暴露出在下方的基板202。接著，凹化暴露出的基板202以形成初始凹槽(未顯示)，初始凹槽相鄰於PMOS閘疊250的邊緣。一實施例中，可以約1~1000mTorr的壓力、約50~1000W的功率、約20~500V的偏壓(bias voltage)、及40~60℃的溫度，並以HBr及/或Cl2作為蝕刻氣體進行等向性乾蝕刻製程。在實施例中，可調整等向性乾蝕刻製程的偏壓以容許較佳的蝕刻方向之控製，進而達到源/汲凹部區域的理想輪廓。一些實施例中，移去鄰接PMOS閘疊250之側壁間隔物212外表面的部份應力膜218以形成間隔物218’。間隔物218’在隨後的磊晶成長(epitaxy growth)製程中，可作為保護器的功能提供給PMOS閘疊250的側壁。
一些實施例中，接著提供濕蝕刻製程以擴大初始凹槽，進而形成凹槽228。一些實施例中，以包括四甲基氫氧化銨(hydration tetramethyl ammonium,TMAH)等的化學藥品進行濕蝕刻製程。一些實施例中，凹槽228為楔形且帶有尖端朝著PMOS閘疊250的通道區域伸入基板202中。PMOS閘疊250的側壁與相鄰的尖端之間的間距S被視為尖端的接近點 (proximity)。深度D3係垂直地從基板202之表面到尖端測量而得。依照設計規格，錯位222的角度θ 1、水平緩衝W、夾止點224的深度D2、尖端之接近點的間距S、及尖端的深度D3之間的相互關係是需要的。一些實施例中，滿足上述相互關係以確保相鄰於PMOS閘疊250的錯位222完全被移除。一些實施例中，相互關係滿足下列方程式，W>|D2-D3|×tanθ1+S。在此之後，例如，藉由濕去除(stripping)製程及/或O2電漿製程移除保護器226。
請參照第1圖與第7圖，方法100持續進行制步驟112，在基板202之凹槽228中形成源/汲元件230。在一些實施例中，源/汲元件230之上表面高於基板之上表面。一些實施例中，源/汲元件230之上表面高於基板之上表面，且高度差為約1~10nm。在另一實施例中，源/汲元件230之上表面與基板之上表面本質上為共平面(co-planar)。在一些實施例中，源/汲元件230包括使用製程在凹槽228中成長的應變材料，製程包括選擇性磊晶成長(selective epitaxy growth,SEG)、環狀沉積與蝕刻(cyclic deposition and etching,CDE)、化學氣相沉積(chemical vapor deposition,CVD)技術(例如，氣相磊晶(vapor-phase epitaxy,VPE)及/或超高真空化學氣相沈積(ultra-high vacuum CVD,UJV-CVD))、分子束磊晶(molecular bean epitaxy,MBE)、其他合適磊晶製程、或上述之組合。一些實施例中，應變材料具有不同於基板202的晶格常數，以在半導體裝置200之通道區域上誘導應變或應力，因而導致裝置的載子遷移率(carrier mobility)以增強裝置的效能。
在本實施例中，使用化學藥品進行預清洗(pre-cleaning)製程以清洗凹槽228，化學藥品包括氫氟酸(hydrofluric acid,HF)、或其他合適的溶液。接著，可提供氣態或液態前驅物(例如，鍺化矽(SiGe))，使其與基板202之組成物相互作用(interact)以形成應變材料，進而填入凹槽228。在一實施例中，應變材料的形成包括在600~750℃的溫度與10~80Torr的壓力下，使用包括SiH2Cl2、HCl、GeH4、B2H6、H2、或上述之組合的反應氣體進行SiGe的反應。一些實施例中，SiH2Cl2的質量流率與HCl的質量流率比為約0.45~0.55。
在一些實施例中，成長於凹槽228且不相鄰於隔離結構204的應變材料大部分平行於基板202之頂表面的晶面。本實施例中，成長於凹槽228且不相鄰於隔離結構204的應變材料具有由(100)晶面形成的上表面。在本實施例中，因為由氧化矽形成的隔離結構204無法提供成核位置(nucleation site)以形成磊晶材料，隔離結構204限制了成長於凹槽228且相鄰於隔離結構204的應變材料。
一些實施例中，成長於凹槽228且相鄰於隔離結構204的應變材料傾向於具有不完全平行於基板202之頂表面的晶面的上表面。在一些實施例中，成長於凹槽228內且相鄰於隔離結構204的應變材料傾向於具有由(100)晶面與穩定的表面能(surface energy)所形成的上表面。
請參照第1圖與第8圖，方法100進行至步驟114，在源/汲元件230上形成蓋(capping)層232。蓋層232可作為保護層，其有防止下方應變材料被隨後的蝕刻製程過度蝕 刻的功能。本實施例中，蓋層232是由磊晶成長製程所形成。一些實施例中，蓋層232之厚度為約1~5nm。在凹槽228中的應變材料之上的蓋層232可沿著應變材料上表面的晶向(crystal orientation)成長。一些實施例中，在不相鄰於隔離結構204的應變材料之上成長的蓋層232傾向於具有由(100)晶面所形成的上表面。一些實施例中，凹槽228中且相鄰於隔離結構204的應變材料之上成長的蓋層232傾向於具有由(111)晶面所形成的上表面。
在此之後，一些實施例中，移除在NMOS閘疊240上殘留的應力膜218(即未移除的部份)及鄰接PMOS閘疊250之側壁間隔物212外表面的間隔物218’。舉例來說，藉由濕蝕刻(使用磷酸或氫氟酸)或乾蝕刻(使用合適的蝕刻劑)移除殘留的應力膜218與間隔物218’。
根據實施例，NMOS閘疊的錯位與PMOS閘疊的應變材料之好處為，在主動區域(例如，源/汲)內形成的錯位與應變材料可分別改善NMOS閘疊與PMOS閘疊之通道區域內的應力。再者，根據實施例，形成NMOS閘疊之錯位與PMOS閘疊之應變材料的製程能簡化形成製程，因為不需要額外的光阻層或硬遮罩因而能將成本降至最低。如此一來，本發明能在不增加大量的成本的形況下提高通道區域內的應力值以改善載體遷移率(carrier mobility)。應被理解的是，不同的實施例具有不同的優勢，而任何實施例不需具備特定的優勢。
半導體裝置可更進一步接受CMOS或MOS加工以形成各種元件。例如，方法100可持續進行以形成主要隔離件。 也可形成接觸元件，例如金屬矽化物(silicide)區域。接觸元件包括金屬矽化物材料(例如，矽化鎳(NiSi)、鉑矽化鎳(NiPtSi)、鉑鍺矽化鎳(NiPtGeSi)、鍺矽化鎳(NiGeSi)、矽化鐿(YbSi)、矽化鉑(PtSi)、矽化銥(IrSi)、矽化鉺(ErSi)、矽化鈷(CoSi)、其他合適導電材料、或上述之組合。接觸元件可由製程形成，包括沉積金屬層、將金屬層退火，使其能夠與矽反應而形成金屬矽化物、以及移除未反應的金屬層。可在基板上更進一步形成層間介電層(inter-level dielectric,ILD)且更進一步施加化學機械研磨(chemical mechanical polishing,CMP)製程於基板以將基板平坦化。另外，可在形成層間介電層之前，在閘結構之上形成接觸蝕刻停止層(contact etch stop layer,CESL)。
一實施例中，NMOS閘疊240與PMOS閘疊250係由最終裝置剩餘的多晶矽(polysilicon)(例如，多晶矽208)所組成。在另一實施例中，實施閘取代(gate replacement)製程(或閘後製(gate last)製程)，以金屬取代多晶矽NMOS閘疊240與PMOS閘疊250。舉例來說，金屬閘可取代NMOS閘疊240與PMOS閘疊250的閘疊(例如，多晶矽閘疊)。金屬閘包括襯(liner)層、功函數(work function)層、導電層、金屬閘層、填充層、其他合適的層、及/或上述之組合。各個層包括任何合適的材料，例如，鋁、銅、鎢、鈦、鉭、鋁氮化鉭(tantalum aluminum nitride)、氮化鈦、氮化鉭、矽化鎳、矽化鈷、銀、TaC、TaSiN、TaCN、TiAl、TiAlN、WN、金屬合金、其他合適材料、或上述之組合。
隨後的製程可在基板上進一步形成不同的接觸點 /導孔/導線及多層內連線元件(例如，金屬層和層間介電層)，上述元件被配置以連接半導體裝置的各種元件或基板。額外的元件可提供電性內連線給裝置。舉例來說，多層內連線包括垂直內連線(例如，傳統的導孔或接觸窗)及水平內連線(例如，金屬線)。不同的內連線結構可利用不同的導電材料，包括銅、鎢、及/或金屬矽化物(silicide)。在一範例中，使用鑲嵌(damascene)製程及/或雙鑲嵌製程形成銅相關(copper related)多層內連線結構。
所揭示的半導體裝置可用於不同的應用中，例如數位電路、影像感測裝置、異(hetero)半導體裝置、動態隨機存取記憶(dynamic random access memory,DRAM)單元、單電子電晶體(single electron transistor,SET)、及/或其他微電子裝置(在此全部稱為微電子裝置)。當然，本發明亦可應用於及/或易合適於其他種類的電晶體，包括單閘電晶體、雙閘電晶體、及其他多閘(multiple-gate)電晶體，且可用於許多不同應用中，包括感測單元、記憶單元、邏輯單元等。
上述說明提供許多不同的實施例或範例，用以實施本發明不同的特徵。以上所述的部件及排置的特定範例係用以簡化本說明。當然，此僅僅作為範例說明而並未用以限定本發明。因此，此處所述的部件可在不脫離本發明之精神和範圍內以不同於此處實施例的方式進行排列、組合或裝配。
以上概略說明了本發明數個實施例的特徵，使所屬技術領域中具有通常知識者對於後續本發明的詳細說明可更為容易理解。任何所屬技術領域中具有通常知識者應瞭解到 本說明書可輕易作為其它結構或製程的變更或設計基礎，以進行相同於本發明實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構或製程並未脫離本發明之精神和保護範圍內，且可在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。
200‧‧‧半導體裝置
202‧‧‧基板
204‧‧‧隔離元件
206‧‧‧閘介電層
208‧‧‧閘電極層
210‧‧‧硬遮罩層
212‧‧‧側壁間隔物
218‧‧‧應力膜
218’‧‧‧間隔物
222‧‧‧錯位
224‧‧‧夾止點
230‧‧‧源/汲元件
232‧‧‧蓋層
240‧‧‧NMOS閘疊
250‧‧‧PMOS閘疊

Claims (11)

  1. 一種半導體裝置的製造方法，包括：形成一閘疊於一基板上，該基板具有一表面；形成一非晶區域於該基板中，且該非晶區域相鄰於該閘疊的一邊緣，其中該非晶區域具有一深度D1；形成一應力膜於該基板上；進行一製程以形成帶有一夾止點(pinchoff point)的一錯位(dislocation)於該基板中，其中該錯位形成一角度θ 1，該角度θ 1係對應到垂直於基板之表面的參考水平而測得，且其中該夾止點以一距離W與該閘疊的該邊緣隔開，且該夾止點相對於該基板之該表面具有一深度D2；移除至少一部分的該錯位，以形成帶有一尖端的一凹槽於該基板中，其中該尖端相對於該基板之該表面具有一深度D3，且該尖端以一距離S與該閘疊之該邊緣隔開；以及形成一源/汲元件於該凹槽內。
  2. 如申請專利範圍第1項所述之半導體裝置的製造方法，更包括：在移除該部份的該錯位之前，移除至少一部分的該應力膜，以形成鄰接於該閘疊之側壁的多個間隔物。
  3. 如申請專利範圍第1項所述之半導體裝置的製造方法，更包括：在形成該應力膜之前，形成鄰接於該閘疊之側壁的多個側壁間隔物。
  4. 如申請專利範圍第1項所述之半導體裝置的製造方法，其 中該深度D1為約10~150nm。
  5. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該些深度D2、D3、該些距離W、S、與該角度θ1的相互關係滿足下列方程式，W>|D2-D3|×tanθ1+S。
  6. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該非晶區域係由進行一佈植(implantation)製程以植入矽、或鍺於該基板。
  7. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中形成該錯位的該製程為一退火製程，其係在400~750℃下進行一快速熱退火(rapid thermal annealing,RTA)製程10秒~5分鐘。
  8. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中形成該錯位的該製程為一退火製程，其係在990~1050℃下進行一尖波熱退火(spike thermal annealing,RTA)製程0.1~2秒。
  9. 一種半導體裝置的製造方法，包括：形成一第一閘結構與一第二閘結構於一基板上；形成一第一非晶區域與一第二非晶區域於該基板中，該第一非晶區域相鄰於該第一閘結構且該第二非晶區域相鄰於該第二閘結構；沉積一應力膜於該第一與第二非晶區域上；進行一退火製程以在該基板內形成一第一錯位與一第二錯位，該第一錯位相鄰於該第一閘結構且該第二錯位相鄰於該第二閘結構； 移除該第二錯位以形成相鄰於該第二閘結構的一凹槽，而保留該第一錯位相鄰於該第一閘結構；以及形成一源/汲元件於該凹槽中。
  10. 如申請專利範圍第9項所述之半導體裝置的製造方法，更包括：在移除該第二錯位之前，移除相鄰於該第二閘結構且位於該基板上的一部分該應力膜，而保留另一部分的該應力膜以形成鄰接該第二閘結構之側壁的間隔物，其中位於該基板上且相鄰於該第二閘結構的該部分的應力膜的移除步驟並未將相鄰於該第一閘結構的該部分的該應力膜移除。
  11. 一種半導體裝置，包括：一半導體基板，其具有一表面；一第一閘結構與一第二閘結構，於該半導體基板之上；帶有一夾止點(pinchoff point)的一錯位(dislocation)，於該半導體基板中且相鄰於該第一閘結構之一邊緣，其中該錯位形成一角度θ 1，該角度θ 1係對應到垂直於基板之表面的參考水平而測得，且其中該夾止點以一距離W與該第一閘結構的該邊緣隔開並以一深度D2與該基板之該表面隔開；以及帶有一尖端的一源/汲元件，於該半導體基板中，且該源/汲元件相鄰於該第二閘結構的一邊緣，其中該尖端相對於該基板之該表面具有一深度D3，且該尖端以一距離S與該第二閘結構之該邊緣隔開，且其中W>|D2-D3|×tanθ1+S。
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