US20060084235A1 - Low rc product transistors in soi semiconductor process - Google Patents
Low rc product transistors in soi semiconductor process Download PDFInfo
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- US20060084235A1 US20060084235A1 US10/965,964 US96596404A US2006084235A1 US 20060084235 A1 US20060084235 A1 US 20060084235A1 US 96596404 A US96596404 A US 96596404A US 2006084235 A1 US2006084235 A1 US 2006084235A1
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- 238000000034 method Methods 0.000 title claims abstract description 59
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- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 28
- 239000001301 oxygen Substances 0.000 claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 24
- 239000010703 silicon Substances 0.000 claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 125000006850 spacer group Chemical group 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 7
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims 1
- 235000002020 sage Nutrition 0.000 claims 1
- 230000008901 benefit Effects 0.000 description 6
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- 238000005859 coupling reaction Methods 0.000 description 6
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- 238000010405 reoxidation reaction Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
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- 239000012535 impurity Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
Abstract
Description
- The present invention is in the field of semiconductor fabrication processes and more particularly semiconductor fabrication processes employing silicon-on-insulator (SOI) technology.
- Historically, transistors in conventional CMOS semiconductor fabrication processes were fabricated as “bulk” transistors, meaning that the source/drain regions and the active channel region were formed in an upper portion of the semiconductor bulk substrate. Bulk transistors suffer from large junction capacitance, which slows devices. SOI technology was developed, at least in part, to address this problem. In an SOI process, the starting material includes a thin semiconductor top layer overlying a buried dielectric layer, sometimes referred to herein as a buried oxide (BOX) layer overlying a semiconductor substrate or bulk. The active devices such as transistors are formed in the thin top layer.
- SOI processes improved the junction capacitance problem, but encountered other undesirable effects as the top layer becomes thinner. Specifically, conventional SOI transistors exhibited increased resistance, sometimes denoted as a transistor's external resistance (Rext) due to very thin source/drain regions. Elevated source/drain regions were then proposed and developed to reduce Rext, but the elevated source/drain structure introduced increased capacitive coupling between the source/drain regions and the transistor gate. It would be desirable to implement a SOI technology that includes transistors having low junction capacitance, low external resistance, and low capacitive coupling between source/drain and gate.
- The present invention is illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which:
-
FIG. 1 is a partial cross sectional view of an SOI wafer; -
FIG. 2 illustrates subsequent processing of the wafer ofFIG. 1 in which a transistor gate structure is formed overlying an active region of the wafer; -
FIG. 3 illustrates processing subsequent toFIG. 2 in which portions of the wafer top layer are removed; -
FIG. 4 illustrates processing subsequent toFIG. 3 in which source/drain trenches are formed in the buried oxide layer; -
FIG. 5 illustrates processing subsequent toFIG. 4 in which exposed portions of the transistor channel are insulated; -
FIG. 6 illustrates processing subsequent toFIG. 5 in which a first epitaxial growth is performed to grow an epitaxial structure in the source/drain trenches; -
FIG. 7 illustrates processing subsequent toFIG. 6 in which an anneal is performed to isolate the first epitaxial structure from the wafer substrate; -
FIG. 8 illustrates processing subsequent toFIG. 7 in which oxide is removed to expose the first epitaxial structure and the active channel region; -
FIG. 9 illustrates processing subsequent toFIG. 8 in which a second epitaxial process is performed to form the transistor source/drain regions; -
FIG. 10 illustrates alternative processing subsequent toFIG. 3 in which vertical sidewall source/drain trenches are formed in the buried oxide layer; -
FIG. 11 illustrates alternative processing subsequent toFIG. 10 in which the active channel is protected by depositing an oxide spacer; -
FIG. 12 illustrates alternative processing subsequent toFIG. 11 in which a first epitaxial structure is formed in the source/drain trenches; -
FIG. 13 illustrates alternative processing subsequent toFIG. 12 in which the protective oxide spacer is removed and a second epitaxial structure is formed to create the transistor source/drain regions. - Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
- Generally speaking, the present invention is concerned with forming transistors in SOI wafer technologies in a manner that reduces junction capacitance and short channel effects while minimizing increases in external resistance and parasitic capacitive coupling. The invention includes the use of source/drain regions that are recessed within the BOX layer to minimize capacitance between source/drain and gate. These regions will be referred to as recessed source/drain regions for simplicity although they may include the extension regions as well. The recessed source/drain regions may include tapered sidewalls to reduce junction capacitance. The source/drain regions are formed epitaxially using the wafer substrate as the epitaxial seed or template. One sequence may include a two-stage or two-step epitaxial process in which an oxygen rich epitaxial layer is formed at the base of the recessed source/drain region (i.e., overlying the substrate) followed by the formation of a “normal” or substantially oxygen-free epitaxial layer. The oxygen in the oxygen rich epitaxial layer facilitates the formation of an oxide between the substrate and the recessed source/drain thereby isolating the source/drain from the substrate.
- Turning now to the drawings,
FIGS. 1 through 9 illustrate selected stages in a first embodiment of a wafer processing sequence according to the present invention. InFIG. 1 , awafer 101 suitable for use with the present invention is depicted. As depicted inFIG. 1 ,wafer 101 is an SOI wafer having a semiconductor top layer oractive layer 106 overlying a buried oxide (BOX)layer 104 overlying a semiconductor bulk orsubstrate 102.Active layer 106 andsubstrate 102 are likely to be single crystal silicon or silicon germanium whileBOX layer 104 is likely to be a silicon oxide compound such as thermally formed silicon dioxide. - Turning now to
FIG. 2 , atransistor gate structure 110 has been formed overlyingactive layer 106 ofwafer 101. In the depicted implementation,gate structure 110 includes a gatedielectric layer 112, agate electrode 114,dielectric sidewalls 116, and adielectric capping layer 117. Gate dielectric 112, in one embodiment, is a thermally formed silicon dioxide. In other embodiments, gate dielectric 112 is a high-K dielectric (a dielectric material having a dielectric constant in excess of approximately 4.0) most likely comprised of a metal-oxide compound such as HfO2.Gate electrode 114 is a conductive structure preferably comprised of doped polysilicon, a metal or metal alloy (e.g., TaSi, Ti, TiW, etc.), or a combination thereof.Dielectric spacers 116 andcapping layer 117 are preferably comprised of silicon nitride or another dielectric that has good etch selectivity characteristics relative to silicon. - Referring now to
FIG. 3 , exposed portions ofactive layer 106 are removed (e.g., etched) thereby resulting in the formation of a transistor channel structure 107 (comprised of the portion ofactive layer 106 that is not removed). Beneficially,channel structure 107 formed in this manner is self-aligned togate structure 110. Thesidewalls 116 andcapping layer 117 surroundinggate electrode 114 protectelectrode 114 during the removal ofactive layer 106. The removal of the exposed portions ofactive layer 106 exposes the underlying portions ofBOX layer 104. In an embodiment in whichactive layer 106 is epitaxial silicon (doped or undoped), the removal step may include a dry etch process using, for example, SF6 and Cl2 to achieve adequate selectively with respect to cappinglayer 117 as well as theunderlying BOX layer 104. In one embodiment, the removal of exposed portions ofactive layer 106 is integrated into the gate etch step (i.e., the etch process that defines gate electrode 114). In this embodiment, the gate etch is maintained until the exposed portions ofactive layer 106 are removed thereby saving an etch step. - Referring now to
FIG. 4 , source/drain trenches 120 are formed inBOX layer 104. A patternedphotoresist layer 118 is first formed overlyingbox layer 104 using conventional photolithography and photoresist techniques. In the depicted embodiment, patternedphotoresist layer 118 defines a boundary oredge 124 of each source/drain trench 120 that is distal fromchannel structure 107 while a boundary oredge 125 of eachtrench 120 proximal tochannel structure 107 is defined by and self-aligned togate structure 110. Thus, source/drain trenches 120, likechannel structure 107, are self-aligned togate structure 110. - In one embodiment the
trenches 120 are at a 90 degree angle with the respect to thesubstrate surface 102. In the embodiment depicted inFIG. 4 , the etch of source/drain trenches 120 is controlled to produce slopedsidewalls 122. In this embodiment,sloped sidewalls 122 preferably exhibit an angle between 40 to 80 degrees an upper surface ofsubstrate 102. When the source/drain structure that ultimately occupies source/drain trenches 120 conforms to slopedsidewalls 122, capacitive coupling to the underlying substrate is reduced due to the reduced area of the source/drain structure at the interface withsubstrate 102. Moreover, thesloped sidewall 122 beneficially produces reduces source to drain coupling. - Referring now to
FIG. 5 , following formation of the source/drain trenches 120, an oxide forming process is performed to isolate thechannel region 107 from a subsequent epitaxial process. In one embodiment, the isolation ofchannel structure 107 is achieved by performing a thermal oxidation or reoxidation step to produceprotective oxide structures 126 at the exposed edges ofchannel structure 107. The reoxidation step is preferably followed by a short plasma etch to remove oxide formed on the upper surface of the exposed portions ofsubstrate 102 during the reoxidation thereby exposing the upper surface ofsubstrate 102. - Referring now to
FIG. 6 , the process of constructing recessed source/drain structures 130 is initiated. Using the exposed portions ofsubstrate 102 as a seed, an epitaxial growth or deposition process is performed to grow or deposit afirst epitaxial layer 132. Firstepitaxial layer 132 is preferably doped or undoped silicon or silicon germanium. In the depicted embodiment,first epitaxial layer 132 only partially fills the source/drain trench 120 and thereby leaves room within source/drain 120 for formation of a second epitaxial layer. The formation of distinct first and second epitaxial layers in this embodiment, beneficially facilitates a process sequence in whichfirst epitaxial layer 132 is electrically isolated fromsubstrate 102 following the first epitaxial process. More specifically, one implementation of the invention includes depositing or growing firstepitaxial layer 132 as an oxygen rich epitaxial layer (e.g., an epitaxial layer having an oxygen content not in excess of approximately 5%). - Referring to
FIG. 7 ,wafer 101 is annealed in an oxygen bearing ambient. The anneal of an oxygen rich first epitaxial layers causes the formation of anoxide layer 136 betweenepitaxial layer 132 andsubstrate 102 and adielectric layer 133 overlyingepitaxial layer 132. The presence ofoxide layer 136 betweenepitaxial layer 132 andsubstrate 102 provides excellent electrical isolation between the two and further reduces the junction capacitance by increasing the effective distance betweenepitaxial layer 132 andsubstrate 102. - Referring now to
FIG. 8 , an oxide removal process such as an HF dip is performed to remove theoxide layer 133 overlyingepitaxial layer 132 and to removeprotective oxide structures 126 thereby exposing the exterior edges ofchannel region 107. The oxide removal process is preferably a relatively short process, being just sufficient to removeoxide layer 133 andprotective oxide structures 126, to minimize the amount ofBOX layer 104 removed. In addition, the strip process is preferably selective tosidewall spacers 116 to protect the integrity ofgate dielectric 112. In the preferred implementation,sidewalls spacers 116 are thicker thanprotective oxide structures 126 thereby ensuring protection against unintended etching ofgate dielectric 112. - Referring now to
FIG. 9 , formation of recessed source/drain structures 130 is completed by forming asecond epitaxial layer 134 overlyingfirst epitaxial layer 132. Recessed source/drain structures 130 are so named because one may think of these regions as comprised of conventional elevated source/drain structures that are then “recessed” into theBOX layer 104. As such, recessed source/drain structures 130 exhibit the electrical resistivity characteristics of conventional elevated source/drain structures without exhibiting the parasitic capacitance characteristic of elevated source/drain transistors. Because the upper surface of recessed source/drain structures 130 is approximately coincident or planar with the upper surface ofchannel region 107, overlap and the resulting capacitive coupling between source/drainsstructures 130 andgate electrode 114 is beneficially minimized. In an embodiment wherefirst epitaxial layer 132 is formed during an oxygen rich epitaxial process,second epitaxial layer 132 is preferably substantially free of oxygen. Likefirst epitaxial layer 132,second epitaxial layer 134 is preferably doped or undoped silicon or silicon germanium. - The process depicted in
FIG. 6 throughFIG. 9 includes two distinct epitaxial processes and additional processing between the two epitaxial steps. In another implementation, recessed source/drain structures 130 are formed with a single continuous epitaxial step. In this embodiment,protective oxide structures 126 are removed prior to the epitaxial step. If the single epitaxial step in this embodiment does not include an oxygen rich phase, electrical isolation between the recessed source/drain 130 and theunderlying substrate 102 is achieved by appropriate doping of the two structures so that the resulting junction is reversed biased under normal operating conditions. This process may include implanting an impurity species intosubstrate 102 prior to performing the epitaxial growth. - Completion of recessed source/
drain structures 130 results in the formation of atransistor 100 as depicted inFIG. 9 . The depicted embodiment oftransistor 100 includes achannel region 107 formed from a top layer of an SOI wafer and recessed, epitaxially formed (i.e., crystalline) source/drain structures 130 that extend through the SOI wafer buriedoxide layer 104 to theunderlying substrate 102 or to anoxide layer 136 overlying the substrate. Recessed source/drain structures 130 may include an oxygen rich portion and an oxygen free portion. Moreover, recessed source/drain structures 130 as shown inFIG. 9 feature sloped sidewalls 122 (FIG. 4 ) to reduce the junction capacitance withsubstrate 102. The recessed source/drain structures 130 have a thickness (vertical dimension) that is greater than the thickness ofchannel 107 thereby alleviating external resistance problems. Because, however, source/drain regions are recessed withinBOX layer 104, an upper surface of source/drain structures 130 coincides approximately with an upper surface ofchannel 107. Thus, there is approximately no vertical overlap between source/drain structures 130 andtransistor gate structure 110 the resulting overlap capacitance is negligible. While negligible overlap capacitance is generally desirable, there may be embodiments that do not substantially suffer from some degree of overlap. In some of these embodiments, the recessed source/drain structure described herein may be supplemented with an elevated source/drain structure if the resulting increase in parasitic capacitance is countered by an increase in overall device performance. - Referring now to
FIGS. 10 through 13 , an alternative processing sequence subsequent to that shown inFIG. 3 is presented. This second embodiment uses substantially vertically sidewalled and recessed source/drain regions and includes an alternative to the reoxidation step described above with respect toFIG. 5 . - Referring to
FIG. 10 , source/drain trenches 120 are formed inBOX layer 104 using a patternedphotoresist layer 118 andgate structure 110 as a mask. Source/drain trenches 120 as depicted inFIG. 10 have sidewalls that are substantially vertical or perpendicular to the upper surface ofsubstrate 102. While the vertically sidewalled source/drain trenches 120 ofFIG. 10 may result in higher junction capacitance between the source/drain regions andsubstrate 102 than the sloped sidewall source/drain structures ofFIG. 9 , the etch process to produce vertical sidewall trenches may be more repeatable or otherwise manufacturable than the sloped sidewall etch process. The junction capacitance of the vertically sidewalled, recessed source/drain structure that will be formed intrenches 120 is still reduced relative to the junction capacitance of bulk transistors, in which the source/drain regions are entirely enclosed by the surrounding substrate or well. - Referring to
FIG. 11 , an oxide spacer formation sequence is performed to form thin (preferably less than 8 nm)oxide spacer structures 127 on sidewalls ofgate structure 110 and source/drain trenches 120 and thereby temporarily insulatechannel structure 107 from subsequent processing steps.Spacer structures 127 are formed in a conventional spacer formation manner by depositing a dielectric such as a conformal oxide layer overwafer 101 and then etching the deposited layer with an anisotropic etch in a manner that will be familiar to those skilled in semiconductor processing. The spacer etch process clears the deposited oxide from the upper surface ofsubstrate 102 in preparation for a subsequent epitaxial formation of the source/drain structures. - Referring to
FIG. 12 , afirst epitaxial layer 132 is formed by epitaxial growth ordeposition overlying substrate 102. Likefirst epitaxial layer 132 ofFIG. 6 ,first epitaxial layer 132 ofFIG. 12 preferably fills only a portion of source/drain trench 120 andfirst epitaxial layer 132 is preferably an oxygen rich layer from which an isolation dielectric layer can be formed between the source/drain structure and theunderlying substrate 102. - Referring to
FIG. 13 , completion of the transistor is then achieved by first performing an anneal to formdielectric layer 136, removing the remaining and exposed portions of oxide spacers 127 (and any oxide layer overlyingepitaxial layer 132 formed during the anneal step). The recessed source/drain structures 130 are then completed by a performing a second epitaxial process to grow asecond epitaxial layer 134 overlyingfirst epitaxial layer 132 and in contact withchannel structure 107. - In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, the reoxidation process shown in conjunction with the sloped sidewall embodiment of source/
drain structures 130 may be used in the vertically sidewalled embodiment. Conversely, the oxide spacer sequence shown in conjunction with the vertical sidewall embodiment of source/drain structures 130 may be used in the sloped sidewall embodiment. Also, the use of a single epitaxial step may be substituted for the sequence of performing an oxygen rich epitaxial step followed by an oxygen free epitaxial step. The single epitaxy embodiment may include a first phase in which an oxygen rich film is grown and a second phase in which an oxygen free film is grown. Alternatively, the single epitaxy step may omit the oxygen rich phase and, instead, isolate the source/drain structures from the substrates by appropriate doping. In addition, whereas specific material and compounds are referred to in the depicted implementations, alternative materials may be used when appropriate.Silicon nitride spacers 116 could, for example, be silicon oxynitride spacers. - Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
- Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
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US20070278591A1 (en) * | 2006-06-01 | 2007-12-06 | International Business Machines Corporation | Method and structure to form self-aligned selective-soi |
US20080050866A1 (en) * | 2005-08-25 | 2008-02-28 | International Business Machines Corporation | Semiconductor structures integrating damascene-body finfet's and planar devices on a common substrate and methods for forming such semiconductor structures |
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