WO2012075670A1 - 一种半导体器件及其制造方法 - Google Patents
一种半导体器件及其制造方法 Download PDFInfo
- Publication number
- WO2012075670A1 WO2012075670A1 PCT/CN2011/001726 CN2011001726W WO2012075670A1 WO 2012075670 A1 WO2012075670 A1 WO 2012075670A1 CN 2011001726 W CN2011001726 W CN 2011001726W WO 2012075670 A1 WO2012075670 A1 WO 2012075670A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- gate
- layer
- dielectric
- region
- gate region
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 106
- 239000000463 material Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 125000006850 spacer group Chemical group 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 8
- 239000003989 dielectric material Substances 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims 1
- 238000002407 reforming Methods 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
一种半导体器件及其制造方法
优先权要求
本申请要求了 2010 年 12 月 08 日 提交的、 申请号为 201010589244.X, 发明名称为 "一种半导体器件及其制造方法" 的中 国专利申请的优先权, 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及一种半导体器件及其制造方法, 具体来说, 涉及一种 基于栅极替代工艺的半导体器件及其制造方法。 背景技术
以"高 k栅介质 /金属栅"技术为核心的 CMOS器件栅工程研究是 22 纳米及以下技术中最有代表性的核心工艺, 与之相关的材料、 工艺及 结构研究已在广泛的进行中。 目前, 针对高 k栅介质 /金属栅技术的研 究可大概分为两个方向, 即前栅工艺和栅极替代工艺, 前栅工艺的栅 极的形成在源、 漏极生成之前, 栅极替代工艺的栅极的形成则在源、 漏极生成之后, 此工艺中栅极不需要承受很高的退火温度。
针对后栅技术, 一个非常重要的工艺是栅槽内的高 k 栅介质和金 属栅材料填充。 随着 MOS 器件特征尺寸的不断减小, 尤其是进入到 22nm及以下技术节点后, MOS器件的物理栅长已经降低到 3 Onm以下, 同时为了降低栅电阻, 栅的高度栅也要保持在一定水平 (如 30nm 左 右) 。 在这样高宽比大于一的具有纳米尺度的栅槽内进行多种材料的 填充具有很大难度, 一个典型的难点就是栅槽内金属栅层和高 k 栅介 质层的均匀性问题和填充金属内的空洞问题。 填充金属内空洞的出现 主要是由于薄膜沉积过程中固有的保型性( Step Coverage )问题造成的, 窄;勾 ;槽填 力的角度来看,、优化栅 构、 降低栅槽的高宽比应该是 更有效的解决方法。
因此, 需要提出一种能够既能降低栅槽的高宽比又能保证足够低 的栅电阻的栅极替代工艺的半导体器件及其制造方法。
发明内容
鉴于上述问题, 本发明提供了一种制造半导体器件的方法, 所述 方法包括: A、 提供半导体衬底; B、 在所述衬底上形成伪栅极区、 在 所述栅极区的侧壁上形成侧墙以及在伪栅极区两侧的半导体衬底内形 成源漏区, 所述伪栅极区包括界面层和伪栅电极; C、 对所述器件进行 平坦化并以源漏区上的介质帽层为停止层; D、对所述器件进行平坦化, 直至暴露介质帽层; E、 进一步去除所述伪栅电极以暴露所述界面层; F、 在所述界面层上形成替代栅极区; G、 对所述器件进行后续加工。
本发明还提供了由以上方法制造的器件, 所述器件包括: 半导体 的第一侧墙; 形成于所述界面层两侧的半导体衬底内的源漏区; _形成 于所述源漏区上的介质帽层, 所述介质帽层与所述第一侧墙具有相同 的高度; 形成于所述界面层上的栅极区, 所述栅极区包括栅介盾层及 其上的栅电极。
通过采用本发明的方法, 以介质帽层的厚度控制栅槽的厚度, 并 进一步根据需要形成所需厚度和宽度的替代栅极, 由于介质帽层的厚 度远小于替代栅极的厚度, 这样既降低栅槽的高宽比, 又能保证足够 低的栅电阻, 还保持了后栅工艺原有的优点。 附图说明
图 1 示出了根据本发明的实施例的半导体器件的制造方法的流程 图; . 、 , 、 , , 、 意图。 具体实施方式
本发明通常涉及一种半导体器件及其制造方法。 下文的公开提供 了许多不同的实施例或例子用来实现本发明的不同结构。 为了简化本 发明的公开, 下文中对特定例子的部件和设置进行描述。 当然, 它们 仅仅为示例, 并且目的不在于限制本发明。 此外, 本发明可以在不同 例子中重复参考数字和 /或字母。 这种重复是为了简化和清楚的目的, 其本身不指示所讨论各种实施例和 /或设置之间的关系。 此外, 本发明
提供了的各种特定的工艺和材料的例子, 但是本领域普通技术人员可 以意识到其他工艺的可应用于性和 /或其他材料的使用。 另外, 以下描 述的第一特征在第二特征之 "上"的结构可以包括第一和第二特征形成 为直接接触的实施例, 也可以包括另外的特征形成在第一和第二特征 之间的实施例, 这样第一和第二特征可能不是直接接触。
参考图 1 , 图 1示出了根据本发明实施例的半导体器件的制造方法 的流程图。 在步骤 S01 , 提供半导体衬底。 参考图 2, 在此实施例中, 半导体衬底 200具有第一区域 201和第二区域 202 , 所述第一区域 201 与第二区域 202 由隔离区 204相互隔离, 所述第一区域 201 与第二区 域 202 由隔离区 208相互隔离, 衬底 200 包括位于晶体结构中的硅衬 底 (例如晶片 ) , 还可以包括其他基本半导体或化合物半导体, 例如 Ge、 GeSi、 GaAs、 InP、 SiC或金刚石等。 根据现有技术公知的设计要 求 (例如 p型衬底或者 n型衬底) , 衬底 200可以包括各种掺杂配置。 此外, 衬底 200可以可选地包括外延层, 可以被应力改变以增强性能, 以及可以包括绝缘体上硅( SOI )结构。 隔离区 204可以包括二氧化硅 或其他可以分开器件的有源区的材料。
在步骤 S02 , 在所述衬底上形成伪栅极区、 在所述栅极区的侧壁上 形成侧墙以及在伪栅极区两侧的半导体衬底内形成源漏区, 所述伪栅 极区包括界面层和伪栅电极。 可以利用常规的工艺步骤、 材料以及设 备来形成该步骤的结构。
在一个实施例中, 参考图 2-图 5 , 具体来说, 首先, 在衬底 200 上依次形成界面层 205和伪栅电极 206 , 参考图 2, 界面层 205可以包 括 Si02 、 SiONx、 HfSOx等, 厚度可以为 0.3-lnm, 伪栅电极 206可以 包括非晶硅或多晶硅, 厚度可以为 10-60nm。
而后, 在所述伪栅电极 206上形成硬掩膜 208, 在本实施例中, 通 过依次沉积 Si02的第一硬掩膜 208-1、 Si3N4的第二硬掩膜 208-2 和 Si02的第三硬掩膜 208-3来形成,参考图 3, Si02的硬掩膜 208-1、208-3 厚度依次可以为 5-30nm , Si3N4 的第二硬掩膜 208-2 的厚度可以为 10-70nm, 所述硬掩膜还可以是其他材料形成的其他的结构, 此处仅为 示例, 不限于此。
而后, 进行图形化, 参考图 4 , 可以利用干法或湿法刻蚀技术刻蚀 所述界面层 205、 伪栅电极 206和硬掩膜 208的堆叠, 并进行清洗, 在
第一区域 201 和第二区域 202上形成了如图 4的结构, 其中第三硬掩 膜 208-3在刻蚀及后续清洗中被除去了。
而后, 在所述界面层 205、 伪栅电极 206 及硬掩膜 208-1、 208-2 的堆叠的侧壁上形成側墙 210, 参考图 5, 在一个实施例中, 侧墙 210 为三层结构, 通过沉积、 刻蚀依次形成第一侧墙 210-1为 Si3N4、 第二 侧墙 210-2为 Si02和第三侧墙 210-3为 Si3N4 , 厚度依次为 5-15nm、 2-10nm, 10-40nm, 所述侧墙还可以为包括其他材料的其他结构, 此处 仅仅是作为示例, 不局限于此。
而后, 可以通过根据期望的晶体管结构, 注入 p型或 n型掺杂物 或杂质到第一区域 201和第二区域 202的衬底 200中而形成源漏区 212、 214 , 参考图 5所示, 源漏区 212、 214可以由包括光刻、 离子注入、 扩散和 /或其他合适工艺的方法形成。 此外, 可选地, 在形成第一侧墙 210-1后, 可以形成源漏延伸区。 优选地, 在形成源漏区 212、 214后, 还可以通过自对准金属硅化的方法, 在源漏区上形成金属硅化物 215 , 以减小接触电阻。
在步骤 S03, 在所述伪栅极区以及源漏区上形成介质帽层。 参考图 6, 在所述器件结构上沉积介质帽层 216, 所述介质帽层 216可以包括 Si3N4、 Si02或低 k材料, 可以通过包括原子沉积方法、 等离子增强化 学气象沉积 (PECVD ) 或其他方法来形成, 所述介质帽层 216的厚度 为 5-60nm, 介质帽层的厚度高于界面层。 本发明通过介质帽层的厚度 来控制随后工艺中栅槽的高度(后栅工艺中,去除伪栅极形成的沟槽)。
优选地, 为了防止后续工艺中, 平坦化时对小尺寸栅结构的不利 影响, 参考图 7, 可以在上述器件上进一步沉积介质层 218 , 所述介质 层 218具有与介盾帽层 216不同的材料, 以在后续平坦化工艺时, 停 止在介质帽层 216上。
在步骤 S04 ,对所述器件进行平坦化并以源漏区上的介盾帽层为停 止层。 可以离用 CMP (化学机械平坦化) 的方法, 对图 6或图 7中所 示的器件进行平坦化, 并以源漏区 212、 214上的介质帽层 216为停止 层, 参考图 8。
在步骤 S05 , 进一步去除所述伪栅电极以暴露所述界面层。 参考图
9, 可以通过 RIE的方法, 将剩余的伪栅电极 206去除, 直至暴露所述 界面层 205,形成栅槽 220 ,可见, 所述栅槽 220的高度由介质帽层 216
的厚度来决定, 由于介质帽层的厚度远小于替代栅极的厚度, 这样既 降低栅精的高宽比, 这样在进一步形成替代栅极时, 提高了窄沟槽填 充能力。 此外, 优选地, 可以进一步利用湿法刻蚀将界面层 205去除, 并重新形成界面层 205 , 以提高界面层的盾量。
在步骤 S06,形成替代栅极区,替代栅极区包括栅介质层和栅电极。 可以在栅槽的宽度范围内形成栅电极, 也可以在栅槽内及栅槽之外形 成栅电极, 来减小栅电阻。 具体步骤包括:
首先, 如图 10和 1 1 所示, 在所述器件上依次沉积栅介质层 222 和栅电极, 所述栅介质层 222可以包括但不限于高 k介质材料(例如, 和氧化硅相比, 具有高介电常数的材料) , 厚度为 0.8-4nm, 高 k介质 材料的例子包括例如铪基材料, 如 Hf02、 HfSiO、 HfSiON, H仃 aO、 HfTiO、 HfZrO, 其组合和 /或者其它适当的材料, 所述栅电极可以是一 层或多层结构, 第一区域和第二区域的栅电极可以采用相同或不同的 材料, 在图示实施例中, 所述栅电极为两层结构, 第一区域和第二区 域的栅电极不同的材料(n型和 p型金属材料) , 可以通过在器件上沉 积第一金属栅 224 , 例如 TiAIN, 厚度为 l-10nm, 而后去除第二区域 202上的笫一金属栅 224 , 而后再沉积另一金属栅 225 , 例如 TiN, 厚 度为 l-10nm, 并去除第一区域 201 上的金属栅 225, 从而在第一区域 201 和第二区域 202上分别形成不同材料的第一金属栅 224、 225 , 而 后在所述器件上进一步沉积第二金属栅 226, 参考图 1 1, 所述第二金 属栅 226可以包括低电阻的金属材料, 例如 Al、 Ti、 1^八1>(和 \¥等。 而后, 利用 CMP对第二金属栅 226平坦化, 如图 12所示。 而后进行 图形化, 在一个实施例中, 仅对栅电极图形化, 图形化时可以根据需 要去除栅电极, 从而形成具有不同宽度的栅电极的替代栅, 参考图 13, 所述栅电极 224和 226的宽度大于栅槽的宽度(即界面层 205的宽度), 这样使替代栅具有更小的栅电阻, 参考图 17, 还可以形成所述栅电极 224和 226的宽度与栅槽的宽度相同的替代栅。 在另外的实施例中, 可 以进一步对栅介质层 222进行图形化, 参考图 16。
而后, 根据需要对所述器件进行后续加工。 例如, 在所述替代栅 极区的侧壁形成替代侧墙 228,并覆覆盖所述器件形成层间介质层 230, 参考图 14所示, 以及在所述源漏区上形成接触塞 232, 参考图 15-17。
以上对本发明实施例的半导体器件的制造方法进行了详细的描
述, 此外, 根据上述方法, 本发明还提出了一种根据上述方法形成半 导体器件, 参考图 15-17, 所述器件包括: 半导体衬底 200; 形成于所 述半导体衬底 200上的界面层 202 以及形成于所述界面层 205侧壁的 第一侧墙 210; 形成于所述界面层 205 两侧的半导体村底内的源漏区 212、 214; 形成于所述源漏区上的介质帽层 216, 所述介质帽层 216与 所述第一侧墙 210具有相同的高度; 形成于所述界面层 205上的栅极 区, 所述栅极区包括栅介质层 222 及其上的栅电极。 所述第一侧墙的 厚度可以高于所述界面层的厚度。 所述介质帽层的厚度为 5-60nm。 根 据需要, 所述栅极区的宽度可以大于或者等于界面层的宽度, 在栅极 区的宽度大于界面层的宽度时, 还进一步包括形成于所述第一侧墙内 壁及部分第一侧墙上的栅介质层, 及栅介质层上的栅极区, 或者形成 于所述第一侧墙内壁、 第一侧墙上以及介质帽层上的栅介质层, 以及 位于所述第一侧墙内壁及部分第一侧墙上的栅介质层之上的栅极区。 所述栅介质层包括高 k介质材料, 所述栅电极包括 n型或 p型金属栅。
以上对使用介质帽层控制栅槽高度的基于后栅工艺的半导体器件 及其形成方法进行了详细的描述, 本发明通过介质帽层的厚度控制栅 槽的厚度, 并进一步根据需要形成所需厚度和宽度的替代栅极, 由于 介质帽层的厚度远小于替代栅极的厚度, 这样既降低栅槽的高宽比, 提高了窄沟槽填充能力, 又能保证足够低的栅电阻, 还保持了后栅工 艺原有的优点。
虽然关于示例实施例及其优点已经详细说明, 应当理解在不脱离 本发明的精神和所附权利要求限定的保护范围的情况下, 可以对这些 实施例进行各种变化、 替换和修改。 对于其他例子, 本领域的普通技 术人员应当容易理解在保持本发明保护范围内的同时, 工艺步骤的次 序可以变化。
此外, 本发明的应用范围不局限于说明书中描述的特定实施例的 工艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开 内容, 作为本领域的普通技术人员将容易地理解, 对于目前已存在或 者以后即将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步 骤, 其中它们执行与本发明描述的对应实施例大体相同的功能或者获 得大体相同的结果, 依照本发明可以对它们进行应用。 因此, 本发明 所附权利要求旨在将这些工艺、 机构、 制造、 物质组成、 手段、 方法
或步骤包含在其保护范围内
Claims
1、 一种制造半导体器件的方法, 所述方法包括:
A、 提供半导体衬底;
B、 在所述衬底上形成伪栅极区、 在所述栅极区的側壁上形成侧墙 以及在伪栅极区两侧的半导体衬底内形成源漏区, 所述伪栅极区包括 界面层和伪栅电极;
C、 在所述伪栅极区以及源漏区上形成介质帽层;
D、 对所述器件进行平坦化并以源漏区上的介质帽层为停止层; E、 进一步去除所述伪栅电极以暴露所述界面层;
F、 在所述界面层上形成替代栅极区;
G、 对所述器件进行后续加工。
2、 根据权利要求 1所述的方法, 其中所述步骤 F包括: 在所述器 件上依次沉积栅介质层和栅电极; 图形化所述栅电极, 以形成替代栅 极区, 其中所述栅电极的宽度大于或等于所述界面层的宽度。
3、 根据权利要求 1所述的方法, 其中所述步骤 F包括: 在所述器 件上依次沉积栅介质层和栅电极; 图形化所述栅电极及栅介质层, 以 形成替代栅极区, 其中所述栅电极的宽度大于所述界面层的宽度。
4、根据权利要求 1所述的方法, 其中在所述步骤 C和 D之间还包 括: 覆盖所述器件以形成介质层, 所述介盾层具有与介盾帽层不同的 材料。
5、根据权利要求 1所述的方法,其中所述步骤 E和 F之间还包括: 去除所述界面层, 并重新形成所述界面层。
6、 根据权利要求 1所述的方法, 其中所述介质帽层的厚度大于所 述界面层的厚度。
7、 根据权利要求 1-5 中任一项所述的方法, 其中所述介质帽层的 厚度为 5-60nm。
8、 根据权利要求 1-5 中任一项所述的方法, 其中所述栅介质层包 括高 k介质材料, 所述栅电极包括 n型或 p型金属栅。
9、 根据权利要求 1所述的方法, 其中所述步骤 G包括: 在所述替 代栅极区的侧壁形成替代侧墙, 以及覆盖所述器件形成层间介质层, 以及在所述源漏区上形成接触塞。
10、 一种半导体器件, 所述器件包括:
半导体村底; 第一侧墙; ' ' 、 ― 、 、 , ― ' 、 形成于所述界面层两侧的半导体村底内的源漏区;
形成于所述源漏区上的介质帽层, 所述介质帽层与所述第一侧墙 具有相同的高度;
形成于所述界面层上的栅极区, 所述栅极区包括栅介质层及其上 的栅电极。
1 1、 根据权利要求 10所述的器件, 其中所述第一侧墙的厚度高于 所述界面层的厚度。
12、 根据权利要求 1 1所述的器件, 还包括形成于所述第一侧墙内 壁及部分第一侧墙上的栅介质层, 及栅介质层上的栅极区。
13、 根据权利要求 1 1所述的器件, 还包括形成于所述第一侧墙内 壁、 第一侧墙上以及介质帽层上的栅介质层, 以及位于所述第一侧墙 内壁及部分第一侧墙上的栅介质层之上的栅极区。
14、根据权利要求 10-13中任一项所述的器件, 其中所述介质帽层 的厚度为 5-60nm。
15、根据权利要求 10- 13中任一项所述的器件, 还包括形成于所述 栅极区侧壁的第二侧墙以及覆盖所述器件的层间介质层。
16、根据权利要求 10-13中任一项所述的器件, 其中所述栅介质层 包括高 k介盾材料, 所述栅电极包括 n型或 p型金属栅。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/395,608 US8802518B2 (en) | 2010-12-08 | 2011-10-17 | Semiconducor device and method for manufacturing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201010589244.XA CN102569076B (zh) | 2010-12-08 | 2010-12-08 | 一种半导体器件及其制造方法 |
CN201010589244.X | 2010-12-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2012075670A1 true WO2012075670A1 (zh) | 2012-06-14 |
Family
ID=46206554
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2011/001726 WO2012075670A1 (zh) | 2010-12-08 | 2011-10-17 | 一种半导体器件及其制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8802518B2 (zh) |
CN (1) | CN102569076B (zh) |
WO (1) | WO2012075670A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20140104890A (ko) * | 2013-02-21 | 2014-08-29 | 글로벌파운드리즈 인크. | 집적 회로들 및 금속 게이트 전극들을 갖는 집적 회로들을 제조하기 위한 방법들 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103839793B (zh) * | 2012-11-21 | 2018-02-13 | 中国科学院微电子研究所 | 半导体器件制造方法 |
CN104037130B (zh) * | 2013-03-05 | 2017-09-22 | 中芯国际集成电路制造(上海)有限公司 | Cmos晶体管的制作方法 |
CN104217935B (zh) * | 2013-06-05 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | 晶体管的形成方法 |
CN104425360B (zh) * | 2013-09-05 | 2017-05-17 | 中芯国际集成电路制造(上海)有限公司 | 导电插塞的形成方法 |
CN104576338B (zh) * | 2013-10-13 | 2017-10-03 | 中国科学院微电子研究所 | 一种mosfet结构及其制造方法 |
US10892164B2 (en) * | 2019-04-16 | 2021-01-12 | International Business Machines Corporation | Dual hard mask replacement gate |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6271094B1 (en) * | 2000-02-14 | 2001-08-07 | International Business Machines Corporation | Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance |
US6440808B1 (en) * | 2000-09-28 | 2002-08-27 | International Business Machines Corporation | Damascene-gate process for the fabrication of MOSFET devices with minimum poly-gate depletion, silicided source and drain junctions, and low sheet resistance gate-poly |
CN101783298A (zh) * | 2009-01-21 | 2010-07-21 | 中国科学院微电子研究所 | 抑制高k栅介质/金属栅结构界面层生长的方法 |
CN102110650A (zh) * | 2009-12-29 | 2011-06-29 | 中国科学院微电子研究所 | 一种半导体器件及其制造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6495437B1 (en) * | 2001-02-09 | 2002-12-17 | Advanced Micro Devices, Inc. | Low temperature process to locally form high-k gate dielectrics |
DE102007046849B4 (de) * | 2007-09-29 | 2014-11-06 | Advanced Micro Devices, Inc. | Verfahren zur Herstellung von Gateelektrodenstrukturen mit großem ε nach der Transistorherstellung |
-
2010
- 2010-12-08 CN CN201010589244.XA patent/CN102569076B/zh active Active
-
2011
- 2011-10-17 WO PCT/CN2011/001726 patent/WO2012075670A1/zh active Application Filing
- 2011-10-17 US US13/395,608 patent/US8802518B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6271094B1 (en) * | 2000-02-14 | 2001-08-07 | International Business Machines Corporation | Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance |
US6440808B1 (en) * | 2000-09-28 | 2002-08-27 | International Business Machines Corporation | Damascene-gate process for the fabrication of MOSFET devices with minimum poly-gate depletion, silicided source and drain junctions, and low sheet resistance gate-poly |
CN101783298A (zh) * | 2009-01-21 | 2010-07-21 | 中国科学院微电子研究所 | 抑制高k栅介质/金属栅结构界面层生长的方法 |
CN102110650A (zh) * | 2009-12-29 | 2011-06-29 | 中国科学院微电子研究所 | 一种半导体器件及其制造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20140104890A (ko) * | 2013-02-21 | 2014-08-29 | 글로벌파운드리즈 인크. | 집적 회로들 및 금속 게이트 전극들을 갖는 집적 회로들을 제조하기 위한 방법들 |
KR101595932B1 (ko) | 2013-02-21 | 2016-02-19 | 글로벌파운드리즈 인크. | 집적 회로들 및 금속 게이트 전극들을 갖는 집적 회로들을 제조하기 위한 방법들 |
Also Published As
Publication number | Publication date |
---|---|
CN102569076B (zh) | 2015-06-10 |
US20130092986A1 (en) | 2013-04-18 |
US8802518B2 (en) | 2014-08-12 |
CN102569076A (zh) | 2012-07-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11251303B2 (en) | Method for fabricating a strained structure and structure formed | |
KR102073395B1 (ko) | 분리 병합된 소스/드레인 구조체를 가지는 반도체 디바이스를 제조하는 방법 | |
US9076819B2 (en) | Contact structure of semiconductor device | |
TWI584478B (zh) | 半導體裝置及其製造方法 | |
KR102287552B1 (ko) | 게이트 라스트 프로세스에서의 선택적 하이 k 형성 | |
US20090039442A1 (en) | Semiconductor Devices and Methods of Manufacture Thereof | |
US20090189201A1 (en) | Inward dielectric spacers for replacement gate integration scheme | |
US10026641B2 (en) | Isolation structure of semiconductor device | |
WO2011079604A1 (zh) | 一种半导体器件及其制造方法 | |
TWI478340B (zh) | 半導體元件及於基板上之金屬閘結構之製造方法 | |
WO2011066747A1 (zh) | 半导体器件及其形成方法 | |
WO2012075670A1 (zh) | 一种半导体器件及其制造方法 | |
KR20200066569A (ko) | 반도체 디바이스를 제조하는 방법 및 반도체 디바이스 | |
WO2013000268A1 (zh) | 一种半导体结构及其制造方法 | |
WO2013067725A1 (zh) | 一种半导体结构的制造方法 | |
CN104821332A (zh) | 半导体器件结构和制造方法 | |
WO2013170477A1 (zh) | 半导体器件及其制造方法 | |
TWI240375B (en) | Integrated circuit structure and method of fabrication | |
WO2013000197A1 (zh) | 一种半导体结构及其制造方法 | |
WO2011124059A1 (zh) | 一种高速晶体管结构及其制造方法 | |
WO2013159455A1 (zh) | 半导体结构及其制造方法 | |
WO2011113270A1 (zh) | 一种半导体器件及其制造方法 | |
CN107623034B (zh) | 一种半导体器件及制备方法、电子装置 | |
WO2013000196A1 (zh) | 一种半导体结构及其制造方法 | |
CN117836953A (zh) | 具有沟槽内部间隔物的全环栅场效应晶体管及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 13395608 Country of ref document: US |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 11846500 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 11846500 Country of ref document: EP Kind code of ref document: A1 |