WO2015051564A1 - 一种mosfet结构及其制造方法 - Google Patents

一种mosfet结构及其制造方法 Download PDF

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Publication number
WO2015051564A1
WO2015051564A1 PCT/CN2013/085664 CN2013085664W WO2015051564A1 WO 2015051564 A1 WO2015051564 A1 WO 2015051564A1 CN 2013085664 W CN2013085664 W CN 2013085664W WO 2015051564 A1 WO2015051564 A1 WO 2015051564A1
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gate stack
layer
source
dummy gate
drain
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PCT/CN2013/085664
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English (en)
French (fr)
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尹海洲
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中国科学院微电子研究所
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Priority to US14/905,440 priority Critical patent/US9496342B2/en
Publication of WO2015051564A1 publication Critical patent/WO2015051564A1/zh

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    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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Definitions

  • the present invention relates to a MOSFET structure and a method of fabricating the same. More specifically, it relates to a MOSFET structure for reducing off-state leakage current and a method of fabricating the same.
  • the channel portion in order to enhance the gate-to-channel control ability and better suppress the short channel effect, it is desirable that the channel portion be as narrow as possible.
  • the channel thickness is less than 10 nm, since the carrier mobility decreases as the channel thickness decreases, the device performance is more severely affected.
  • the channel portion near the source end is particularly affected. Severe, and at the drain end, the effect of channel width on mobility has no major effect due to the effect of high field saturation.
  • Drain Induction Barrier Lower is a non-ideal effect in short-channel devices, that is, when the channel length is reduced, the source-drain voltage is increased to make the source and drain regions PN
  • the junction depletion region is close, the power line in the channel can pass from the drain region to the source region, and the source barrier height is lowered, so that the number of carriers for injecting the source region into the channel increases, and the drain current increases.
  • the influence of the DIBL becomes more and more serious, the transistor threshold voltage is lowered, the device voltage gain is lowered, and the integration of the VLSI is also limited.
  • the present invention provides a method for fabricating a MOSFET that effectively reduces DIBL current, effectively suppressing short channel effects of the device and improving device performance. Specifically, the manufacturing method provided by the present invention includes the following steps:
  • the vacancy is located on the bottom of the source side, and the method of forming the vacancy is a combination of anisotropic etching and isotropic etching.
  • the forbidden band width of the semiconductor layer gradually increases from a side closer to the source end to a side closer to the drain end;
  • the material of the semiconductor layer is silicon germanium
  • the present invention also provides a MOSFET structure, including:
  • Source and drain regions located in the bottom of both sides of the gate stack
  • the length L of the semiconductor layer under the gate stack is less than or equal to the width of the gate stack.
  • silicon germanium having a small band gap is used instead of the original channel material silicon, and the band gap of the channel material is made from the source by adjusting the proportion of silicon germanium in the silicon germanium material. End Gradually increasing to the leak end, effectively increasing the height difference between the drain end barrier and the source end barrier, and reducing
  • the present invention can effectively suppress the leakage current caused by the GIDL effect. Therefore, with the semiconductor structure of the present invention, device leakage current can be effectively reduced, and device performance can be optimized.
  • FIG. 1 through 6 are cross-sectional views showing respective stages of fabrication of a MOSFET in accordance with an embodiment of the present invention.
  • the present invention provides a MOSFET structure, including: a substrate 100; a gate stack 600 above the substrate 100; and a bottom of the gate stack 600 a source/drain region 400; an interlayer dielectric layer 500 covering the source and drain regions; and a semiconductor layer 300 in the substrate 100 under the gate stack 600 and on one side thereof, wherein the semiconductor layer 300 is formed
  • the material forbidden band width gradually increases along the channel direction from the side close to the source end to the side closer to the drain end.
  • the semiconductor channel region is located on the surface of the substrate, and the preferred material is a single crystal silicon or a single crystal germanium alloy film having a thickness of 5 to 20 nm. This region is extremely lightly doped or even undoped. In the case of doping, the doping type is opposite to that of the source and drain regions.
  • the source and drain regions are respectively located on both sides of the gate stack 600 in the semiconductor layer above the substrate. The thickness of the source region is greater than the thickness of the drain region. The thickness of the channel portion on the side close to the source region is larger than the thickness of the channel near the drain end side, and is 10 nm to 60 nm.
  • the semiconductor layer 300 is located under the gate stack 600 and has a length L that is less than or equal to the width of the gate stack 600.
  • the raw material of the original village is replaced by a material with a gradual change of the forbidden band width.
  • silicon germanium with a small band gap is used instead of the original channel material silicon, and the band gap of the channel material is adjusted by adjusting the proportion of silicon germanium in the silicon germanium material.
  • the width gradually increases from the source end to the drain end, effectively increasing the height difference between the drain end barrier and the source end barrier, and reducing the leakage current caused by the DIBL.
  • the forbidden band width of the semiconductor material on the drain side is larger than the semiconductor band gap on the source side, the present invention can effectively suppress the leakage current caused by the GIDL effect.
  • a semiconductor substrate 100 is first provided, and a dummy gate structure 200 is formed on the substrate 100.
  • the dummy gate structure 200 may be a single layer or a plurality of layers.
  • the dummy gate structure 200 may comprise a polymer material, amorphous silicon, polysilicon or TiN, and may have a thickness of 10 nm to 200 nm.
  • the dummy gate structure includes polysilicon and dioxide. Specifically, the polysilicon is filled in the gate vacancies by chemical vapor deposition, and the height is slightly lower than the sidewall 10-20 nm, and then a polysilicon is formed.
  • the layer of the silicon dioxide dielectric layer may be formed by epitaxial growth, oxidation, CVD or the like.
  • the gate electrode pattern is then formed using a conventional CMOS process photolithography and etching of the dummy gate stack deposited. A portion of the silicon germanium channel layer 101 covered by the gate dielectric layer forms a channel region of the transistor. It should be noted that the method of forming the gate dielectric layer is the same or similar, and therefore will not be described again.
  • an epitaxial protective layer 101 is formed over the semiconductor structure to cover the substrate 100 and the dummy gate stack 200.
  • the epitaxial protective layer 101 functions to prevent formation of a product on the semiconductor structure on the side of the drain end when epitaxial growth is performed in the subsequent step.
  • the material of the epitaxial protective layer 101 is silicon dioxide and has a thickness of 5 to 20 nm.
  • sacrificial spacers 102 are formed on the sidewalls of the gate stack for spacing the gates apart.
  • a silicon nitride sacrificial spacer dielectric layer of 40 nm to 80 nm thick is deposited by LPCVD, and then a silicon nitride sacrificial spacer 102 having a width of 35 nm to 75 nm is formed on both sides of the gate electrode by a guest technique.
  • the sacrificial sidewalls 102 can also be formed from silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
  • the sacrificial sidewall 102 may have a multi-layered structure.
  • the sacrificial spacers 102 may also be formed by a deposition etch process including a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm, or 80 nm.
  • FIG. 1 A cross-sectional view of the semiconductor structure after completion of the above steps is shown in FIG.
  • the dummy gate stack 200 and the substrate 100 on one side thereof are covered with a mask or photoresist 206 to form vacancies 102 on the substrate, as shown in FIG.
  • the photoresist is covered on the semiconductor structure, and the photoresist 206 on the semiconductor structure on the source side is removed by a step of development, exposure, etc., to expose the substrate 100.
  • the semiconductor structure is etched to form vacancies 102.
  • the vacancies 102 are located on the substrate side of the source side, and the length L of the overlap with the dummy gate stack 200 is less than or equal to the width of the dummy gate stack.
  • the etching method is a combination of anisotropic etching and isotropic etching.
  • the forbidden band width of the material in the channel near the drain end is larger than the forbidden band width of the material in the channel near the source end, which can effectively reduce the GIDL The leakage current caused.
  • a semiconductor layer 300 is grown layer by layer on the semiconductor structure to fill the vacancies 102, as shown in FIG.
  • the material of the semiconductor layer 300 is silicon germanium, and the forbidden band width gradually increases from a side close to the source end to a side close to the drain end, that is, the proportion of silicon in the silicon germanium gradually increases.
  • a silicon germanium material is grown layer by layer in the vacancy 102 by a selective epitaxy method. Due to the existence of the epitaxial protective layer 101, the grown silicon germanium exists only in the vacancy 102 and does not exist in the semiconductor drain region and the dummy region.
  • the gate surface is grown.
  • the band gap variation of the material of the channel region can be controlled by adjusting the number and proportion of the silicon germanium material to obtain the desired band structure. Since the proportion of silicon in the semiconductor material at the drain end is gradually increased, the forbidden band width of the semiconductor layer 300 gradually increases from the side closer to the source end to the side closer to the drain end, effectively increasing the drain barrier and The height difference between the source barriers reduces the leakage current caused by DIBL.
  • a Halo implant can also be performed to form a Halo implant region.
  • the impurity type of the source-drain extension region is the same as the device type, and the impurity type of the Halo implant is opposite to the device type.
  • sidewall spacers 201 are formed on the sidewalls of the gate stack for spacing the gates. Specifically, a silicon nitride spacer layer of a thickness of 40 nm to 80 nm is deposited by LPCVD, and then a silicon nitride spacer 201 having a width of 35 nm to 75 nm is formed on both sides of the gate electrode by a guest technique. Sidewall 201 can also be formed from silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials. The side wall 201 may have a multi-layered structure. The spacers 201 may also be formed by a deposition etching process including a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm or 80 nm.
  • a silicon dioxide dielectric layer having a thickness of 10 nm to 35 nm is deposited on the semiconductor structure, and the dielectric layer is used as a buffer layer, and ions are implanted into the source and drain regions.
  • the dopant is boron or boron or indium or gallium.
  • the dopant is phosphorus or arsenic or antimony.
  • the doping concentration is 5el0 19 cm- 3 ⁇ lel0 2G cm- 3 .
  • an interlayer dielectric layer 500 is formed on the semiconductor structure.
  • the material of the interlayer dielectric layer 500 is silicon dioxide.
  • the semiconductor structure in which the interlayer dielectric layer 500 is deposited is as shown in FIG.
  • the dummy gate structure 200 is removed to form dummy gate vacancies.
  • the removal of the dummy gate structure 200 can be removed by wet etching and/or dry etching. In one embodiment, plasma etching is employed.
  • the gate stack 600 is formed in the gate vacancies.
  • the gate stack 600 may be only a metal gate or a metal/polysilicon composite gate with silicide on the upper surface of the polysilicon.
  • the gate dielectric layer 601 next deposits the work function adjusting layer 602, and then forms the gate metal layer 603 over the work function metal layer.
  • the gate dielectric layer 601 may be a thermal oxide layer, including silicon oxide or silicon oxynitride; or a high-k dielectric such as HfA10N, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, A1 2 0 3 ,
  • the gate dielectric layer 601 may have a thickness of 1 nm to 10 nm, for example, 3 nm, 5 nm, or 8 nm, of one or a combination of La 2 O 3 , ZrO 2 , and LaAlO.
  • the gate dielectric layer 601 can be formed by processes such as thermal oxidation, chemical vapor deposition (CVD), or atomic layer deposition (ALD).
  • the work function metal layer can be made of a material such as TiN or TaN, and has a thickness ranging from 3 nm to 15 nm.
  • the metal conductor layer may be in a one-layer or multi-layer structure.
  • the material can be TaN, TaC, TiN, TaAlN, One of TiAlN, ⁇ 1 ⁇ , TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x or a combination thereof.
  • the thickness may range, for example, from 10 nm to 40 nm, such as 20 nm or 30 nm.
  • the ultra-thin SOI MOS transistor can be fabricated by finally entering a conventional CMOS thick-film process, including a passivation layer, an open contact hole, and metallization.
  • a silicon germanium having a larger band gap is used instead of the original channel material silicon, and by adjusting the proportion of silicon germanium in the silicon germanium material, the band gap of the channel material is changed from the source end to the drain end. Gradually decreasing, effectively increasing the height difference between the drain barrier and the source barrier, reducing the leakage current caused by DIBL.
  • the vacancy is located in the semiconductor structure on the source side, the forbidden band width of the material in the channel near the drain end is larger than the forbidden band width of the material in the channel near the source end, and the leakage current caused by GIDL can be effectively reduced. . Therefore, with the semiconductor structure of the present invention, device leakage current can be effectively reduced, and device performance can be optimized.

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  • Thin Film Transistor (AREA)

Abstract

一种MOSFET结构及其制造方法，其中制造方法包括：a.提供衬底（100）、伪栅叠层（200）、外延保护层（101）以及牺牲侧墙（205）；b.用掩膜板覆盖伪栅叠层（200）及其一侧的衬底（100），在衬底（100）上形成空位（102）；c.在半导体结构上逐层生长半导体层（300），以填充空位（102）；d.去除外延保护层（101）以及牺牲侧墙（205），在半导体结构上依次形成源漏扩展区、侧墙（201）、源漏区（400）以及层间介质层（500）；e.去除伪栅叠层（200）以形成伪栅空位，在伪栅空位中形成栅极叠层（600）。本方法制造的MOSFET结构可以显著减小漏端感应势垒降低效应对器件性能的影响。

Description

一种 MOSFET结构及其制造方法
[0001]本申请要求了 2013年 10月 13 日提交的、 申请号为 201310476449.0、 发明名称为 "一种 MOSFET 结构及其制造方法" 的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
[0002】本发明涉及一种 MOSFET结构及其制造方法。 更具体而言， 涉及一种 用于降低关态漏电流的 MOSFET结构及其制造方法。 技术背景
[0003]在 MOSFET结构中， 为了增强栅对沟道的控制能力， 更好的抑制短沟 道效应， 希望沟道部分越窄越好。 然而， 在沟道厚度小于 10nm以后， 由于载 流子迁移率随着沟道厚度的减小而降低， 器件性能会受到较严重的影响， 特 別地， 在靠近源端的沟道部分所受影响尤为严重， 而在漏端， 由于高场饱和 作用的影响， 沟道宽度对迁移率的影响不起主要作用。
[0004】漏端感应势垒降低效应 （Drain Induction Barrier Lower) 是短沟道器件 中存在的一种非理想效应， 即当沟道长度减小， 源漏电压增加而使得源区和 漏区 PN结耗尽区靠近时， 沟道中的电力线可以从漏区穿越到源区， 并导致源 端势垒高度降低， 从而使源区注入沟道的载流子数目增加， 漏端电流增大。 随着沟道长度的进一步减小， DIBL的影响越来越严重， 使晶体管阔值电压降 低， 器件电压增益下降， 同时也限制了超大规模集成电路集成度的提高。
[0005] 因此， 如何提供一种可有效减小 MOS 器件 DIBL 电流的 MOS 管制 作方法， 已成为业界亟待解决的技术问题。 发明内容
[0006]本发明提供了一种有效减小 DIBL电流的 MOSFET制作方法， 有效抑 制了器件的短沟道效应， 提高了器件性能。 具体地， 本发明提供的制造方法 包括以下步骤：
a. 提供村底、 伪栅叠层、 外延保护层以及牺牲侧墙；
b. 用掩膜板覆盖伪栅叠层及其一侧的村底， 在村底上形成空位；
c 在所述半导体结构上逐层生长半导体层， 以填充空位；
d. 去除所述外延保护层以及牺牲侧墙，在所述半导体结构上依次形成源漏 扩展区、 侧墙、 源漏区以及层间介质层；
e. 去除伪栅叠层以形成伪栅空位，在所述伪栅空位中依次沉积栅极介质层、 功函数调节层和栅极金属层。
[0007】其中， 优选的， 所述空位位于源端一侧的村底上， 形成所述空位的方 法是各向异性刻蚀与各向同性刻蚀的组合。
[0008]其中， 所述空位与伪栅叠层重叠的长度 L小于或等于伪栅叠层宽度。
[0009]其中， 所述半导体层的禁带宽度从靠近源端一侧到至靠近漏端一侧逐 渐增大；
[0010】其中， 所述半导体层的材料为硅锗；
[0011]其中， 所述半导体层从靠近源端一侧到至靠近漏端一侧硅锗中硅的比 例逐渐增大。
[0012】相应地， 本发明还提供一种 MOSFET结构， 包括：
村底；
位于所述村底上方的栅极叠层；
位于所述栅极叠层两侧村底中的源漏区；
覆盖所述源漏区的层间介质层；
以及位于所述栅极叠层下方及其一侧的村底中的半导体层， 其中， 构成 所述半导体层的材料禁带宽度沿着沟道方向从靠近源端一侧到至靠近漏端一 侧逐渐增大。
[0013]其中， 所述半导体层位于栅极叠层下方的长度 L小于等于栅极叠层的 宽度。
[0014]根据本发明所述的半导体结构， 采用禁带宽度较小的硅锗代替原沟道 材料硅， 且通过调节硅锗材料中硅锗的比例， 使沟道材料的禁带宽度从源端 到漏端逐渐增加， 有效地增大了漏端势垒和源端势垒之间的高度差， 减小了
DIBL所引起的漏电流。 同时， 由于漏端一侧的半导体材料禁带宽度大于源端 一侧的半导体禁带宽度， 本发明还能有效的抑制 GIDL效应所引起的漏电流。 因此， 通过本发明中的半导体结构， 可以有效的减小器件漏电流， 优化器件 性能。 附图说明
[0015]通过阅读参照以下附图所作的对非限制性实施例所作的详细描述， 本 发明的其它特征、 目的和优点将会变得更明显：
图 1〜图 6为根据本发明的一个具体实施方式中 MOSFET各个制造阶段的 剖面图。
附图中相同或相似的附图标记代表相同或相似的部件。 具体实施方式
[0016】为使本发明的目的、 技术方案和优点更加清楚， 下面将结合附图对本 发明的实施例作详细描述。
[0017】下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其 的元件。 下面通过参考附图描述的实施例是示例性的， 仅用于解释本发明， 而不能解释为对本发明的限制。
[0018】参见图 6， 本发明提供了一种 MOSFET结构， 包括： 村底 100; 位于所 述村底 100上方的栅极叠层 600;位于所述栅极叠层 600两侧村底中的源漏区 400; 覆盖所述源漏区的层间介质层 500; 以及位于所述栅极叠层 600下方及 其一侧的村底 100中的半导体层 300， 其中， 构成所述半导体层 300的材料禁 带宽度沿着沟道方向从靠近源端一侧到至靠近漏端一侧逐渐增大。
[0019]半导体沟道区位于村底的表面， 其优选材料为单晶硅或单晶锗合金薄 膜， 其厚度为 5~20nm。 该区域是极轻摻杂甚至未摻杂的。 在摻杂的情况下， 其摻杂类型与源漏区摻杂相反。 [0020】源区和漏区分別位于栅极叠层 600 两侧， 村底上方的半导体层内。 源 区的厚度大于漏区的厚度。 靠近源区一侧的沟道部分厚度大于靠近漏端一侧 的沟道厚度， 为 10nm~60nm。
[0021]所述半导体层 300位于栅极叠层 600下方， 其长度 L小于等于栅极叠 层 600 的宽度。 采用禁带宽度渐变的材料替换原村底材料， 具体的， 采用禁 带宽度较小的硅锗代替原沟道材料硅， 且通过调节硅锗材料中硅锗的比例， 使沟道材料的禁带宽度从源端到漏端逐渐增加， 有效地增大了漏端势垒和源 端势垒之间的高度差， 减小了 DIBL所引起的漏电流。 同时， 由于漏端一侧的 半导体材料禁带宽度大于源端一侧的半导体禁带宽度， 本发明还能有效的抑 制 GIDL效应所引起的漏电流。
[0022】下面结合附图对本发明的制作方法进行详细说明， 包括以下步骤。 需 要说明的是， 本发明各个实施例的附图仅是为了示意的目的， 因此没有必要 按比例绘制。
[0023】参见图 1， 首先提供半导体村底 100， 并在所述村底 100上形成伪栅结 构 200。 所述伪栅结构 200可以是单层的， 也可以是多层的。 伪栅结构 200可 以包括聚合物材料、 非晶硅、 多晶硅或 TiN， 厚度可以为 10nm~200nm。 本 实施例中， 伪栅结构包括多晶硅和二氧化， 具体的， 采用化学汽相淀积的方 法在栅极空位中填充多晶硅， 其高度略低于侧墙 10~20nm， 接着在多晶硅上 方形成一层二氧化硅介质层， 形成方法可以是外延生长、 氧化、 CVD等。 接 着采用常规 CMOS工艺光刻和刻蚀所淀积的伪栅叠层形成栅电极图形。 硅锗 沟道层 101中被栅极介质层所覆盖的部分形成晶体管的沟道区。需说明地是， 举的形成栅介质层相同或类似的方法， 故不再赘述。
[0024】接下来， 在所述半导体结构上形成外延保护层 101， 覆盖所述村底 100 和伪栅叠层 200。外延保护层 101的作用是在后续步骤中进行外延生长时， 保 护漏端一侧的半导体结构上不形成生成物。 具体的， 在本发明中， 所述外延 保护层 101的材料是二氧化硅， 其厚度为 5~20nm。 [0025】接下来， 在栅极堆叠的侧壁上形成牺牲侧墙 102， 用于将栅极隔开。 具 体的， 用 LPCVD淀积 40nm~80nm厚的牺牲侧墙介质层氮化硅， 接着用会客 技术再栅电极两侧形成宽度为 35nm~75nm的氮化硅牺牲侧墙 102。 牺牲侧墙 102 还可以由氧化硅、 氮氧化硅、 碳化硅及其组合， 和 /或其他合适的材料形 成。 牺牲侧墙 102可以具有多层结构。 牺牲侧墙 102还可以通过包括沉积刻 蚀工艺形成， 其厚度范围可以是 10nm -100nm， 如 30nm、 50nm或 80nm。
[0026]上述步骤完成之后的半导体结构剖面图如图 1所示。
[0027]接下来，用掩膜板或光刻胶 206覆盖伪栅叠层 200及其一侧的村底 100， 在村底上形成空位 102， 如图 2所示。 具体的， 在所述半导体结构上覆盖光刻 胶 206， 并通过显影、 曝光等步骤， 去除位于源端一侧半导体结构上的光刻胶 206， 暴露出村底 100。接下来， 对所述半导体结构进刻蚀行以形成空位 102。 所述空位 102位于源端一侧的村底上， 其与伪栅叠层 200重叠的长度 L小于 或等于伪栅叠层宽度。 所述刻蚀方法是各向异性刻蚀和各向同性刻蚀的组合。 在本实施例中， 由于所述空位位于源端一侧的半导体结构中， 因此靠近漏端 的沟道中材料的禁带宽度大于靠近源端的沟道中材料的禁带宽度， 可以有效 地减小 GIDL所引起的漏电流。
[0028]接下来，在所述半导体结构上逐层生长半导体层 300，以填充空位 102， 如图 3所示。 其中， 所述半导体层 300的材料为硅锗， 其禁带宽度从靠近源 端一侧到至靠近漏端一侧逐渐增大， 即硅锗中硅的比例逐渐增大。 具体的， 采用选择性外延的方法， 在所述空位 102 中逐层生长硅锗材料， 由于外延保 护层 101 的存在， 生长的硅锗只存在于空位 102 中而不会在半导体漏区和伪 栅表面进行生长。 可通过调节硅锗材料的层数和比例来控制沟道区材料的禁 带宽度变化， 得到所需要的能带结构。 由于漏端的半导体材料中硅的比例逐 渐增大， 因此所述半导体层 300 的禁带宽度从靠近源端一侧到至靠近漏端一 侧逐渐增大， 有效地增大了漏端势垒和源端势垒之间的高度差， 减小了 DIBL 所引起的漏电流。
[0029]接下来，去除位于所述半导体结构上的外延保护层 101和牺牲侧墙 205， 露出伪栅结构 200， 如图 4所示。接下来， 对伪栅结构 200两侧的村底进行摻 杂， 以形成源漏扩展区， 还可以进行 Halo注入， 以形成 Halo注入区。 其中源 漏扩展区的杂质类型与器件类型一致， Halo注入的杂质类型与器件类型相反。
[0030]可选地，在栅极堆叠的侧壁上形成侧墙 201，用于将栅极隔开。具体的， 用 LPCVD淀积 40nm~80nm厚的牺牲侧墙介质层氮化硅， 接着用会客技术再 栅电极两侧形成宽度为 35nm~75nm的氮化硅侧墙 201。 侧墙 201还可以由氧 化硅、 氮氧化硅、 碳化硅及其组合， 和 /或其他合适的材料形成。 侧墙 201可 以具有多层结构。 侧墙 201 还可以通过包括沉积刻蚀工艺形成， 其厚度范围 可以是 lOnm -lOOnm, 如 30nm、 50nm或 80nm。
[0031】接下来， 在所述半导体结构上淀积一层厚度为 10nm~35nm厚的二氧化 硅介质层， 并以该介质层为緩冲层， 离子注入源漏区。 对 P型晶体而言， 摻 杂剂为硼或弗化硼或铟或镓等。 对 N型晶体而言， 摻杂剂为磷或砷或銻等。 摻杂浓度为 5el019cm-3~lel02G cm-3。 源漏区摻杂完成后， 在所述半导体结构上 形成层间介质层 500。 在本实施例中， 层间介质层 500的材料为二氧化硅。 淀 积完层间介质层 500的半导体结构如图 5所示。
[0032】接下来， 去除所述伪栅结构 200， 形成伪栅空位。 去除伪栅结构 200可 以采用湿刻和 /或干刻除去。 在一个实施例中， 采用等离子体刻蚀。
[0033】接下来， 如图 6所示， 在栅极空位中形成栅极叠层 600。 栅极叠层 600 可以只为金属栅极， 也可以为金属 /多晶硅复合栅极， 其中多晶硅上表面上具 有硅化物。
[0034】具体的， 优选的， 在伪栅空位中栅极介质层 601， 接下来沉积功函数调 节层 602， 之后再在功函数金属层之上形成栅极金属层 603。 所述栅极介质层 601可以是热氧化层，包括氧化硅、氮氧化硅；也可为高 K介质，例如 HfA10N、 HfSiAlON, HfTaAlON, HfTiAlON, HfON、 HfSiON、 HfTaON、 HfTiON、 A1203、 La203、 Zr02、 LaAlO中的一种或其组合， 栅极介质层 601的厚度可以 为 lnm -10nm，例如 3nm、5nm或 8nm。可以采用热氧化、化学气相沉积（CVD) 或原子层沉积 （ALD) 等工艺来形成栅极介质层 601。
[0035]功函数金属层可以采用 TiN、TaN等材料制成，其厚度范围为 3nm~15nm。 金属导体层可以为一层或者多层结构。其材料可以为 TaN、 TaC、 TiN、 TaAlN、 TiAlN、 ΜοΑ1Ν、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax中的一种或其组合。 其厚度范围例如可以为 lOnm -40nm， 如 20nm或 30nm。
[0036】最后进入常规 CMOS厚道工艺， 包括点击钝化层、 开接触孔以及金属 化等， 即可制的所述超薄 SOI MOS晶体管。
[0037】在本发明中， 采用禁带宽度更大的硅锗代替原沟道材料硅， 且通过调 节硅锗材料中硅锗的比例， 使沟道材料的禁带宽度从源端到漏端逐渐下降， 有效地增大了漏端势垒和源端势垒之间的高度差，减小了 DIBL所引起的漏电 流。 同时， 由于所述空位位于源端一侧的半导体结构中， 因此靠近漏端的沟 道中材料的禁带宽度大于靠近源端的沟道中材料的禁带宽度， 可以有效地减 小 GIDL所引起的漏电流。 因此， 通过本发明中的半导体结构， 可以有效的减 小器件漏电流， 优化器件性能。
[0038】 因此， 通过本发明中的半导体结构， 可以有效的减小器件漏电流， 优 化器件性能。
[0039] 虽然关于示例实施例及其优点已经详细说明， 应当理解在不脱离本发 明的精神和所附权利要求限定的保护范围的情况下， 可以对这些实施例进行 各种变化、 替换和修改。 对于其他例子， 本领域的普通技术人员应当容易理 解在保持本发明保护范围内的同时， 工艺步骤的次序可以变化。
[0040]此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作为本 领域的普通技术人员将容易地理解， 对于目前已存在或者以后即将开发出的 工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本发明 描述的对应实施例大体相同的功能或者获得大体相同的结果， 依照本发明可 以对它们进行应用。 因此， 本发明所附权利要求旨在将这些工艺、 机构、 制 造、 物质组成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1、 一种 MOSFET制造方法， 包括：
a.提供村底 （100)、 伪栅叠层 （200)、 外延保护层 （101 ) 以及牺牲侧墙 (205 ) ;
b.用掩膜板覆盖伪栅叠层 （200) 及其一侧的村底 （100)， 在村底上形成 空位 ( 102) ;
c.在所述半导体结构上逐层生长半导体层 （300)， 以填充空位 (102) ; d.去除所述外延保护层 （101 ) 以及牺牲侧墙 （205)， 在所述半导体结构 上依次形成源漏扩展区、 侧墙 （201 )、 源漏区以及层间介质层 （500) ;
e.去除伪栅叠层 （200) 以形成伪栅空位， 在所述伪栅空位中形成栅极叠 层。
2、 根据权利要求 1所述的制造方法， 其特征在于， 优选地， 所述空位（102) 位于源端一侧的村底上。
3、根据权利要求 1或 2所述的制造方法， 其特征在于， 所述形成空位（102) 的方法是各向异性刻蚀与各向同性刻蚀的组合。
4、 根据权利要求 1、 2或 3所述的制造方法， 其特征在于， 所述空位 （102) 与伪栅叠层 （200) 重叠的长度 L小于或等于伪栅叠层宽度。
5、 根据权利要求 1所述的制造方法， 其特征在于， 所述半导体层 （300) 的 禁带宽度从靠近源端一侧到至靠近漏端一侧逐渐增大。
6、根据权利要求 1或 5所述的制造方法， 其特征在于， 所述半导体层（300) 的材料为硅锗。
7、 根据权利要求 6所述的制造方法， 其特征在于， 所述半导体层 （300) 从 靠近源端一侧到至靠近漏端一侧硅锗中硅的比例逐渐增大。
8、 一种 MOSFET结构， 包括：
村底 （100) ;
位于所述村底 （100) 上方的栅极叠层 （600) ;
位于所述栅极叠层 （600) 两侧村底中的源漏区 （400) ; 覆盖所述源漏区的层间介质层 （500) ;
以及位于所述栅极叠层 （600) 下方及其一侧的村底 （100) 中的半导体 层 （300)， 其中， 构成所述半导体层 （300) 的材料禁带宽度沿着沟道方向从 靠近源端一侧到至靠近漏端一侧逐渐增大。
9、根据权利要求 8所述的 MOSFET结构，其特征在于，所述半导体层（300) 位于栅极叠层 （600) 下方的长度 L小于等于栅极叠层 （600) 的宽度。
10、根据权利要求 8所述的 MOSFET结构，其特征在于，所述半导体层（300) 的材料为硅锗。
11、根据权利要求 8所述的 MOSFET结构，其特征在于，所述半导体层（300) 从靠近源端一侧到至靠近漏端一侧硅锗中硅的比例逐渐增大。
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