WO2015054927A1 - 一种mosfet结构及其制造方法 - Google Patents

一种mosfet结构及其制造方法 Download PDF

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Publication number
WO2015054927A1
WO2015054927A1 PCT/CN2013/085622 CN2013085622W WO2015054927A1 WO 2015054927 A1 WO2015054927 A1 WO 2015054927A1 CN 2013085622 W CN2013085622 W CN 2013085622W WO 2015054927 A1 WO2015054927 A1 WO 2015054927A1
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layer
dummy gate
gate
oxide layer
barrier layer
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PCT/CN2013/085622
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English (en)
French (fr)
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李睿
尹海洲
刘云飞
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中国科学院微电子研究所
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Publication of WO2015054927A1 publication Critical patent/WO2015054927A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Definitions

  • the present invention relates to a MOSFET structure and a method of fabricating the same. More specifically, it relates to a MOSFET structure for reducing the number of hot electrons in a channel near a drain terminal and a method of fabricating the same.
  • the channel inversion layer is partially pinched, that is, the channel surface near the drain end has a small carrier concentration, and the resistance is large.
  • the channel region is Most of the voltage falls on the pinch-off region, which generates a large electric field in the pinch-off region.
  • the inversion carrier in the channel region moves to the boundary of the pinch-off region under the action of the electric field, it will be accelerated by the electric field in the pinch-off region, and will be quickly swept to the drain. In this process, the electrons will be very The large velocity is much larger than the velocity of movement in the anti-carrier region. Therefore, the velocity of electron movement in the pinch-off region is independent of the mobility, and mainly depends on the voltage on the pinch-off region.
  • the present invention provides a method for reducing the probability of hot carrier transition, specifically, replacing the channel material near the drain end with indium phosphide and/or indium arsenide.
  • a hot carrier transition barrier layer the material of which has a higher electron affinity than the original channel material, increases the barrier height between the pinch-off region and the gate dielectric layer, and increases the hot carrier transition required The energy, thereby reducing the number and probability of hot carriers entering the gate dielectric layer.
  • the present invention provides a MOSFET structure for reducing the number of hot electrons in a channel near a drain terminal and a method of fabricating the same, which effectively reduces the number and probability of hot carriers entering the gate dielectric layer, and improves the number of Device performance.
  • the manufacturing method provided by the present invention includes the following steps:
  • the vacancy is located on the surface of the village floor, the depth is less than 2 nm, and the length is less than 1/3 of the length of the gate.
  • the element forming the transition barrier layer is indium indium and/or indium arsenide.
  • the present invention also provides a semiconductor structure, including:
  • Source and drain regions located in the bottom of both sides of the gate stack
  • transition barrier layer is located on the surface of the substrate, the depth is less than 2 nm, and the length is less than 1/3 of the length of the gate.
  • the element forming the transition barrier layer is indium phosphide and/or indium arsenide.
  • a method for reducing the probability of hot carrier transitions provided by the present invention, specifically Indium phosphide and/or indium arsenide replaces the channel material near the drain end side to form a hot carrier transition barrier layer, and the material of the barrier layer has an electron affinity greater than that of the original channel material, effectively increasing The barrier height between the pinch-off region and the gate dielectric layer increases the energy required for hot carrier transitions, thereby reducing the number and probability of hot carriers entering the gate dielectric layer, optimizing device performance.
  • FIG. 1 through 7 schematically illustrate cross-sectional views of semiconductor structures at various stages of forming a fabrication method in accordance with the present invention.
  • the present invention provides an asymmetric MOSFET structure, comprising: a substrate 100; a gate stack 500 located above the substrate 100; and a substrate on both sides of the gate stack 500.
  • the transition blocking layer 400 is located on the surface of the semiconductor structure 100, the depth is less than 2 nm, and the length is less than 1/3 of the gate length, wherein the element forming the transition blocking layer 400 is indium phosphide and/or arsenic. indium.
  • the material of the barrier layer has greater electron affinity than the original channel material, effectively increasing the barrier height between the pinch-off region and the gate dielectric layer, and increasing the energy required for the hot carrier transition. The number and probability of hot carriers entering the gate dielectric layer are reduced, optimizing device performance.
  • the gate structure includes a gate dielectric layer, a work function adjustment layer, and a gate metal layer.
  • the gate dielectric layer is preferably made of silicon oxynitride or silicon oxide or a high K material. Its equivalent oxidation thickness is from 0.5 nm to 5 nm.
  • the gate metal layer may be only a metal gate or a metal/polysilicon composite gate, wherein the polysilicon There is silicide on the upper surface.
  • the semiconductor channel region is located on the surface of the substrate 100.
  • the preferred material is a single crystal silicon or a single crystal germanium alloy film having a thickness of 2 to 20 nm. This region is extremely lightly doped or even undoped. In the case of doping, the doping type is opposite to that of the source and drain regions.
  • the source and drain regions are respectively located on both sides of the gate stack, within the village substrate 100.
  • the source region is symmetrical with the drain region, and its doping type is opposite to that of the village.
  • the gate dielectric layer 103 may be a thermal oxide layer, including silicon oxide or silicon oxynitride; or a high-k dielectric such as HfA10N, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, A1 2 0 3 ,
  • the gate dielectric layer 301 may have a thickness of 1 nm to 10 nm, for example, 3 nm, 5 nm or 8 nm, of one or a combination of La 2 O 3 , Zr0 2 , and LaAlO.
  • the gate dielectric layer can be formed by processes such as thermal oxidation, chemical vapor deposition (CVD), or atomic layer deposition (ALD).
  • a dummy gate structure 150 is formed on the gate dielectric layer.
  • the dummy gate structure 150 may be a single layer or a plurality of layers.
  • the dummy gate structure 150 may comprise a polymer material, amorphous silicon, polysilicon or TiN, and may have a thickness of 10 nm to 200 nm.
  • the dummy gate structure includes polysilicon and dioxide.
  • a chemical vapor deposition method is used to fill the gate vacancies with polysilicon, and then a silicon dioxide dielectric layer is formed over the polysilicon.
  • the formation method may be Epitaxial growth, oxidation, CVD, and the like.
  • the gate electrode pattern is formed by photolithography and etching of the deposited dummy gate stack by a conventional CMOS process, and then the exposed portion of the gate dielectric layer 103 is etched away by using the gate electrode pattern as a mask. It should be noted that, unless otherwise specified, the deposition of various dielectric materials in the embodiments of the present invention may employ the same or similar methods of forming the gate dielectric layer as described above, and thus will not be described again.
  • the substrate 100 on both sides of the dummy gate structure is shallowly doped to form a lightly doped source and drain region, and Halo implantation may also be performed to form a Halo implant region.
  • the type of shallow doping impurity is the same as the type of device, and the type of impurity implanted by Halo is opposite to the device type.
  • sidewall spacers 150 are formed on sidewalls of the gate stack for spacing the gates. specific, A 40 nm to 80 nm thick sacrificial sidewall dielectric layer of silicon nitride is deposited by LPCVD, and then a silicon nitride spacer 150 having a width of 35 nm to 75 nm is formed on both sides of the gate electrode by a guest technique. Sidewall 150 may also be formed from silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials. The side wall 150 may have a multi-layered structure. The sidewall spacer 150 may also be formed by a deposition etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm, or 80 nm.
  • a silicon dioxide dielectric layer having a thickness of 10 nm to 35 nm is deposited on the semiconductor structure to form an interlayer dielectric layer 300, and the dielectric layer is used as a buffer layer, and the ion implantation source and drain are formed.
  • Area For the P-type crystal, the dopant is boron or boron fluoride or indium or gallium.
  • the dopant is phosphorus or arsenic or antimony.
  • the doping concentration is 5el0 19 cm_ 3 ⁇ lel0 2() cm_ 3 .
  • the semiconductor structure after doping is completed as shown in FIG.
  • the dummy gate structure is removed to form dummy gate vacancies, as shown in FIG.
  • the removal of the dummy gate structure can be removed by wet etching and/or dry etching. In one embodiment, plasma etching is employed.
  • the oxygen growth method formed on the semiconductor substrate 100 in the dummy gate vacancies may be dry oxygen oxidation, and the generated oxide layer 350 has a thickness of 5 to 15 nm.
  • the semiconductor on the source side and the dummy gate vacancy near the source side are covered with a photoresist to expose the oxide layer 350 near the drain end side.
  • the semiconductor is anisotropically etched to form a vacancy 450 on the oxide layer 350 not covered by the photoresist and the substrate 100 below it, the length of which does not exceed 1/3 of the gate length. .
  • the thickness of the epitaxial layer in order to ensure that the material constituting the channel has a high quality lattice structure, we need the thickness of the epitaxial layer to be smaller than the relaxation of the film and the critical thickness before the defect is introduced.
  • the portion of the vacancy in the bottom of the village is no more than 2 nm deep, that is, less than the critical thickness of epitaxial growth of the epitaxially grown thin film of indium arsenide and/or indium arsenide on silicon.
  • the photoresist is removed, and indium phosphide and/or indium arsenide are selectively grown on the semiconductor structure to fill the vacancy 450 to form a transition barrier layer 400, the surface of the transition barrier layer 450 and the oxide layer. 350 flush.
  • the transition barrier layer 400 is grown by atomic layer deposition.
  • the semiconductor structure is anisotropically etched to remove the oxide layer 350 and The upper half of the transition barrier layer 400, which is flush with the oxide layer 350, causes the surface of the transition barrier layer to be flush with the surface of the semiconductor substrate 100.
  • the semiconductor material forming the transition barrier layer 400 has a greater electron affinity than the substrate material, that is, the barrier height between the transition barrier layer 400 and the gate dielectric layer is greater than other portions of the channel, hot carriers. More energy is required to cross the barrier into the gate dielectric layer, effectively reducing the number of hot carriers that transition into the gate dielectric layer and improving device performance.
  • the gate metal layer may be only a metal gate or a metal/polysilicon composite gate, wherein the polysilicon has a silicide on its upper surface.
  • a work function metal layer is deposited on the gate dielectric layer, and then a metal conductor layer is formed on the work function metal layer.
  • the work function metal layer can be made of a material such as TiN or TaN, and has a thickness ranging from 3 nm to 15 nm.
  • the metal conductor layer may be in a one-layer or multi-layer structure.
  • the material may be one of TaN, TaC, TiN, TaAlN, TiAlN, ⁇ 1 ⁇ , TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x or a combination thereof.
  • the thickness may range, for example, from 10 nm to 40 nm, such as 20 nm or 30 nm.

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Abstract

本发明提供了一种 MOSFET制造方法，包括：a.提供衬底、源漏区、伪栅叠层、层间介质层和侧墙；b.去除伪栅叠层形成伪栅空位，并在伪栅空位中的衬底上形成氧化层；c.在所述半导体结构漏端一侧覆盖光刻胶，露出伪栅空位中靠近源端的氧化层；d.对未被光刻胶覆盖的衬底及氧化层进行各向异性刻蚀，形成空位；e.去除光刻胶，在所述空位中淀积跃迁阻挡层，直至所述跃迁阻挡层与氧化层平齐；f.对所述半导体结构进行刻蚀，去除氧化层以露出沟道表面；g.在所述伪栅空位中淀积栅极叠层。根据本发明提供的方法，有效抑制了热载流子效应优化了器件性能。

Description

一种 MOSFET结构及其制造方法
[0001]本申请要求了 2013年 10月 15 日提交的、 申请号为 201310480377.7、 发明名称为 "一种 MOSFET 结构及其制造方法" 的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
[0002】本发明涉及一种 MOSFET结构及其制造方法。 更具体而言， 涉及一种 用于减小靠近漏端的沟道中热电子数目的 MOSFET结构及其制造方法。 技术背景
[0003】 MOSFET 处于饱和区时， 沟道反型层部分夹断， 即靠近漏端的沟道表 面反型载流子浓度很小， 电阻很大， 根据串联分压关系， 此时沟道区的电压 大部分落在夹断区上， 在夹断区产生很大的电场。 当沟道区的反型载流子在 电场作用下运动到夹断区边界时， 将会被夹断区的电场加速， 很快的被扫到 漏端， 这一过程中电子将会获得很大的速度， 远大于在反型载流子区时运动 的速度， 因此， 在夹断区电子的运动速度与迁移率无关， 主要取决于夹断区 上的电压大小。
[0004】随着源漏之间电压的增大， 夹断区载流子所处的电场也随着增大， 因 此电子能获得更高的速度和更大的能量， 产生一定数目的热载流子， 夹断区 的电场增大到一定程度时， 这些热载流子具有一定的几率越过沟道和栅介质 层之间的势垒， 进入栅介质层中， 从而在栅介质层中引入缺陷和陷阱， 影响 器件性能。
[0005】针对这一问题， 本发明提供了一种减小热载流子跃迁几率的方法， 具 体的， 采用磷化铟和 /或砷化铟替换靠近漏端一侧的沟道材料， 形成热载流子 跃迁阻挡层， 该阻挡层的材料的电子亲和能大于原沟道材料， 增大夹断区与 栅极介质层之间的势垒高度， 增大热载流子跃迁所需的能量， 从而减小热载 流子进入栅极介质层的数目和几率。 发明内容
[0006]本发明提供了一种用于减小靠近漏端的沟道中热电子数目的 MOSFET 结构及其制造方法， 有效地减小了热载流子进入栅极介质层的数目和几率， 提高了器件性能。 具体地， 本发明提供的制造方法包括以下步骤：
a) 提供村底、 源漏区、 伪栅叠层、 层间介质层和侧墙；
b) 去除伪栅叠层形成伪栅空位， 并在伪栅空位中的村底上形成氧化层； c) 在所述半导体结构漏端一侧覆盖光刻胶， 露出伪栅空位中靠近源端的 氧化层；
d) 对未被光刻胶覆盖的村底及氧化层进行各向异性刻蚀， 形成空位； e) 去除光刻胶， 在所述空位中淀积跃迁阻挡层， 直至所述跃迁阻挡层与 氧化层平齐；
f) 对所述半导体结构进行刻蚀， 去除氧化层以露出沟道表面；
g) 在所述伪栅空位中淀积栅极叠层。
[0007】其中， 所述空位位于村底表面， 其深度小于 2nm， 长度小于栅极长度 的 1/3。
[0008]其中， 形成跃迁阻挡层的元素为鱗化铟和 /或砷化铟。
[0009】相应的， 本发明还提供了一种半导体结构， 包括：
村底；
位于所述村底上方的栅极叠层；
位于所述栅极叠层两侧村底中的源漏区；
位于所述栅极叠层两侧的侧墙；
位于所述侧墙两侧的层间介质层；
以及位于栅极下方靠近漏端一侧村底中的跃迁阻挡层。
[0010】其中， 所述跃迁阻挡层位于村底表面， 其深度小于 2nm， 长度小于栅 极长度的 1/3。
[0011]其中， 形成跃迁阻挡层的元素为磷化铟和 /或砷化铟。
[0012】根据本发明提供的一种减小热载流子跃迁几率的方法， 具体的， 采用 磷化铟和 /或砷化铟替换靠近漏端一侧的沟道材料，形成热载流子跃迁阻挡层， 该阻挡层的材料的电子亲和能大于原沟道材料， 有效的增大了夹断区与栅极 介质层之间的势垒高度， 增大了热载流子跃迁所需的能量， 从而减小热载流 子进入栅极介质层的数目和几率， 优化了器件性能。 附图说明
[0013]图 1至图 7示意性地示出了形成根据本发明的制造方法各阶段半导体 结构的剖面图。
具体实施方式
[0014】为使本发明的目的、 技术方案和优点更加清楚， 下面将结合附图对本 发明的实施例作详细描述。
[0015】下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其 的元件。 下面通过参考附图描述的实施例是示例性的， 仅用于解释本发明， 而不能解释为对本发明的限制。
[0016】参见图 7， 本发明提供了一种非对称 MOSFET结构， 包括： 村底 100 ; 位于所述村底 100上方的栅极叠层 500 ;位于所述栅极叠层 500两侧村底中的 源漏区 200 ; 位于所述栅极叠层 500两侧的侧墙 160 ; 位于所述侧墙 160两侧 的层间介质层 300 ;以及位于栅极下方靠近漏端一侧村底中的跃迁阻挡层 400。
[0017]其中，所述跃迁阻挡层 400位于半导体结构 100表面，其深度小于 2nm， 长度小于栅极长度的 1/3， 其中， 形成跃迁阻挡层 400的元素为磷化铟和 /或砷 化铟。 该阻挡层的材料的电子亲和能大于原沟道材料， 有效的增大了夹断区 与栅极介质层之间的势垒高度， 增大了热载流子跃迁所需的能量， 从而减小 热载流子进入栅极介质层的数目和几率， 优化了器件性能。
[0018】栅结构包括栅极介质层、 功函数调节层和栅极金属层。 栅介质层优选 材料为氮氧化硅，也可为氧化硅或高 K材料。其等效氧化厚度为 0.5nm~5nm。 栅极金属层可以只为金属栅极， 也可以为金属 /多晶硅复合栅极， 其中多晶硅 上表面上具有硅化物。
[0019】半导体沟道区位于村底 100 的表面， 其优选材料为单晶硅或单晶锗合 金薄膜， 其厚度为 2~20nm。 该区域是极轻摻杂甚至未摻杂的。 在摻杂的情况 下， 其摻杂类型与源漏区摻杂相反。
[0020]源区和漏区分別位于栅极叠层两侧，村底 100内。源区与漏区相对称， 其摻杂类型与村底相反。
[0021】下面结合附图对本发明的制作方法进行详细说明， 包括以下步骤。 需 要说明的是， 本发明各个实施例的附图仅是为了示意的目的， 因此没有必要 按比例绘制。
[0022]首先提供村底， 并在所述村底上形成栅极介质层。 所述栅极介质层 103 可以是热氧化层， 包括氧化硅、 氮氧化硅； 也可为高 K介质， 例如 HfA10N、 HfSiAlON, HfTaAlON, HfTiAlON, HfON、 HfSiON、 HfTaON、 HfTiON、 A1203、 La203、 Zr02、 LaAlO 中的一种或其组合， 栅极介质层 301 的厚度可 以为 lnm -10nm， 例如 3nm、 5nm或 8nm。 可以采用热氧化、 化学气相沉积 (CVD) 或原子层沉积 （ALD) 等工艺来形成栅极介质层。
[0023]接下来， 在所述栅极介质层上形成伪栅结构 150。所述伪栅结构 150可 以是单层的， 也可以是多层的。伪栅结构 150可以包括聚合物材料、非晶硅、 多晶硅或 TiN， 厚度可以为 10nm~200nm。 本实施例中， 伪栅结构包括多晶 硅和二氧化， 具体的， 采用化学汽相淀积的方法在栅极空位中填充多晶硅， 接着在多晶硅上方形成一层二氧化硅介质层， 形成方法可以是外延生长、 氧 化、 CVD等。接着采用常规 CMOS工艺光刻和刻蚀所淀积的伪栅叠层形成栅 电极图形， 然后以栅电极图形为掩膜腐蚀掉栅极介质层 103 的棵露部分。 需 说明地是， 以下若无特別说明， 本发明实施例中各种介质材料的淀积均可采 用上述所列举的形成栅介质层相同或类似的方法， 故不再赘述。
[0024】接下来， 对伪栅结构两侧的村底 100进行浅摻杂， 以形成轻摻杂源漏 区， 还可以进行 Halo注入， 以形成 Halo注入区。其中浅摻杂的杂质类型与器 件类型一致， Halo注入的杂质类型与器件类型相反。
[0025]可选地，在栅极堆叠的侧壁上形成侧墙 150，用于将栅极隔开。具体的， 用 LPCVD淀积 40nm~80nm厚的牺牲侧墙介质层氮化硅， 接着用会客技术再 栅电极两侧形成宽度为 35nm~75nm的氮化硅侧墙 150。 侧墙 150还可以由氧 化硅、 氮氧化硅、 碳化硅及其组合， 和 /或其他合适的材料形成。 侧墙 150可 以具有多层结构。 侧墙 150还可以通过包括沉积刻蚀工艺形成， 其厚度范围 可以是 lOnm -lOOnm, 如 30nm、 50nm或 80nm。
[0026】接下来， 在所述半导体结构上淀积一层厚度为 10nm~35nm厚的二氧化 硅介质层， 形成层间介质层 300， 并以该介质层为緩冲层， 离子注入源漏区。 对 P型晶体而言， 摻杂剂为硼或氟化硼或铟或镓等。 对 N型晶体而言， 摻杂 剂为磷或砷或銻等。摻杂浓度为 5el019cm_3~lel02() cm_3。 完成摻杂之后的半导 体结构如图 1所示。
[002 接下来， 去除所述伪栅结构， 形成伪栅空位， 如图 2 所示。 去除伪栅 结构可以采用湿刻和 /或干刻除去。 在一个实施例中， 采用等离子体刻蚀。
[0028】接下来， 如图 3所示， 在所述伪栅空位中的半导体村底 100上形成氧 生长方法可以采用干氧氧化， 生成的氧化层 350厚度为 5~15nm。
[0029】接下来， 如图 4 所示， 用光刻胶覆盖源端一侧的半导体以及靠近源端 一侧的伪栅空位， 露出靠近漏端一侧的氧化层 350。接下来， 对所述半导体进 行各向异性刻蚀刻蚀， 在未被光刻胶覆盖的氧化层 350和其下方的村底 100 上形成空位 450， 其的长度不超过栅极长度的 1/3。 考虑到异质外延生长会在 界面处引入缺陷， 为了保证构成沟道的材料具有高质量的晶格结构， 我们需 要在外延层的厚度小于薄膜发生弛豫， 引入缺陷之前的临界厚度， 因此， 所 述空位位于村底中的部分深度不超过 2nm， 即小于鱗化铟和 /或砷化铟在硅上 外延生长薄膜弛豫的临界厚度。
[0030】接下来， 去除光刻胶， 在所述半导体结构上选择项生长磷化铟和 /或砷 化铟以填充空位 450， 形成跃迁阻挡层 400， 所述跃迁阻挡层 450表面与氧化 层 350平齐。 为了保证薄膜质量， 在本实施例中， 优选的， 采用原子层淀积 法生长跃迁阻挡层 400。
[0031】接下来， 对所述半导体结构进行各向异性刻蚀， 去除氧化层 350 以及 与氧化层 350平齐的跃迁阻挡层 400的上半部分， 使得跃迁阻挡层的表面与 半导体村底 100表面平齐。 形成跃迁阻挡层 400的半导体材料具有比村底材 料更大的电子亲和能， 也就是说， 跃迁阻挡层 400 与栅极介质层之间的势垒 高度大于沟道其他部分， 热载流子需要更大的能量才能越过势垒进入栅介质 层中， 有效减小了跃迁进入栅介质层中的热载流子数目， 提高了器件性能。
[0032】接下来， 在栅极空位中依次形成栅极介质层、 功函数调节层和栅极金 属层。 栅极金属层可以只为金属栅极， 也可以为金属 /多晶硅复合栅极， 其中 多晶硅上表面上具有硅化物。 具体的如图 7所示， 优选的， 在栅极介质层上 先沉积功函数金属层， 之后再在功函数金属层之上形成金属导体层。 功函数 金属层可以采用 TiN、 TaN等材料制成， 其厚度范围为 3nm~15nm。 金属导体 层可以为一层或者多层结构。其材料可以为 TaN、 TaC、 TiN、 TaAlN、 TiAlN、 ΜοΑ1Ν、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax中 的一种或其组合。 其厚度范围例如可以为 10nm -40nm， 如 20nm或 30nm。
[0033]虽然关于示例实施例及其优点已经详细说明， 应当理解在不脱离本发 明的精神和所附权利要求限定的保护范围的情况下， 可以对这些实施例进行 各种变化、 替换和修改。 对于其他例子， 本领域的普通技术人员应当容易理 解在保持本发明保护范围内的同时， 工艺步骤的次序可以变化。
[0034]此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作为本 领域的普通技术人员将容易地理解， 对于目前已存在或者以后即将开发出的 工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本发明 描述的对应实施例大体相同的功能或者获得大体相同的结果， 依照本发明可 以对它们进行应用。 因此， 本发明所附权利要求旨在将这些工艺、 机构、 制 造、 物质组成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1、 一种 MOSFET制造方法， 包括：
a.提供村底 （100)、 源漏区 （200)、 伪栅叠层 （150)、 层间介质层 （300) 和侧墙 （160) ;
b.去除伪栅叠层 （150) 形成伪栅空位， 并在伪栅空位中的村底上形成氧 化层 （350) ;
c.在所述半导体结构漏端一侧覆盖光刻胶，露出伪栅空位中靠近源端的氧 化层 （350) ;
d.对未被光刻胶覆盖的村底 （100) 及氧化层 （350) 进行各向异性刻蚀， 形成空位 （450) ;
e.去除光刻胶， 在所述空位 （450) 中淀积跃迁阻挡层 （400)， 直至所述 跃迁阻挡层 （400) 与氧化层平齐；
f.对所述半导体结构进行刻蚀， 去除氧化层 （350) 以露出沟道表面； g.在所述伪栅空位中淀积栅极叠层 （500)。
2、 根据权利要求 1所述的制造方法， 其特征在于， 所述空位 （450) 位于村 底 （100) 表面， 其深度小于 2nm， 长度小于栅极长度的 1/3。
3、 根据权利要求 1所述的制造方法， 其特征在于， 形成跃迁阻挡层 （400) 的元素为碌化铟和 /或砷化铟。
4、 一种半导体结构， 包括：
村底 （100) ;
位于所述村底 （100) 上方的栅极叠层 （500) ;
位于所述栅极叠层 （500) 两侧村底中的源漏区 （200) ;
位于所述栅极叠层 （500) 两侧的侧墙 （160) ;
位于所述侧墙 （160) 两侧的层间介质层 （300) ;
以及位于栅极下方靠近漏端一侧村底中的跃迁阻挡层 （400)。
5、 根据权利要求 4所述的半导体结构， 其特征在于， 所述跃迁阻挡层 （400) 位于村底 （100) 表面， 其深度小于 2nm， 长度小于栅极长度的 1/3。
6、 根据权利要求 4所述的半导体结构， 其特征在于， 跃迁阻挡层 （400) 的 材料为碌化铟和 /或砷化铟。
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