WO2014079296A1 - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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WO2014079296A1
WO2014079296A1 PCT/CN2013/085532 CN2013085532W WO2014079296A1 WO 2014079296 A1 WO2014079296 A1 WO 2014079296A1 CN 2013085532 W CN2013085532 W CN 2013085532W WO 2014079296 A1 WO2014079296 A1 WO 2014079296A1
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layer
polycrystalline
soi substrate
source
gate stack
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PCT/CN2013/085532
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French (fr)
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尹海洲
朱慧珑
骆志炯
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中国科学院微电子研究所
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Publication of WO2014079296A1 publication Critical patent/WO2014079296A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure

Definitions

  • the present invention relates to the field of semiconductor fabrication, and more particularly to a semiconductor structure and a method of fabricating the same. Background technique
  • CMOS devices fabricated using silicon-on-insulator have many advantages such as high speed, low power consumption, high integration, anti-irradiation and no self-locking effects, and have become the preferred structure for deep sub-micron and nano-scale MOS devices. .
  • SOI structure of ultra-thin silicon film ⁇ 100nm is often required to make the device channel fully depleted.
  • the CMOS circuit fabricated with this ultra-thin SOI (UTSOI) structure can improve DIBL ( Drain Induced Barrier Lowering, such as short channel effects, improved subthreshold characteristics of the device, reduced static power consumption of the circuit, and elimination of the kink effect.
  • DIBL Drain Induced Barrier Lowering, such as short channel effects, improved subthreshold characteristics of the device, reduced static power consumption of the circuit, and elimination of the kink effect.
  • the metal silicide may consume the entire silicon film, but it is still difficult to reduce.
  • the source/drain region has a series resistance and contact resistance, and may also cause a large leakage current.
  • RSD Raised Source/Drain
  • the contact resistance of the source/drain regions can be further reduced, the drive current of the device can be increased, and the device performance can be improved.
  • a commonly used method for forming a source/drain is selective epitaxial monocrystalline silicon, germanium, etc., and the process temperature is generally above 650 ° C.
  • the formed source/drain extension region and channel are easily formed.
  • Doped region The redistribution of dopants may cause problems such as a threshold voltage being too low, or a channel through-short. Reducing the process temperature of the source/drain and reducing its influence on the doping profile is an important challenge to improve the source/drain technology. Summary of the invention
  • the present invention is directed to at least solving the above technical deficiencies, and provides a method for fabricating a semiconductor device and a structure thereof, which can reduce the process temperature for increasing source/drain growth, reduce the influence on the doping profile of the semiconductor structure, and improve the semiconductor device. Performance and reliability.
  • the present invention provides a method of fabricating a semiconductor structure, the method comprising the steps of:
  • step (a) wherein, before or after forming the sidewall in step (a), the method further comprises the steps of:
  • a source/drain extension region is formed.
  • Another aspect of the invention also provides a semiconductor structure including an SOI substrate, a gate stack, sidewall spacers, and source/drain regions, wherein:
  • the SOI substrate includes a substrate layer, an insulating layer over the substrate layer, and a device layer over the insulating layer;
  • the gate stack is located above the SOI substrate
  • the sidewall is located on a sidewall of the gate stack
  • the source/drain regions are formed over the SOI substrate on both sides of the gate stack, and the material thereof is polycrystalline Sii_ x Ge x .
  • the source/drain regions can be formed at a lower temperature, the influence on the doping profile of the semiconductor structure is reduced, and the series resistance of the source/drain regions is reduced. And contact resistance, to avoid problems such as threshold voltage drop, channel punch-through short circuit, etc., to improve the performance and reliability of semiconductor devices.
  • FIG. 1 is a flow chart of one embodiment of a method of fabricating a semiconductor structure in accordance with the present invention
  • FIG. 2 to FIG. 8 are schematic cross-sectional views of the semiconductor structure at various stages of fabrication in the process of fabricating a semiconductor structure in accordance with the method illustrated in FIG. 1. detailed description
  • the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials.
  • the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. The embodiment, such that the first and second features may not be in direct contact.
  • FIGS. 2 through 8 are cross-sectional views showing stages of fabricating a semiconductor structure in accordance with the flow of FIG. 1 in accordance with an embodiment of the present invention.
  • the method of forming the semiconductor structure of FIG. 1 will be specifically described below with reference to FIGS. 2 through 8.
  • the drawings of the embodiments of the present invention are intended to be illustrative only, and are not necessarily to scale.
  • step S101 an SOI substrate 100 is provided, a gate stack is formed on the SOI substrate 100, and sidewall spacers 230 are formed on sidewalls of the gate stack.
  • the SOI substrate 100 includes a base layer 101, an insulating layer 102 over the base layer 101, and a device layer 103 over the insulating layer 102.
  • the base layer 101 is single crystal silicon.
  • the base layer 101 may also include other basic semiconductors such as germanium, or other compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide or indium phosphide.
  • the thickness of the base layer 101 can be, but is not limited to, a few hundred meters, such as a thickness ranging from 0.2 mm to 1 mm.
  • the insulating layer 102 may be SiO 2 , silicon nitride, Al 2 0 3 or any other suitable insulating material. Typically, the insulating layer 102 has a thickness ranging from 10 nm to 300 nm.
  • the device layer 103 may be any one of the semiconductors included in the base layer 101.
  • the device layer 103 is monocrystalline silicon.
  • the device layer 103 may also include other base semiconductors or compound semiconductors.
  • the thickness of the device layer 103 ranges from 10 nm to 100 nm.
  • the SOI substrate 100 is an ultra-thin SOI (Utho-Sin SOI) substrate having an extremely thin device layer, and the thickness is usually less than 10 nm, which is advantageous for controlling the source/drain region depth and forming an ultra-thin Shallow junctions, thereby reducing short channel effects.
  • Utho-Sin SOI ultra-thin SOI
  • an isolation region such as a shallow trench isolation (STI) structure 120, is formed in the SOI substrate 100 to electrically isolate the continuous semiconductor device.
  • STI shallow trench isolation
  • the gate stack is formed over the SOI substrate 100 and includes a gate dielectric layer 210 and a gate 220, as shown in FIG.
  • the gate stack may further include a capping layer (not shown) over the gate, such as by depositing silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof. Formed to protect the top region of the gate 220 from damage during subsequent processing.
  • the gate dielectric layer 210 is located on the SOI substrate 100 and may be a high K dielectric, for example, Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO. One or a combination thereof. In another embodiment, it may also be a thermal oxide layer including silicon oxide or silicon oxynitride; the gate dielectric layer 210 may have a thickness of 1 nm to 10 nm, such as 5 nm or 8 nm.
  • the pole 220 may be a heavily doped polysilicon formed by deposition, or a shape success function metal layer (for NMOS, such as TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x, etc., for PMOS, such as MoN x , TiSiN, TiCN, TaAlC, TiAIN, TaN, PtSi x , Ni 3 Si, Pt, Ru, Ir, Mo, HfRu, RuO x ), the thickness may be from 1 nm to 20 nm For example, 3 nm, 5 nm, 8 nm, 10 nm, 12 nm or 15 nm, a heavily doped polysilicon, Ti, Co, Ni, Al, W or alloy thereof is formed on the work function metal layer to form a gate electrode 220.
  • NMOS such as TaC, TiN, TaTbN, Ta
  • the sidewall spacers 230 are formed on sidewalls of the gate stack for spacing the gate stacks apart.
  • Sidewall 230 can be formed from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
  • the side wall 230 may have a multi-layered structure.
  • the sidewall spacer 230 may be formed by a deposition-etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm or 80 nm.
  • step S101 further comprising forming a source/drain extension region 300 after forming the gate stack or after forming the sidewall spacer 230.
  • a shallow source/drain extension 300 can be formed in the substrate 100 by low energy implantation, and P-type or N-type dopants or impurities can be implanted into the substrate 100, for example, for PMOS, source/drain extension Region 300 can be P-doped Si; for NMOS, source/drain extension 300 can be N-doped Si.
  • the semiconductor structure is subsequently annealed to activate doping in the source/drain extension 300, and the annealing may be formed by other suitable methods including rapid annealing, spike annealing, and the like.
  • the annealing operation may also be performed after forming the source/drain regions. Since the thickness of the source/drain extension region 300 is shallow, the short channel effect can be effectively suppressed.
  • FIG. 5 is a cross-sectional view showing the structure after the gate stack is formed by implanting the gate stack as a mask to form the source/drain extension region 300
  • FIG. 6 is a view showing the formation of the gate stack. After the side wall 230, a structural cross-sectional view of the source/drain extension region 300 is formed.
  • step S102 is performed to form a polycrystalline 81 1 ⁇ 3 ⁇ 4 ⁇ layer 310 on the SOI substrate 100.
  • the method of forming the polycrystalline 81 1 ⁇ 3 ⁇ 4 ⁇ layer 310 includes plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), by gas flow rate, gas pressure , equipment power, etc. are adjusted,
  • PECVD plasma enhanced chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • RTCVD rapid thermal chemical vapor deposition
  • the process temperature for forming the polycrystalline 81 1 ⁇ 3 ⁇ 4 ⁇ ⁇ layer 310 can be controlled to be below 450 ° C, and the typical process temperature is 425 ° C, 400 ° C.
  • the method of chemical vapor deposition to form a polycrystalline Sii_ x Ge x layer has less influence on the existing doping distribution of the semiconductor structure, which is beneficial to improve The performance and reliability of semiconductor devices.
  • the reaction gas for forming polycrystalline Si 1-x Ge x y3 ⁇ 4 310 is SiH 4 , GeH 4 , and the composition ratio of Si and Ge in Sii_ x Ge x is adjusted by controlling the gas flow rate or gas percentage of Si 3 ⁇ 4 or GeH 4 .
  • the value of X is 0.2 to 0.7.
  • the thickness of the polycrystalline Si ⁇ Ge x layer 310 is not larger than the height of the gate stack having a thickness in the range of 50nm ⁇ 200nm.
  • the doping of the polycrystalline 81 1 _ ⁇ ⁇ 6 ⁇ ⁇ layer 310 is achieved by performing in-situ doping while forming the polycrystalline 81 1 _ ⁇ ⁇ 6 ⁇ ⁇ layer 310;
  • ion implantation may be performed after the formation of the polycrystalline 81 1 _ ⁇ ⁇ 6 ⁇ ⁇ layer 310 to achieve doping of the polycrystalline 8 ⁇ 6 layer 310.
  • the doping concentration of the polycrystalline Sii_ x Ge x is 10 18 ⁇ 2 ⁇ 10 20 cm" 3
  • the doping type of the Si 1-x Ge x layer is N type
  • the doping type of the layer is P type.
  • step S103 annealing is performed, and the polycrystal is patterned.
  • step S102 the 81 1 ⁇ 3 ⁇ 4 ⁇ layer formed by plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), or the like may be amorphous.
  • PECVD plasma enhanced chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • RTCVD rapid thermal chemical vapor deposition
  • the crystal structure is restored by annealing, and defects are eliminated, thereby obtaining a polycrystalline Sii_ x Ge x layer.
  • the donor and acceptor impurities are activated by annealing.
  • the polycrystalline 81 1 _ ⁇ ⁇ 6 ⁇ ⁇ layer is patterned by a dry etching RIE or the like, and a source/drain region 310 is formed on the etched Sii_ x Ge x layer.
  • the present invention also provides a semiconductor structure, as shown in FIG. 8, the semiconductor structure package
  • the SOI substrate 100, the gate stack, the sidewall spacers 230, and the source/drain regions 310 are included.
  • the SOI substrate 100 includes a base layer 101, an insulating layer 102 over the base layer 101, and a device layer 103 over the insulating layer 102; the gate stack is located on the SOI substrate 100.
  • the sidewall spacers 230 are located on the sidewalls of the gate stack; the source/drain regions 310 are formed on the SOI substrate 100 on both sides of the gate stack, and the material thereof is Polycrystalline Si 1-x Ge x .
  • the polycrystalline Si 1-x Ge x source/drain regions have a thickness of 50 nm to 200 nm, and x has a value of 0.2 to 0.7.
  • the polycrystalline Si 1-x Ge ⁇ doping concentration is 10 18 ⁇ 2xl 2 2 cm - 3 , and for the NMOS, the doping type of the polycrystalline 81 1 _ ⁇ ⁇ 6 ⁇ ⁇ layer is N type;
  • the doping type of the polycrystalline Sii_ x Ge x layer is P type.
  • the source/drain region 310 is a raised source/drain structure, that is, the top of the source/drain region 310 is higher than the bottom of the gate stack, which is advantageous for reducing the series resistance and contact resistance of the source/drain regions, polycrystalline Si ⁇ Ge S has a smaller contact resistance than polysilicon, further improving the current driving capability of the semiconductor device.
  • the semiconductor structure further includes a source/drain extension region 300 embedded in the device layer 103, sandwiched between the source/drain region 310 and the insulating layer 102. between.

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Abstract

一种半导体结构的制造方法，该方法包括以下步骤：提供SOI衬底（100），在SOI衬底（100）上形成栅极堆叠（210、220），在栅极堆叠（210、220）的侧壁形成侧墙（230）；在SOI衬底（100）上形成多晶Si1-xGex层；退火，形成源/漏区（310）。一种半导体结构。通过在较低温度下形成多晶Si1-xGex的源/漏区（310），降低了对沟道、源/漏延伸区（300）掺杂分布的影响，提高了器件性能和可靠性。

Description

一种半导体结构及其制造方法
[0001]本申请要求了 2012年 11月 26日提交的、 申请号为 201210489362.2、 发明名称为 "一种半导体结构及其制造方法" 的中国专利申请的优先权， 其 全部内容通过引用结合在本申请中。 技术领域
[0002]本发明涉及半导体制造领域， 尤其涉及一种半导体结构及其制造方 法。 背景技术
[0003]为了提高集成电路芯片的性能和集成度，器件特征尺寸按照摩尔定 律不断缩小， 目前已经进入纳米尺度。 随着器件体积的缩小， 功耗与漏 电流成为最关注的问题。 采用绝缘体上硅 SOI ( Silicon on Insulator )制备 的 CMOS器件具有高速、 低功耗、 高集成度、 抗辐照和无自锁效应等许 多优点， 已成为深亚微米及纳米级 MOS器件的优选结构。 为了进一步提 高 CMOS器件的性能， 往往要求超薄硅膜（≤100nm ) 的 SOI结构， 使器 件沟道处于全耗尽状态， 用这种超薄 SOI ( UTSOI ) 结构制备的 CMOS 电路可以改善 DIBL ( Drain Induced Barrier Lowering , 漏致势垒降低 )等 短沟道效应、 改善器件的亚阈值特性、 降低电路的静态功耗、 消除 kink 效应等。
[0004】然而， 由于超薄 SOI的顶层硅膜 （≤100nm ) 非常薄， 造成了较大 的源 /漏区串联电阻和接触电阻， 金属硅化物可能消耗掉整个硅膜， 但仍 难以减小源 /漏区串联电阻和接触电阻的影响， 同时还可能造成较大的漏 电流。 通过形成提升源 /漏 （ Raised Source/Drain, RSD ), 可以进一步降低 源 /漏区的接触电阻， 增大器件的驱动电流， 提高器件性能。 现有技术中， 形成提升源 /漏常用的方法为选择性外延单晶硅、 锗等， 工艺温度一般在 650°C以上， 工艺过程中， 容易使得已经形成的源 /漏扩展区、 沟道掺杂区 等的掺杂剂再分布， 可能会造成阈值电压过低， 或沟道穿通短路等问题。 降低提升源 /漏的工艺温度， 减小其对掺杂分布的影响， 成为提升源 /漏技 术的一个重要挑战。 发明内容
[0005]本发明旨在至少解决上述技术缺陷，提供一种半导体器件的制造方 法及其结构， 降低提升源 /漏生长的工艺温度， 减小其对半导体结构掺杂 分布的影响， 提高半导体器件的性能和可靠性。
[0006】为达上述目的， 本发明提供了一种半导体结构的制造方法， 该方法 包括以下步骤：
( a )提供 SOI衬底， 在所述 SOI衬底上形成栅极堆叠， 在所述栅极 堆叠的侧壁形成侧墙；
( b ) 在暴露的 SOI衬底上形成多晶 Si1-xGex层；
( c ) 退火， 在 SOI衬底上的多晶 Si Gex层中形成源 /漏区。
[0007】其中， 在步骤 （a ) 中形成侧墙之前或之后， 还包括步骤：
[0008]以所述栅极堆叠为掩膜， 形成源 /漏延伸区。
[0009】本发明另一方面还提出一种半导体结构， 包括 SOI衬底、 栅极堆 叠、 侧墙、 源 /漏区， 其中：
[0010】所述 SOI衬底包括基底层、 位于所述基底层之上的绝缘层以及位 于所述绝缘层之上的器件层；
[0011]所述栅极堆叠位于所述 SOI衬底之上；
[0012]所述侧墙位于所述栅极堆叠的侧壁上；
[0013]所述源 /漏区形成于所述 SOI衬底之上，位于所述栅极堆叠的两侧， 其材料为多晶 Sii_xGex。
[0014]根据本发明提供的半导体结构及其制造方法，可以在较低温度下形成 源 /漏区， 减小了其对半导体结构掺杂分布的影响， 减小了源 /漏区的串联 电阻和接触电阻， 避免出现阈值电压降低、 沟道穿通短路等问题， 提高 半导体器件的性能和可靠性。 附图说明
[0015]本发明上述的和 /或附加的方面和优点从下面结合附图对实施例的 描述中将变得明显和容易理解， 其中：
[0016】图 1 是根据本发明的半导体结构的制造方法的一个具体实施方式 的流程图；
[0017] 图 2至图 8为根据图 1示出的方法制造半导体结构过程中该半导体结 构在各个制造阶段的剖面结构示意图。 具体实施方式
[0018]下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类 似功能的元件。 下面通过参考附图描述的实施例是示例性的， 仅用于解 释本发明， 而不能解释为对本发明的限制。 下文的公开提供了许多不同 下文中对特定例子的部件和设置进行描述。 当然， 它们仅仅为示例， 并 且目的不在于限制本发明。 此外， 本发明可以在不同例子中重复参考数 字和 /或字母。 这种重复是为了筒化和清楚的目的， 其本身不指示所讨论 各种实施例和 /或设置之间的关系。 此外， 本发明提供了的各种特定的工 艺和材料的例子， 但是本领域普通技术人员可以意识到其他工艺的可应 用于性和 /或其他材料的使用。 另外， 以下描述的第一特征在第二特征之 "上"的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包 括另外的特征形成在第一和第二特征之间的实施例， 这样第一和第二特 征可能不是直接接触。
[0019]图 1为根据本发明的半导体结构制造方法的流程图， 图 2至图 8为根 据本发明的一个实施例按照图 1所示流程制造半导体结构的各个阶段的剖面 示意图。 下面将结合图 2至图 8对图 1中形成半导体结构的方法进行具体地 描述。 需要说明的是， 本发明实施例的附图仅是为了示意的目的， 因此没 有必要按比例绘制。 [0020】参考图 2至图 6, 在步骤 S 101中， 提供 SOI衬底 100 , 在所述 SOI 衬底 100上形成栅极堆叠， 在所述栅极堆叠的侧壁形成侧墙 230。 如图 2 所示， 所述 SOI衬底 100包括基底层 101、位于所述基底层 101之上的绝 缘层 102以及位于所述绝缘层 102之上的器件层 103。
[0021】在本实施例中， 所述基底层 101为单晶硅。 在其他实施例中， 所述 基底层 101 还可以包括其他基本半导体例如锗， 或其他化合物半导体， 例如， 碳化硅、 砷化镓、 砷化铟或者磷化铟。 典型地， 所述基底层 101 的厚度可以约为但不限于几百 米， 例如 0.2mm-lmm的厚度范围。
[0022】所述绝缘层 102可以为 Si02、 氮化硅、 A1203或者其他任何合适的 绝缘材料， 典型地， 所述绝缘层 102的厚度范围为 10nm~300nm。
[0023】所述器件层 103 可以为所述基底层 101 包括的半导体中的任何一 种。 在本实施例中， 所述器件层 103 为单晶硅。 在其他实施例中， 所述 器件层 103 还可以包括其他基本半导体或者化合物半导体。 典型地， 所 述器件层 103的厚度范围是 10nm~100nm。 在本实施例中， 所述 SOI衬底 100为超薄 SOI ( Ultra-Thin SOI, UTSOI )衬底， 具有极薄的器件层， 厚 度通常小于 10nm, 有利于控制源 /漏区深度， 形成超浅结， 从而减小短 沟道效应。
[0024]特别地，在所述 SOI衬底 100中形成隔离区，例如浅沟槽隔离（STI) 结构 120 , 以便电隔离连续的半导体器件。
[0025】所述栅堆叠形成于所述 SOI衬底 100之上， 其包括栅介质层 210、 栅极 220 , 如图 3所示。 可选地， 所述栅极堆叠还可以包括覆盖在所述栅 极上的覆盖层 （未在图中示出） ， 例如通过沉积氮化硅、 氧化硅、 氮氧 化硅、 碳化硅及其组合形成， 用以保护栅极 220 的顶部区域， 防止其在 后续的工艺中受到破坏。 所述栅介质层 210位于 SOI衬底 100上， 可以 为高 K介质， 例如， Hf02、 HfSiO、 HfSiON、 HfTaO、 HfTiO、 HfZrO, A1203、 La203、 Zr02、 LaAlO中的一种或其组合。 在另一个实施例中， 还 可以是热氧化层， 包括氧化硅、 氮氧化硅； 所述栅极介质层 210 的厚度 可以为 lnm~10nm, 如 5nm或 8nm。 而后在所述栅介质层 210上形成栅 极 220, 所述栅极 220可以是通过沉积形成的重掺杂多晶硅， 或是先形成 功函数金属层（对于 NMOS , 例如 TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax等，对于 PMOS,例如 MoNx, TiSiN, TiCN, TaAlC, TiAIN, TaN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, HfRu, RuOx ) , 其厚度可以为 lnm-20nm, 如 3nm、 5nm、 8nm、 10nm、 12nm或 15nm, 再在所述功函数 金属层上形成重掺杂多晶硅、 Ti、 Co、 Ni、 Al、 W或其合金等而形成栅极 220。
[0026】如图 4所示， 所述侧墙 230形成于栅堆叠的侧壁上， 用于将栅堆叠 隔开。 侧墙 230可以由氮化硅、 氧化硅、 氮氧化硅、 碳化硅、 及其组合， 和 /或其他合适的材料形成。 侧墙 230可以具有多层结构。 侧墙 230可以 通过包括沉积-刻蚀工艺形成，其厚度范围可以是 10nm ~100nm,如 30nm、 50nm或 80nm。
[0027】可选地， 在步骤 S101中， 还包括在形成所述栅极堆叠之后或形成 所述侧墙 230之后， 形成源 /漏延伸区 300。 通过低能注入的方式在衬底 100中形成较浅的源 /漏延伸区 300 , 可以向衬底 100中注入 P型或 N型 掺杂物或杂质， 例如， 对于 PMOS来说， 源 /漏延伸区 300可以是 P型掺 杂的 Si; 对于 NMOS来说， 源 /漏延伸区 300可以是 N型掺杂的 Si。 可 选地， 随之对所述半导体结构进行退火， 以激活源 /漏延伸区 300中的掺 杂， 退火可以采用包括快速退火、 尖峰退火等其他合适的方法形成。 在 本发明的其他一些实施例中，退火操作也可以放在形成源 /漏区之后进行。 由于源 /漏延伸区 300的厚度较浅， 可以有效地抑制短沟道效应。 图 5所 示为在形成所述栅极堆叠之后， 以所述栅极堆叠为掩膜进行注入， 形成 所述源 /漏延伸区 300后的结构剖面图， 图 6所示为在形成所述侧墙 230 之后， 形成所述源 /漏延伸区 300后的结构剖面图。
[0028]参考图 1和图 7, 执行步骤 S 102 , 在所述 SOI衬底 100上， 形成 多晶 811^¾}^层 310。 形成所述多晶 811^¾}^层 310的方法包括等离子增 强化学气相淀积 （PECVD ) 、 低压化学气相淀积 （LPCVD ) 、 快速热化 学气相沉积（RTCVD ) , 通过对气体流量、 气压、 设备功率等进行调整， 可以控制形成多晶 811^¾}^层 310的工艺温度在 450 °C以下， 典型的工艺 温度为 425 °C、 400°C。相比于选择性外延单晶 Si、 Ge (工艺温度≥650 °C ) , 化学气相淀积形成多晶 Sii_xGex层的方法， 对半导体结构已有的掺杂分布 影响较小， 利于提高半导体器件的性能和可靠性。 典型地， 生成多晶 Si1-xGex y¾ 310的反应气体为 SiH4、 GeH4, 通过控制 Si¾或 GeH4的气体 流量或气体百分比，来调整 Sii_xGex中 Si和 Ge的组分比。在本实施例中， X的取值是 0.2~0.7。所述多晶 Si^Gex层 310的厚度不能高于所述栅极堆 叠的高度， 其厚度范围是 50nm~200nm。 在本实施例中， 通过在形成所述 多晶 811_}^6}^层 310时进行原位掺杂， 实现对所述多晶 811_}^6}^层 310的 掺杂；在本发明的其他一些实施例中，可以在形成所述多晶 811_}^6}^层 310 之后， 再进行离子注入， 实现对所述多晶 8^^6 层310的掺杂。 其中所 述多晶 Sii_xGex的掺杂浓度为 1018 〜 2xl020cm"3 , 对于 NMOS , Si1-xGex 层的掺杂类型为 N型； 对于 PMOS , 所述多晶 811_}^6}^层的掺杂类型为 P 型。
[0029】参考图 1和图 8 , 在步骤 S 103 中， 进行退火， 并图形化所述多晶
8 _}^6}^层， 形成源 /漏区 310。 退火可以采用包括快速退火、 尖峰退火等 其他合适的方法， 工艺温度为 450°C ~550°C。 在步骤 S 102中， 利用等离 子增强化学气相淀积 （PECVD ) 、 低压化学气相淀积 （LPCVD ) 、 快速 热化学气相沉积 （RTCVD )等方法形成的 811^¾}^层有可能是非晶态的， 通过退火恢复其晶体结构， 消除缺陷， 从而得到多晶 Sii_xGex层。 另一方 面， 通过退火激活施主和受主杂质。 随后， 通过干法刻蚀 RIE等合适的 方法对所述多晶 811_}^6}^层进行图形化， 在刻蚀的 Sii_xGex层上形成源 /漏 区 310。
[0030]随后按照常规半导体制造工艺的步骤完成该半导体结构的制造，例 如， 在源 /漏区上形成金属硅化物； 沉积层间介质层以覆盖所述源 /漏区和 栅极堆叠； 刻蚀所述层间介质层暴露源 /漏区以形成接触孔， 在所述接触 孔中填充金属； 以及后续的多层金属互连等工艺步骤。
[0031】本发明还提供了一种半导体结构， 如图 8所示， 所述半导体结构包 括 SOI衬底 100、 栅极堆叠、 侧墙 230、 源 /漏区 310。 其中所述 SOI衬底 100包括基底层 101、 位于所述基底层 101之上的绝缘层 102以及位于所 述绝缘层 102之上的器件层 103 ; 所述栅极堆叠位于所述 SOI衬底 100 之上； 所述侧墙 230位于所述栅极堆叠的侧壁上； 所述源 /漏区 310形成 于所述 SOI 衬底 100 之上， 位于所述栅极堆叠的两侧， 其材料为多晶 Si1-xGex。 所述多晶 Si1-xGex源/漏区的厚度为 50nm~200nm, x 的取值是 0.2~0.7。 所述多晶 Si1-xGe 々掺杂浓度为 1018 ~ 2xl02°cm-3 , 对于 NMOS , 所述多晶 811_}^6}^层的掺杂类型为 N型； 对于 PMOS , 所述多晶 Sii_xGex 层的掺杂类型为 P型。 所述源 /漏区 310为提升源 /漏结构， 即源 /漏区 310 的顶部高于所述栅极堆叠的底部， 有利于减小源 /漏区的串联电阻和接触 电阻， 多晶 Si^Ge S比于多晶硅， 具有更小的接触电阻， 进一步提高半 导体器件的电流驱动能力。
[0032】可选地， 该半导体结构还包括源 /漏延伸区 300 , 所述源 /漏延伸区 300嵌于所述器件层 103中， 夹于所述源 /漏区 310和绝缘层 102之间。
[0033] 虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发 明的精神和所附权利要求限定的保护范围的情况下， 可以对这些实施例进行 各种变化、 替换和修改。 对于其他例子， 本领域的普通技术人员应当容易理 解在保持本发明保护范围内的同时， 工艺步骤的次序可以变化。
[0034]此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工 艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作 为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发 出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本 发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发 明可以对它们进行应用。 因此，本发明所附权利要求旨在将这些工艺、机构、 制造、 物质组成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1、 一种半导体结构的制造方法， 该方法包括以下步骤：
( a )提供 SOI衬底， 在所述 SOI衬底上形成栅极堆叠， 在所述栅极 堆叠的侧壁形成侧墙；
( b ) 在暴露的 SOI衬底上形成多晶 Si1-xGex层；
( c ) 退火， 在 SOI衬底上的多晶 Si Gex层中形成源 /漏区。
2、 根据权利要求 1所述的方法， 步骤（b ) 中， 形成所述多晶 811_}^6}^层 的方法为等离子增强化学气相淀积 （PECVD ) 、 低压化学气相淀积
( LPCVD ) 、 快速热化学气相沉积 （RTCVD ) 。
3、 根据权利要求 2 所述的方法， 其中所述多晶 Sii_xGex层的厚度为 50匪〜 200匪， X的取值是 0·2~0·7。
4、 根据权利要求 1 所述的方法， 其中步骤 （b ) 中， 通过原位掺杂或后 续离子注入的方法， 对所述多晶 Sii_xGex层进行掺杂。
5、根据权利要求 4所述的方法，其中所述多晶 Sii_xGex的掺杂浓度为 1018 - 2xl020cm"3, 对于 NMOS , 所述多晶 811.}^6}^层的掺杂类型为 N型； 对 于 PMOS , 所述多晶 811_}^6}^层的掺杂类型为 P型。
6、 根据权利要求 1所述的方法， 其中步骤（a ) 中， 在形成侧墙之前或之 后， 还包括步骤：
以所述栅极堆叠为掩膜， 形成源 /漏延伸区。
7、 一种半导体结构， 该结构包括 SOI衬底、 栅极堆叠、 侧墙、 源 /漏区， 其中：
所述 SOI衬底包括基底层、 位于所述基底层之上的绝缘层以及位于 所述绝缘层之上的器件层；
所述栅极堆叠位于所述 SOI衬底之上；
所述侧墙位于所述栅极堆叠的侧壁上；
所述源 /漏区形成于所述 SOI衬底之上， 位于所述栅极堆叠的两侧，
8、 根据权利要求 7所述的半导体结构， 其中， 所述多晶 Si^Ge ^J漏区 的厚度为 50nm~200nm, x的取值是 0.2~0.7。
9、 根据权利要求 7所述的半导体结构， 其中， 所述多晶 Sii_xGex的掺杂 浓度为 1018 〜 2xl020cm"3, 对于 NMOS , 所述多晶 Sii_xGex层的掺杂类型 为 N型； 对于 PMOS , 所述多晶 8^^6 层的掺杂类型为 P型。
10、 根据权利要求 7所述的半导体结构， 其中， 还包括源 /漏延伸区， 所 之间。
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