CN101147243A - 使用硅锗制造半导体结构的方法 - Google Patents

使用硅锗制造半导体结构的方法 Download PDF

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CN101147243A
CN101147243A CNA2005800116543A CN200580011654A CN101147243A CN 101147243 A CN101147243 A CN 101147243A CN A2005800116543 A CNA2005800116543 A CN A2005800116543A CN 200580011654 A CN200580011654 A CN 200580011654A CN 101147243 A CN101147243 A CN 101147243A
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germanium
silicon
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马瑞斯·K.·奥罗斯基
亚历山大·L.·巴尔
马里亚姆·G.·撒达卡
特德·R.·怀特
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NXP USA Inc
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Abstract

提供一种具有硅层(24，26，28)的半导体衬底。在一个实施例中，衬底是硅层(24，26，28)下面具有氧化物层(14)的绝缘体上硅(SOI)衬底(12，14，24，26，28)。在硅层(24，26，28)上形成无定形的或多晶的硅锗层(32)。或者将锗注入到硅层(24，26，28)的顶部形成非晶态的硅锗层(32)。然后将硅锗层(32)氧化，使硅锗层转化成二氧化硅层(34)，并使至少一部分硅层(24，26，28)转化成富含锗的硅(36，38)。然后在用富含锗的硅形成晶体管(48，50，52)之前除去二氧化硅层(34)。在一个实施例中，在硅层(28)之上、硅锗层(32)之下用图案掩模层有选择地形成富含锗的硅(36，38)。或者，隔离区可用于限定衬底的局部区域，在衬底的局部区域中形成富含锗的硅。

Description

使用硅锗制造半导体结构的方法
技术领域
本发明涉及半导体器件，尤其涉及使用硅锗的半导体器件。
背景技术
到目前为止，硅是用于制造集成电路的最普通的半导体材料，其益处是众所周知的。近年来，有锗存在的硅的益处变得更相关并被追求。  困难之一是形成高质量硅锗晶体的能力，也就是说形成高质量单晶的能力，尤其在要求的锗浓度下。高质量硅单晶结构是容易得到的，并且比硅锗结构甚至低浓度锗的硅锗结构廉价得多，所以对硅锗来说竞争是困难的。
但是即使从技术角度来说，在锗的浓度超过10％时是难以外延生长单晶硅锗的。因此要在30％的范围内达到更合乎需要的浓度，要求有特殊的后处理。一个例子是氧化10％硅锗材料，这具有耗尽硅的效果，并使未使用的锗扩散到硅锗层的剩余部分并因此增加锗的浓度。这种方法是昂贵的因为它要求生长相对厚的硅锗层，生长时既费时又费钱。
因此，需要一种既高质量又有成本效率的单晶硅锗的成型方法。
附图说明
本发明通过例子作了图解说明，但不局限于附图，其中相同的附图标记表示相同的元件，其中：
图1是根据本发明第一实施例的第一处理阶段的半导体结构的截面图；
图2是图1的半导体结构下一处理阶段的截面图；
图3是图2的半导体结构下一处理阶段的截面图；
图4是图3的半导体结构下一处理阶段的截面图；
图5是图4的半导体结构下一处理阶段的截面图；
图6是图5的半导体结构下一处理阶段的截面图；
图7是图6的半导体结构下一处理阶段的截面图；
图8是图7的半导体结构下一处理阶段的截面图；
图9是图8的半导体结构下一处理阶段的截面图；
图10是图9的半导体结构下一处理阶段的截面图；
本领域技术人员应当理解，附图中的元件是简单明了的描绘的，没有必要按比例描绘。例如，附图中一些元件的尺寸相对于其他元件来说可能是夸大的，这有助于增进对本发明实施例的理解。
具体实施方式
一方面，以单晶硅层为起点用硅锗获得有源半导体。在硅层上形成相对便宜的硅锗层。该层可以由淀积一个多晶的或无定形的层形成，或者由向硅层中注入锗形成。然后氧化该相对便宜的硅锗层，这具有将锗扩散进入下面的单晶硅层的效果。这使在下面的单晶层成为硅锗层。单晶层的锗浓度由相对便宜的硅锗层的厚度和锗浓度决定。这样就得到具有要求的锗厚度的硅锗半导体，它能够被用作有源半导体，或者能够在其上外延生长应变硅层。通过参考附图和以下描述可以更好的理解上述内容。
图1示出了一种半导体结构10，包括：硅半导体层12，半导体层12上的埋入氧化物14，沟槽隔离区16，沟槽隔离区18，沟槽隔离区20，沟槽隔离区22，沟槽隔离区16和18之间的有源区24，沟槽隔离区18和20之间的有源区26，沟槽隔离区20和22之间的有源区28。有源区24-28是单晶硅。沟槽隔离区16-22是绝缘体例如氧化物。在这个处理阶段，沟槽隔离区16-22从埋入氧化物14延伸到半导体结构10的表面。同样地，如图1所示，有源区24-28从埋入氧化物14延伸到半导体结构10的表面。这种结构通过众所周知的绝缘体上半导体(SOI)技术很容易地得到。
图2示出了在全部有源区28之上并延伸到沟槽隔离区20和22的一部分之上形成了掩模30的半导体结构10。掩模30的定位导致有源区24和26被暴露。它优选由氮化物形成，但是其它材料可能也是有效的。掩模不要求非常精确，并且容易地与沟槽隔离区20和22对准。它可以如此形成：沉淀一层氮化物，沉淀一层光致抗蚀剂，使光致抗蚀剂形成图案，然后按照光致抗蚀剂上的图案蚀刻氮化物以留下掩模30。
图3示出了在淀积一层硅锗层32之后的半导体结构10。它是覆盖淀积，不必形成图案。层32可以淀积为无定形的或多晶的，两者都比形成外延生长单晶硅锗廉价。此外，沟槽隔离区16-22在淀积硅锗层32之前形成。
图4示出了图3的硅锗层32氧化之后的氧化物层34和有源区36和38。氧化步骤使硅锗层32转化为含硅并可除去的氧化物层34，并使锗扩散到有源区24和26中分别形成硅锗有源区36和38。有源区24和26因此变为富含锗的硅区。由于有掩模30，有源区28仍然仅保持为硅。因为有源区24和26的厚度为700埃，硅锗层32的有效厚度在约30％锗时为约500埃。有源区36和38的最终厚度为约500埃。在这种条件下，有源区36和38中锗的最终浓度是约30％。也可以应用其他比率的厚度和锗浓度从而在有源区36和38中获得30％的锗浓度。  并且，有源区36和38可以按需要具有稍微不同的锗浓度。有源区36和38的锗浓度的期望范围甚至可以为15-50％。在此例中，有源区36和38的厚度比有源区24和26小。这个减少的数值由氧化步骤进行多久所决定，必须也是在对锗浓度的最终计算中考虑的。该最终浓度为硅锗层的厚度与最后的有源区厚度之比再乘以硅锗层的锗浓度。
由于最初的硅结构，有源区36和38有些压缩。由于锗在晶格中替换硅，整个晶体结构变得更加压缩。在有源区36和38顶部氧化期间，升高的温度引起部分弛豫。因此从原始硅结构就有弛豫，但晶体本身由于包括锗因而是处于压缩条件下的。弛豫相对容易获得，因为硅有源区24和26是由沟槽隔离区16、18和20的氧化物围绕的。压缩对P沟道晶体管的性能是有益的。
图5示出了除去氧化物层34之后的半导体结构10。有源区36和38被暴露了。任选地，在区36和38之上形成薄的氧化物层可能是所希望的。
图6示出了在有源区36之上形成掩模40之后的半导体结构10。在这个例子中，掩模30显示为没有被除去。一种备选方案是在形成掩模40时除去掩模30并重整有源区28上的掩模。可以用与形成掩模30的方法相同的方法来形成掩模40。结果是有源区38被暴露。
图7示出了在有源区38上外延生长单晶硅层42后的半导体结构10。  由于原始硅结构至少有些弛豫，有源区38引起对硅层42的张应力，并因此引起硅层42的应变。对于N沟道晶体管的性能来说，硅层42的应变是所希望的。应变的量约为1％。形成硅层42之后，执行P型注入。在执行注入之前在有源硅层42之上形成薄的氧化物层也许是有益的。注入将对之后的N沟道晶体管的形成提供本底掺杂。
图8示出了除去掩模40并形成掩模44之后的半导体结构10。掩模44覆盖了有源区38和28以及也为有源区的硅层42。这导致有源区36由于注入而被暴露。掩模44可以是全新的掩模，或者可以是新掩模和掩模30的组合。该掩模可以用与形成掩模30和40的方法相同的方法形成。注入物为N型，将对之后的P沟道晶体管的形成提供本底掺杂。有源区处于至少一部分压应力之下，这对于P沟道的性能是有利的。
图9示出了除去掩模44并在有源区36和38以及硅层42之上形成掩模46之后的半导体10。有源区28被暴露，其为传统的单晶硅。有源区28可以用来制造最常用类型的晶体管。因此，普通类型晶体管批量生产的益处在半导体结构10中也是可获得的。
图10示出了分别在有源区36、38和28内和上形成晶体管48、50和52之后的半导体结构10。晶体管50同时也形成在硅层42内。晶体管48为P沟道，具有在有源区36之上的栅极54、在有源区36和栅极54之间的栅极电介质、有源区36中的第一源极/漏极58、有源区36中与第一源极/漏极58分开的第二源极/漏极60、和围绕栅极54的侧壁间隔物56。源极/漏极58和60为P型。晶体管50为N沟道，具有在有源区38和硅层42之上的栅极62、在栅极62和硅层42之间的栅极电介质66、在层42和有源区38中的源极/漏极68、在有源区38和硅层42中与源极/漏极区68分开的源极/漏极70、围绕栅极62的侧壁间隔物64。源极/漏极68和70为N型。晶体管52可以是N沟道或者P沟道，具有在有源区28之上的栅极72、在栅极72和有源区28之间的栅极电介质76、在有源区28中的源极/漏极区78、在有源区28中的源极/漏极80、和围绕栅极72的侧壁间隔物74。源极/漏极78和80可以是P型或N型。晶体管52证明传统的N和P沟道晶体管可以相对简单地集成到所述的方法中。
通过上文的详细说明，本发明已经针对特殊的实施例进行了描述。然而，本领域普通技术人员应当理解，不脱离如下面的权利要求书所述的本发明的范围，可以做出多样的修改和变化。例如，不同于锗和硅的半导体材料可以用于这种方法以达到这种结果。因此，说明书和附图应被视为一种例证性的说明，而不是对本发明保护范围的限制，诸如此类的修改都应包括在本发明的范围之内。
以上描述了特殊实施例的益处、其他优点和问题的解决方案。更进一步的益处的一个例子是，由于在形成硅锗有源区之前能形成沟槽隔离区，在形成沟槽隔离区时不要求额外的改进，不像在硅锗区形成沟槽隔离时所要求的那样。然而，在任一或全部权利要求中，这些益处、优点、问题的解决方案，和可能引起任何益处、优点、或引起解决方案存在或变得更明确的任何元件，不被认为是关键的、必要的或基本的性质或元件。在这里，术语″包括″意味着覆盖不唯一的内含物，就是说，包括一系列元件的步骤、方法、物品或设备不仅仅包括那些元件，还可能包括对这些步骤、方法、物品、或设备来说没有明确地列举或非固有的其他元件。

Claims (26)

1.一种方法，包括：
提供半导体衬底；
在半导体衬底之上形成第一层，其中第一层选自由非晶态的含硅锗层和多晶的含硅锗层组成的组；和
氧化第一层，其中氧化第一层使第一层转化为含硅氧化物层并使至少一部分半导体衬底转化为富锗半导体层。
2.如权利要求1的方法，其中半导体衬底包括位于半导体层之下的埋入氧化物层，在第一层氧化时，所述半导体衬底的半导体层转化为富锗半导体层。
3.如权利要求1的方法，其中半导体衬底包括硅层且所述至少一部分半导体衬底包括硅层，在第一层氧化时，所述半导体衬底的硅层变为富含锗的硅层。
4.如权利要求1的方法，其中氧化第一层将整个第一层转化为含硅氧化物层。
5.如权利要求1的方法，进一步包括除去所述含硅氧化物层。
6.如权利要求1的方法，其中富锗半导体层含有约15-50％范围内的锗。
7.如权利要求1的方法，其中形成第一层的步骤包括覆盖淀积第一层。
8.如权利要求1的方法，其中形成第一层的步骤包括将锗注入半导体衬底的顶部，使顶部转化为非晶的硅锗层。
9.如权利要求1的方法，其中半导体衬底包括第一隔离区和第二隔离区，在第一和第二隔离区之间形成富含锗的硅层。
10.如权利要求1的方法，进一步包括在形成第一层之前在半导体衬底之上形成图案掩模层，所述富含锗的硅层形成于半导体衬底被图案掩模层暴露的部分中。
11.如权利要求1的方法，进一步包括形成晶体管，该晶体管具有在所述富锗半导体层之上的栅极电介质，在栅极电介质之上的栅极，在所述富锗半导体层中的在栅极下面的沟道，和与沟道横向分开的源极/漏极区。
12.如权利要求1的方法，进一步包括：
在所述富锗半导体层之上形成半导体层；和
形成晶体管，该晶体管具有在所述富锗半导体层之上的栅极电介质，在栅极电介质上的栅极，在所述半导体层中的在栅极下面的沟道，和与沟道横向分开的源极/漏极区。
13.一种方法，包括：
提供包括硅层的半导体衬底；
在所述半导体衬底的硅层上形成硅锗层，其中硅锗层为无定形的或多晶的；
氧化硅锗层，使硅锗层转化为二氧化硅并使至少一部分硅层转化为富含锗的硅。
14.如权利要求13的方法，其中形成硅锗层的步骤包括覆盖淀积硅锗层。
15.如权利要求13的方法，其中形成第一层的步骤包括将锗注入半导体衬底的硅层顶部。
16.如权利要求13的方法，进一步包括，在氧化硅锗层后，除去转化了的硅锗层。
17.如权利要求13的方法，进一步包括：
在硅层中形成隔离区，其中位于隔离区之间的硅层的有源部分被转化为富含锗的硅。
18.如权利要求13的方法，进一步包括：
在形成硅锗层之前，形成上覆硅层的图案掩模层，其中硅层被图案掩模层暴露的部分转化为富含锗的硅。
19.如权利要求13的方法，进一步包括形成晶体管，该晶体管具有在富含锗的硅之上的栅极电介质，在栅极电介质之上的栅极，在富含锗的硅中的在栅极下面的沟道，和与沟道横向分开的源极/漏极区。
20.如权利要求13的方法，进一步包括：
在富含锗的硅之上形成半导体层；
形成晶体管，该晶体管具有在半导体层之上的栅极电介质，在栅极电介质之上的栅极，在半导体层中的在栅极下面的沟道，和与沟道横向分开的源极/漏极区。
21.如权利要求13的方法，其中半导体衬底进一步包括在硅层下面的埋入氧化物层。
22.一种方法，包括：
提供半导体衬底；
形成上覆半导体衬底的第一层，其中第一层包括具有第一物质和第二物质的化合物，第一层为无定形的或多晶的；
将第一层转化为包括第一物质的可除去的层，其中将第一层转化为可除去的层驱使第二物质进入下面的半导体衬底中。
23.如权利要求21的方法，进一步包括，在将第一层转化为可除去的层后，除去该可除去的层。
24.如权利要求21的方法，进一步包括：在半导体衬底中形成隔离区，在第一层被转化为可除去的层的期间，第二物质被驱入位于隔离区之间的半导体衬底的有源部分。
25.如权利要求21的方法，进一步包括：在形成第一层之前，形成上覆半导体衬底的图案掩模层，在第一层被转化为可除去的层的期间，第二物质被驱入半导体衬底被图案掩模层暴露的部分。
26.如权利要求21的方法，进一步包括：在第一层被转化之后，形成晶体管，该晶体管具有在半导体衬底之上的栅极电介质，在栅极电介质之上的栅极，在栅极电介质下面的沟道，和与沟道横向分开的源极/漏极区。
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