WO2011038598A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
WO2011038598A1
WO2011038598A1 PCT/CN2010/074392 CN2010074392W WO2011038598A1 WO 2011038598 A1 WO2011038598 A1 WO 2011038598A1 CN 2010074392 W CN2010074392 W CN 2010074392W WO 2011038598 A1 WO2011038598 A1 WO 2011038598A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
fin
region
semiconductor device
source
Prior art date
Application number
PCT/CN2010/074392
Other languages
English (en)
French (fr)
Inventor
朱慧珑
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to US12/865,220 priority Critical patent/US8552477B2/en
Publication of WO2011038598A1 publication Critical patent/WO2011038598A1/zh
Priority to US14/029,157 priority patent/US8741703B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to an improved FinFET formed on a semiconductor-on-insulator (SOI) substrate.
  • SOI semiconductor-on-insulator
  • MOSFETs metal oxide semiconductor field effect transistors
  • a conventional planar MOSFET includes a sandwich structure composed of a hl:l gate electrode, a gate insulating layer, and a semiconductor layer, and includes a channel region under the gate electrode and source/drain regions on both sides of the channel region in the semiconductor layer.
  • a silicide layer can be formed on the source/drain regions, and the silicide layer is connected to the source/drain electrodes by via holes, thereby reducing the parasitic resistance and parasitic capacitance of the device.
  • the planar MOSFET is adversely affected by the short channel effect, causing the threshold voltage of the device to fluctuate as the channel length changes.
  • a FinFET formed on an SOI is disclosed in US Patent No. 6,413, 802, including a channel region formed in the middle of a fin of a semiconductor material, and formed at both ends of the fin. Source/drain area.
  • the gate electrode surrounds the channel region (i.e., the double gate structure) on both sides of the channel region, so that the inversion layer is formed on each side of the channel.
  • the thickness of the channel region in the fin is so thin that the entire channel region can be controlled by the gate, and thus can function to suppress the short channel effect.
  • the capacitive coupling between the source/drain regions and the gate limits the freedom of device design. If it is desired to reduce the parasitic resistance, it is necessary to increase the thickness of the source/drain regions. However, an increase in the thickness of the source/drain regions will result in an increase in the coupling area between the source/drain regions and the gate, resulting in an increase in parasitic capacitance, and vice versa. Therefore, those skilled in the art are not able to achieve a reduction in the parasitic resistance and parasitic capacitance with a conventional FinFET structure.
  • An object of the present invention is to provide a semiconductor device capable of suppressing a short channel effect and reducing parasitic resistance and parasitic capacitance.
  • Another object of the present invention is to provide a semiconductor device that utilizes stress to improve device performance.
  • a semiconductor device formed on a SOI substrate the SOI substrate including a buried insulating layer and a semiconductor layer formed on the buried insulating layer, wherein a semiconductor material is formed in the semiconductor layer a fin, the fin includes two opposite sides perpendicular to a surface of the SOI substrate, the semiconductor device comprising: a source region and a drain region disposed at both ends of the fin; a channel region disposed at an intermediate portion of the fin; And a stack of gate dielectric and gate conductors disposed on one side of the fin, the gate conductor and the channel region being isolated by the gate dielectric, wherein the gate conductor The side parallel to the surface of the SOI substrate extends away from the one side of the fin.
  • a method of fabricating a semiconductor device comprising the steps of: a) forming a fin of a semiconductor material in a layer of semiconductor material of an SOI substrate by a self-aligned method, the fin comprising Two opposite sides perpendicular to the surface of the SOI substrate; b) forming a stack of gate dielectric and gate conductors on one side of the fin, the gate conductors being oriented parallel to the surface of the SOI substrate Extending away from the one side of the fin; c) implanting dopants into the semiconductor material at both ends of the fin to form source and drain regions; and d) forming a channel region in the middle portion of the fin.
  • the semiconductor device of the present invention includes a fin of a semiconductor material, but its structure is different from that of a conventional FinFET because its gate is disposed only on one side of the fin and extends away from the fin, and the conventional FinFET is set to
  • the double gate structure surrounds the channel region of the middle portion of the fin.
  • the source/drain regions are provided at both ends of the fin, extending in a direction opposite to the direction in which the gate extends.
  • the gate electrode extending in parallel with the source/drain regions between the source/drain regions is not included in the semiconductor device of the present invention, so that there is no capacitive coupling of the source/drain regions and the gate, thereby reducing the parasitic capacitance.
  • the semiconductor device of the present invention allows the parasitic resistance to be reduced by using a thicker source/drain region.
  • a stress layer can be formed in the source/drain regions to increase the stress in the channel region, thereby further improving the switching speed of the device.
  • the alignment channel region is very thin: about 5-40 nm.
  • the thickness of the channel region is reduced by the ultra-steep back-off well (SSRW) process. Even if the gate is provided only on one side of the channel, the channel region can still be fully controlled by the gate, thereby reducing the effect of the short channel effect.
  • 1A and 1B are a three-dimensional perspective view and a plan view schematically showing the structure of a semiconductor device according to the present invention, and lines A- ⁇ ', 1- ⁇ and 2- 2' represent the cut-off bits S of the following cross-sectional views.
  • FIGS. 2 to 9 are cross-sectional views of the semiconductor structure formed along the line A-A' of the respective steps of the method of fabricating a semiconductor device in accordance with the present invention, in which respective steps of forming the fin region and the gate region are shown.
  • 10-16 are cross-sectional views of the semiconductor structure formed along the line of the subsequent steps of the method of fabricating a semiconductor device in accordance with the present invention, showing the steps of forming the source/drain regions.
  • 17-21 are cross-sectional views of the semiconductor structure formed along the line A-A' of the subsequent steps of the method of fabricating a semiconductor device in accordance with the present invention, showing various steps of forming a channel region.
  • 22A, 22B, 23A, 23B are cross-sectional views of the semiconductor structure formed along the line A-A' and line 2-2', respectively, of a subsequent step of the method of fabricating a semiconductor device according to the present invention, wherein the source is shown
  • Each of the steps of forming a silicide layer on the /drain region and the gate are cross-sectional views of the semiconductor structure formed along the line A-A' and line 2-2', respectively, of a subsequent step of the method of fabricating a semiconductor device according to the present invention, wherein the source is shown
  • the SOI substrate as an initial structure includes, for example, silicon on insulator, silicon germanium on insulator, and a semiconductor material stack on the insulator.
  • the semiconductor material stack includes, for example, a III-V semiconductor such as C1 ⁇ 4As, InP, GaN, SiC.
  • the gate conductor can be a metal layer, a doped polysilicon layer, or a stacked gate conductor comprising a metal layer and a doped polysilicon layer.
  • the material of the metal layer is TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, H3 ⁇ 4iN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, Hf u, RuOx and a combination of the various metallic materials described.
  • the gate dielectric may be composed of a material of 810 2 or a dielectric constant greater than Si() 2 , including, for example, an oxide, a nitride, an oxynitride, a silicate, an aluminate, a titanate, wherein the oxide includes, for example, si0 2, HlO 2 Zr0 2, A1 2 0 3, Ti0 2, La 2 0 3, for example, comprises nitride Si 3 N 4, including silicates such HffiiOx, e.g. aluminates including LaA10 3, titanates comprise e.g. SrTi0 3 , the oxynitride includes, for example, SiON.
  • the gate dielectric can be formed not only by materials well known to those skilled in the art, but also by materials for the gate dielectric that are bursting in the future.
  • FIG. 1A and 1B are a three-dimensional perspective view and a plan view showing the structure of a semi-conductive device according to the present invention.
  • the line ⁇ - ⁇ ', 1-1 ⁇ 2-2' in Fig. 1B indicates the intercept position of the cross-sectional view, wherein the line ⁇ - ⁇ ' is perpendicular to the channel length direction and passes through the gate, and the line l- ⁇ along the channel The length direction passes through the channel region, and the line 2-2' follows the channel length direction and passes through the insulating material filler between the source/drain regions.
  • a semiconductor device 100 is formed in a semiconductor layer of an SOI substrate, including a channel region 11 at an intermediate portion of a fin of a semiconductor material, source regions 12 and drain regions 13 at both ends thereof, A stack of gate dielectric 14 and gate 15 disposed adjacent one side of the fin, and an insulating fill 18 for filling the opening in the other side of the fin.
  • the thickness of the channel region located in the middle portion of the fin is very thin, for example, in the range of about 5-40 nm. This thickness is similar to the thickness of the channel region in a conventional FinFET and can be formed using a similar self-aligned process.
  • the inventors have found that although the double gate structure is not employed, if the thickness of the channel region is within the above range, the gate electrode on the side of the fin can still act on the entire channel region, thereby suppressing the short channel effect.
  • the semiconductor device further includes stressors 16 and 17 for applying stress to the source region 12 and the drain region 13.
  • the stress layers 16 and 17 are adjacent to the source region 12 and the drain region 13, respectively, and the contact area is as large as possible, so that the contact resistances of the stress layers 16 and 17 with the source region 12 and the drain region 13 are minimized.
  • step portions are formed in the source region 12 and the drain region 13, and the stress layers 16 and 17 are located in the step portion, so that one side and bottom of the stress layers 16 and 17 and the source region 12 and the drain region are provided. 13 contacts.
  • the materials of Mi 16 and 17 should be capable of producing stresses in the channel region that are beneficial for improving the performance of the product.
  • the stress layers 16 and 17 should apply tensile stress in the source/drain direction to the channel region to increase the mobility of electrons as carriers.
  • the stress layers 16 and 17 should apply a compressive stress in the source/drain direction to the channel region to increase the mobility of holes as carriers.
  • the stress layers 16, 17 are respectively located in the source region 12 in contact with the source (not shown), and the drain region 13 is in contact with the drain (not shown).
  • the conductive path between them, and therefore the stress layers 16, 17 should also be electrically conductive.
  • B-doped SiGe materials can be used, and for p-type MOSFETs, Si or C doped with As or P can be used.
  • Source region 12, drain region 13 and gate 15 are not shown in FIGS. 1A and 1B, such as sidewall spacer sidewalls, silicide layers, source contacts, drain contacts, and gates.
  • the method of fabricating a semiconductor device of the present invention begins with an SOI wafer which is a laminate including a bottom substrate 21, a buried insulating layer (BOX) 22, and a top semiconductor layer 23.
  • SOI wafer which is a laminate including a bottom substrate 21, a buried insulating layer (BOX) 22, and a top semiconductor layer 23.
  • BOX buried insulating layer
  • the SiGe layer 24 having a Ge content of about 5-15% and a thickness of about 3-20 nm is epitaxially grown on the SOI wafer by a known deposition process such as PVD, CVD, atomic layer deposition, sputtering, or the like. 30-100 nm Si layer 25.
  • the Si layer 25 may be formed in a separate deposition step, or may be formed in situ by using a Si target or a precursor after epitaxially growing the SiGe layer 24.
  • an Hf0 2 layer 26 having a thickness of about 3 to 10 nm is formed on the Si layer 25 by atomic layer deposition or magnetron sputtering.
  • a portion of the Si 2 layer 26, the Si layer 25, and the SiGe layer 24 is removed by a thousand etching, such as ion milling, plasma etching, reactive ion etching, and laser ablation using the photoresist pattern 27 as a mask.
  • a thousand etching such as ion milling, plasma etching, reactive ion etching, and laser ablation using the photoresist pattern 27 as a mask.
  • a laminated structure in which the Hf0 2 layer 26, the Si layer 25, and the SiGe layer 24 are patterned is formed.
  • reactive ion etching it can be carried out in two steps.
  • the first step choose the etching atmosphere
  • the bulk component is such that a portion of the HfO 2 layer 26 and Si)i 25 is removed and stopped at the top of the SiGe layer 24.
  • the second step a portion of the SiGe layer 24 is removed by changing the gas composition of the etching atmosphere and stopped on the top semiconductor layer 23 of the SOI substrate. It is known in the art that in reactive ion etching, one of the SiGe layer and the Si layer can be selectively removed by changing the gas composition of the etching atmosphere.
  • the photoresist pattern 27 is removed by dissolving or ashing in a solvent.
  • a conformal oxide layer 28 having a thickness of about 2 to 5 nm is formed on the patterned laminate structure and the exposed portion of the top semiconductor layer 23 of the SOI substrate.
  • the thin oxide layer can be formed by a known deposition process such as PVD, CVD, atomic layer deposition, sputtering, and the like.
  • a conformal nitride is first formed, and then a portion of the layer is removed, thereby including ⁇ 1 ⁇ 2
  • Si Layer 25 the SiGe layer 24 has a nitride spacer sidewall 29 having a thickness of about 5 to 50 nm formed on both sides of the laminated structure.
  • a photoresist layer pattern 30 is formed on the structure shown in FIG. 4 by a conventional photolithography process including an exposure and development step to block the left side spacer sidewall and the left side of the patterned laminate structure. section.
  • the spacer sidewalls on the right side are removed by isotropic etching, such as conventional wet etching using an etchant solution, using the resist pattern 30 as a mask.
  • the spacer sidewalls on the right side can be removed in three steps.
  • Ge is implanted into the spacer sidewall on the right side by the oblique ion implantation using the resist pattern 30 as a mask to cause damage.
  • the photoresist pattern 30 is removed by dissolving or ashing in a solvent.
  • the spacer sidewalls on the right side are selectively removed from the spacer sidewalls on the left side by wet etching or dry etching.
  • the gas composition of the etching atmosphere is selected, for example, by reactive ion etching to selectively remove portions of the oxide layer 28 that are exposed on the surface of the semiconductor structure.
  • the gas composition of the etching atmosphere is changed, for example, by reactive ions.
  • the exposed portions of the top semiconductor layer of the SOI substrate are etched selectively to form fins 23' of the semiconductor material in a self-aligned manner.
  • a thin layer 26' of a conformal oxide (such as Hf0 2 ) having a thickness of about 2-4 nm is sequentially formed on the surface of the semiconductor structure shown in FIG. 6 by CVD or ALD as a gate dielectric.
  • a 3-10 nm conformal metal (e.g., TiN, cermet) layer 31 serves as a metal layer for the stacked gate conductor, and a covered polysilicon layer 32 serves as a polysilicon layer in the stacked gate.
  • the polysilicon layer 32 can be doped in situ to increase conductivity.
  • Polysilicon layer 32 covers the entire top of the semiconductor structure. Then, the polysilicon layer 32 is planarized (CMP). The planarization process stops at the top of the metal layer of the stacked gate conductor, thereby obtaining a flat surface of the semiconductor structure.
  • a portion of the polysilicon layer 32 is selectively removed from the metal layer 31 by wet etching or thousand etching, and the multi-product silicon 32 is etched back. Then, an oxide layer 33 of the cap is formed on the entire surface of the semiconductor structure, for example, by CVD.
  • the oxide layer 33 is planarized, and the planarization process is stopped at the top of the metal layer of the stacked gate conductor, thereby obtaining a flat surface of the semiconductor structure.
  • the oxide layer 33 is filled with a portion of the polysilicon layer 32 which is removed by etch back.
  • a nitride layer 34 is formed on the surface of the semiconductor structure, for example, by CVD.
  • a strip-shaped photoresist pattern 35 for defining a gate region of a device including a metal layer 31 and a polysilicon layer 32 is formed by a conventional photolithography process including exposure and development steps. .
  • the nitride eyebrows 34, the oxide layer 33, the polysilicon layer 32, and the like are sequentially removed by a thousand etching, such as ion milling, plasma etching, reactive ion etching, and laser ablation.
  • the metal layer 31, a portion of the oxide thin layer 26' on either side of the fin 23', is etched at the top of the buried insulating layer (BOX) 22 of the SOI wafer.
  • a cross-sectional view of the semiconductor structure taken along line 1-1' is shown in Fig. 10.
  • An etching step using the photoresist pattern 35 as a mask obtains a 3 ⁇ 4 layer of the nitride layer 34, the oxide layer 33, the polysilicon layer 32, the metal layer 31, and the oxide thin layer 26' over the Si layer 25.
  • a portion of the fin 23', the SiGe layer 24, and the Si layer 25 may be removed to define the length of the fin by an additional mask formation and etching step before or after the etching step described above.
  • the dimension of the fin 23' defined thereby is shown in Fig. 10 in the horizontal direction.
  • the portion of the Si layer 25 and the SiGe layer 24 is sequentially removed by dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation, using the photoresist pattern 35 as a mask.
  • dry etching such as ion milling, plasma etching, reactive ion etching, laser ablation
  • a multilayer layer 101 including a nitride layer 34, an oxide layer 33, a polysilicon layer 32, a metal layer 31, an oxide thin layer 26', a Si 25, and a SiGe layer 24 is formed over the fins 23'.
  • the photoresist pattern 35 is removed by dissolving or ashing in a solvent.
  • a thickness of about 2-5 mn is sequentially formed on the entire surface of the semiconductor structure.
  • the conformal oxide layer 35 and the conformal nitride layer 37 having a thickness of about 10-20 nm.
  • a portion of the nitride layer 37 is removed by a thousand etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, which is stopped at the surface of the oxide layer 36, thereby forming a plurality of layers on the fins 23' and Nitride spacer sidewalls 37 are formed on both sides of layer 101, respectively.
  • a thousand etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation
  • the oxide layer 36 is removed by dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation, using the multilayer stack 101 and the nitride spacer sidewalls 37 on both sides as a hard mask.
  • dry etching such as ion milling, plasma etching, reactive ion etching, laser ablation
  • the exposed surface and a portion of the semiconductor material of the fin 23' form an opening 38 at both ends of the fin 23 in the length direction (i.e., the horizontal direction in the drawing).
  • a thin layer of semiconductor material having a thickness of about 1 Onm is retained at the bottom of the cornice 38.
  • the etch step is aligned, wherein the size of ⁇ I" 38 is substantially determined by the mountain oxide layer 36 and the nitride spacer sidewalls 37.
  • Figure 14 illustrates an optional step in some embodiments for performing halo implantation from the opening 38 to the middle portion of the fin 23' using tilt ion implantation (halo implantation for an n-type MOSFET using B or BF2 as a dopant)
  • tilt ion implantation halo implantation for an n-type MOSFET using B or BF2 as a dopant
  • As or P is used as a dopant.
  • FIG 15 illustrates certain steps in the alternative embodiment, the use of angled ion implantation extension implantation (extension implantation) to the intermediate portion of the fin 23 'of the MOSFET 0 to n-type, using as As or P dopants.
  • extension implantation extension implantation
  • B or BF2 is used as a dopant.
  • the extended implant uses a smaller angle of inclination and a larger energy, so that in the extended implant, most of the implanted ions pass through a thin layer of semiconductor material at the bottom of the opening 38, so that the thin layer of the semiconductor material is not amorphous. Chemical.
  • the opening 38 provides a window for ion implantation, and the nitride layer 34, the oxide layer 36, and the nitride spacer sidewall 37 on the surface of the semiconductor structure provide a hard mask, the above-described extended implantation, halo implantation, and Source/drain implants can be performed in situ, reducing the number of masks and simplifying the process.
  • the formed semiconductor structure is annealed, such as a spike anneal, which is used to activate the dopant implanted by the previous implant process and to eliminate damage caused by the implant.
  • the dopant distribution in the semiconductor fin 23' is as shown in the figure, and the source region 12 and the drain region 13 are formed at the bottom of the opening 38, respectively, adjacent to the source region 12 and the drain region 13.
  • the locations respectively form a source extension region 12' and a drain extension region 13', respectively forming a source adjacent to the source extension region 12' and the drain extension region 13' and extending toward the intermediate portion of the fin 23' Halo zone 12" and leak halo zone 13".
  • the stress layer 39 and the epitaxial silicon layer 40 thereon are epitaxially grown in this order.
  • the mountain is epitaxially grown and the stress 39 is formed only on the thin layer of semiconductor material at the bottom of the cornice 38.
  • the material of stress j3 ⁇ 4 39 is SiGe with a Ge content of about 20-50% and B-doped in-situ. After epitaxial growth, compressive stress is generated in the source-drain direction of the channel region, which can enhance the p-type MOSFET. performance.
  • the material of the stress layer 39 is Si:C having a C content of about 0.5-2% and is doped with As or P in situ. After epitaxial growth, tensile stress is generated in the source-drain direction of the channel region, which can be enhanced. The performance of n-type MOSFETs.
  • the formed semiconductor structure is oxidized, and the top of the epitaxial silicon layer 40 is oxidized to form an oxidized thin layer 36' having a thickness of about 3 to 10 nm.
  • the epitaxial silicon layer 40 formed on top of the stress layer 39 is used to obtain good quality SiO 2 .
  • the oxide layer 33 formed in the step shown in FIG. 8 is used as a hard mask, and the metal layer 31 is sequentially removed by dry etching such as ion milling etching, plasma etching, reactive ion etching, and laser ablation. a thin portion of the nitride thin layer 26', the Si layer 25, the SiGe layer 24, and the fins 23'. The etching stops at the top of the buried insulating layer 22 of the SOI substrate, thereby forming the cornice 41 in a self-aligned square shape. .
  • dry etching such as ion milling etching, plasma etching, reactive ion etching, and laser ablation.
  • the thickness of the fin 23' is reduced to a value which is approximately equal to the sum of the thicknesses of the oxide 28 and the nitride spacer sidewall 29.
  • the fins are used to form the channel region, and the stress in the channel region is increased due to the material removed by etching, which stress can further enhance device performance.
  • the laminate material on the right side of the opening 41 can serve as a gate region of an adjacent MOSFET (not shown), and the filling material in the opening 41 can be shallow.
  • the role of the trench isolation zone is left.
  • the nitride spacer sidewalls 37 formed in the step shown in Fig. 12 are also present on the side faces of the gate stack.
  • the oxide thin layer 26' and the metal layer 31 remaining inside the opening are selectively removed by the thousand etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, with respect to the oxide j 33 (The right side wall portion in Fig. 18).
  • the thousand etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation, with respect to the oxide j 33 (The right side wall portion in Fig. 18).
  • ions are implanted into the fins 23' of the semiconductor material by oblique ion implantation, and then annealed (for example, laser annealing) to activate the implanted dopants to form on the side of the fins 23' near the opening 41.
  • SSRW 42. Opening 41 provides a window for ion implantation.
  • the left side spacer sidewalls 37 are removed in three steps.
  • the oxide layer 33 is used as a mask, and the Icheon dip ion implantation implants Ge into the spacer sidewall on the left side to cause damage, as shown in FIG.
  • the photoresist pattern 30 is removed by dissolving or ashing in a solvent.
  • the left side spacer sidewall is selectively removed from the spacer sidewall on the right side by wet etching or dry etching, as shown in FIG.
  • a thin layer 33' of a conformal oxide having a thickness of about 2 to 5 nm is formed on the entire surface of the semiconductor structure, for example, by CVD.
  • Nitride is then deposited, for example by CVD, to a thickness at least which fills the opening 41.
  • the nitride is selectively etched back relative to the oxide layer 33' such that the nitride layer around the opening is completely removed, leaving only the nitride fill material 43 in the cornice.
  • selective etching is performed relative to the nitride fill material 43 by dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation,
  • the etch completely removes portions of the oxide layer 33' that are exposed on the surface of the semiconductor structure, leaving only the portion of the sidewalls and bottom of the ruthenium filled opening of the oxide layer 33', thereby exposing the polysilicon layer in the gate stack
  • This etch also removes a portion of the buried oxide layer 22 of the SOI substrate.
  • a portion of the upper and left side surfaces of the polysilicon layer 32 in the gate stack, and at least a portion of the epitaxial silicon layer 40 of the source and drain regions are converted using a conventional silicidation process. It is a silicide layer to reduce the contact resistance between the gate, source/drain and corresponding metal contacts.
  • a Ni layer having a thickness of about 5 to 12 nm is first deposited, and then heat-treated at a temperature of 300 to 500 ° C for 1 to 10 seconds so that at least a portion of the polysilicon layer 32 and the epitaxial silicon layer 40 form NiSi, and finally the wet method is utilized.
  • the etching removes unreacted Ni.
  • an interlayer insulating layer, a via hole in the interlayer insulating layer, and an upper surface of the interlayer insulating layer are formed on the obtained semiconductor structure according to a method known in the art. Wiring or draining, thereby completing other parts of the semiconductor device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

半导体器件及其制造方法 技术领域
本发明涉及一种半导体器件及其制造方法， 更具体地， 涉及在绝缘体上半导体 ( SOI ) 衬底上形成的改进的 FinFET。 背景技术
集成电路技术的一个重要发展方向是金属氧化物半导体场效应晶体管 (MOSFET) 的尺、寸按比例缩小， 以提高集成度和降低制造成本。 然而， 众所周知 的是随着 MOSFET的尺寸减小会产生短沟道效应。 在 MOSFET的尺寸按比例缩小 时， 栅极的有效长度减小， 使得实际上由栅极电压控制的耗尽层电荷的比例减少， 从而阈值电压随沟道长度减小而下降。
常规的平面 MOSFET包括 hl:l栅电极、栅绝缘层和半导体层构成的三明治结构， 在半导体层中包括位于栅电极下方的沟道区和位于沟道区两侧的源 /漏区。在源 /漏区 上可以形成硅化物层， 利用通孔将硅化物层与源 /漏电极相连， 从而减小了器件的寄 生电阻和寄生电容。平面 MOSFET受到短沟道效应的不利影响， 导致器件的阈值电 压随沟道长度的变化而波动。
为了抑制短沟道效果， 在美国专利 US6, 413， 802中公丌了在 SOI上形成的 FinFET, 包括在半导体材料的鳍片 (fin)的中间形成的沟道区， 以及在鳍片两端形成 的源 /漏区。 栅电极在沟道区的两个侧面包围沟道区 （即双栅结构）， 从而反型层形 成在沟道各侧上。鳍片中的沟道区厚度很薄， 使得整个沟道区都能受到栅极的控制， 因此能够起到抑制短沟道效应的作用。
然而， 在常规的 FinFET 中， ώ于在源 /漏区之间存在着与源 /漏区平行延伸的 栅极， 并且源 /漏区与栅极之间的距离很近， 因此在源 /漏区和栅极之间存在着电容耦 合， 导致了寄生电阻和寄生电容较大的问题。
源 /漏区和栅极之间的屯容耦合限制了器件设计的自由度。 如果希望减小寄生 电阻， 则需要增加源 /漏区的厚度。 然而， 源 /漏区厚度的增加将导致源 /漏区与栅极 之间的耦合面积增加， 从而导致寄生电容的增加， 反之亦然。 因此， 本领域的技术 人员还不能利用常规的 FinFET结构实现寄生电阻和寄生电容的问时减小。
结果， 在常规的 FinFET中， 由于时间常数 RC的值较大而导致延迟增加， 进 而降低了器件的幵关速度。 发明内容
本发明的目的是提供一种能够抑制短沟道效应,并且减小寄生电阻和寄生电容 的半导体器件。
本发明的另一目的是进一歩提供利用应力提高器件性能的半导体器件。
根据本发明的一方面， 提供 种半导体器件， 形成在 S0I 衬底上， 所述 S0I 衬底包括掩埋绝缘层和在掩埋绝缘层上形成的半导体层， 在所述半导体层中形成了 半导体材料的鳍片， 所述鳍片包括垂直于 SOI衬底表面的两个相对侧面， 所述半导 体器件包括： 设置在鳍片两端的源区和漏区； 设置在鳍片的中间部分的沟道区； 以 及设置在鰭片的一个侧面上的栅极电介质和栅极导体的叠层， 所述栅极导体与所述 沟道区之间由所述栅极屯介质隔离， 其中所述栅极导体沿着平行于所述 SOI衬底表 面的方向背离所述鰭片的所述一个侧面延伸。
根据本发明的另一方面， 提供一种制造半导体器件的方法， 包括以下歩骤： a) 通过自对准方法在 SOI衬底的半导体材料层中形成半导体材料的鳍片， 所述鳍片包 括垂直于 SOI衬底表面的两个相对侧面； b) 在鳍片的一个侧面上形成栅极电介质和 栅极导体的叠层， 所述栅极导体沿着平行于所述 SOI衬底表面的方向背离所述鰭片 的所述一个侧而延伸； c) 向鳍片两端的半导体材料中注入掺杂剂以形成源区和漏 区； 以及 d) 在鳍片的中间部分形成沟道区。
应当注意， 本发明的半导体器件包含半导体材料的鳍片， 但其结构不同于常规 的 FinFET , 因为其栅极仅设置在鳍片的一个侧而上并背离鳍片延伸， 而常规的 FinFET设置成双栅结构并包围鳍片的中间部分的沟道区。而且，源 /漏区设置在鳍片 的两端， 朝着与栅极的延伸方向相反的方向延伸。
在本发明的半导体器件中没有包括在源 /漏区之间与源 /漏区平行延伸的栅极， 因此不存在源 /漏区与栅极之问的电容耦合， 从而减小了寄生电容。 同时， 本发明的 半导体器件允许通过使用较厚的源 /漏区而减小寄生电阻。
还可以在鰭片邻接沟道区的部分形成延伸区， 减小载流子的传导路径长度， 从 而进一歩减小与寄生电容和寄生电阻有关的寄生作用。
另外， 还可以在源 /漏区形成应力层， 用来增加沟道区的应力， 从而进一歩提 髙器件的开关速度。 为了有效地控制短沟道效应， 对准沟道区非常薄： 约为 5-40nm。 并且， 在 优选的工艺中， 利用超陡后退阱（SSRW )工艺进 - · 歩减小了沟道区的厚度。 即使仅 在沟道的一侧设置栅极， 沟道区仍然可以受到栅极的完全控制， 从而减小了短沟道 效应的影响。 附图说明
图 1A和 1B是示意性说明根据本发明的半导体器件的结构的三维透视图和俯 视图， 线 A- Α'、 1-Γ和 2- 2'表示以下截面图的截取位 S。
图 2- 9是根据本发明的制造半导体器件的方法的各个步骤所形成的半导体结构 沿 A-A'线的截面图， 其中示出了形成鳍片区域和栅极区域的各个歩骤。
图 10-16是根据本发明的制造半导体器件的方法的随后歩骤所形成的半导体结 构沿 l -Γ线的截面图， 其中示出了形成源 /漏区的各个步骤。
图 17-21是根据本发明的制造半导体器件的方法的随后步骤所形成的半导体结 构沿 A-A'线的截而图， 其中示出了形成沟道区的各个步骤。
图 22A、 22B、 23A、 23B 分别是根据本发明的制造半导体器件的方法的随后 歩骤所形成的半导体结构沿 A-A'线和 2-2'线的截面图， 其中示出了在源 /漏区和栅极 上形成硅化物层的各个歩骤。 具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中， 相同的元件采用类似的 附图标记来表示。 为了清楚起见， 附图中的各个部分没有按比例绘制。
应当理解， 在描述器件的结构时， 当将一层、 一个区域称为位于另一层、 另一 个区域 "上面 "或"上方"时， 可以指直接位于另一层、 另一个区域上面， 或者在其与 另一层、 另一个区域之间还包含其它的层或区域。 并且.， 如果将器件翻转， 该一层、 一个区域将位于另 - - ·层、 另一个区域"下面"或"下方"。
如果为了描述直接位于另一层、 另一个区域上面的情形， 本文将采用"直接 在 ......上面"或"在 ......上而并与之邻接"的表述方式。
在下文中描述了本发明的许多特定的细节， 例如器件的结构、 材料、 尺寸、 处 理工艺和技术， 以便更清楚地理解本发明。 但正如本领域的技术人员能够理解的那 样， 可以不按照这些特定的细节来实现本发明。 除非在下文中特别指出，半导体器件中的各个部分可以由本领域的技术人员公 知的材料构成。 作为初始结构的 SOI衬底例如包括绝缘体上硅、 绝缘体上硅锗、 以 及绝缘体上的半导体材料叠层。 该半导体材料叠层例如包括 III-V 族半导体， 如 C¼As、 InP、 GaN、 SiC。 栅极导体可以是金属层、 掺杂多晶硅层、 或包括金属层和 掺杂多晶硅层的叠层栅导体。 金属层的材料为 TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 H¾iN、 MoSiN、 RuTax、 NiTax, MoNx、 TiSiN、 TiCN、 TaAlC、 TiAlN、 TaN、 PtSix、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 Hf u、 RuOx和所述各种金属材料的组合。 栅极电介质可以由 8102或介¾常数大于 Si()2的材料构成，例如包括氧化物、氮化物、 氧氮化物、硅酸盐、铝酸盐、钛酸盐，其中，氧化物例如包括 Si02、HlO2 Zr02、 A1203、 Ti02、 La203， 氮化物例如包括 Si3N4， 硅酸盐例如包括 HffiiOx, 铝酸盐例如包括 LaA103， 钛酸盐例如包括 SrTi03， 氧氮化物例如包括 SiON。 并且， 栅极电介质不 仅可以由本领域的技术人员公知的材料形成， 也可以采用将来丌发的用于栅极电介 质的材料。
图 1A和 1B是示意性说明根据本发明的半导休器件的结构的三维透视图和俯 视阁。 图 1B中的线 Λ-Α'、 1-1 \ 2-2'表示截面图的截取位置， 其中线 Α-Λ'垂直于沟 道长度方向并经过栅极， 线 l-Γ沿着沟道长度方向并经过沟道区， 线 2-2'沿着沟道 长度方向并经过源 /漏区之间的绝缘材料填充物。
如图 1A和 1B所示， 在 SOI衬底的半导体层中形成了半导体器件 100， 包括 位于半导体材料的鰭片的中间部分的沟道区 11、 位于其两端的源区 12和漏区 13、 设置成邻接鰭片的一个侧面的栅极电介质 14和栅极 15的叠层， 以及用于填充鳍片 的另一个侧面中的丌口的绝缘材料填充物 18。
位于鰭片的中间部分的沟道区的厚度非常薄， 例如在约 5-40nm的范围内。 该 厚度与常规的 FinFET中的沟道区的厚度相近， 并可以采用类似的自对准工艺形成。
本发明人发现， 尽管未采用双栅结构， 但如果沟道区的厚度在上述范围， 位于 鰭片一侧的栅极仍然可以作用在整个沟道区上， 从而抑制短沟道效应。
优选地， 该半导体器件还包括用于向源区 12 和漏区 13 施加应力的应力层 ( stressor) 16和 17。 应力层 16和 17分别与源区 12和漏区 13邻接， 并且接触面积 尽可能大， 使得应力层 16和 17与源区 12和漏区 13的接触电阻最小。 如图 1Λ和 1B所示，在源区 12和漏区 13中形成了台阶部分，应力层 16和 17位于台阶部分中， 从而应力层 16和 17的一个侧面及底部与源区 12和漏区 13接触。 应 Mi 16和 17 的材料应 能够在沟道区中产生有利于提高品休管性能的应 力。 当形成的器件是 n型 MOSFET吋， 应力层 16和 17应当向沟道区施加沿源 /漏 极方向的拉应力， 以提高作为载流子的电子的迁移率。 相反， 当晶体管是 p 型 MOSFET吋， 应力层 16和 17应当向沟道区施加沿源 /漏极方向的压应力， 以提高作 为载流子的空穴的迁移率。
应当注意， 在图 1A和 1B所示的半导体器件结构的实例中， 应力层 16、 17分 别位于源区 12与源极接触（未示出）、 漏区 13与漏极接触（未示出）之间的导电路 径上， 因此应力层 16、 17还应当是导电性的。 对于 n型 MOSFET, 可以采用掺 B 的 SiGe材料， 而对于 p型 MOSFET, 可以采用掺杂 As或 P的 Si:C材料。
在图 1A和 1B中没有示出源区 12、 漏区 13及栅极 15上方的附加层和部分， 例如栅极的侧壁间隔侧壁、 硅化物层、 源极接触、 漏极接触和栅极接触、 层间绝缘 层、 在层间绝缘层中形成的通孔以及钝化层等。
在下文描述制造该半导体器件的歩骤中,将说明与该半导体器件密切相关的一 些附加层和部分， 但省去了对本领域公知的那些附加层和部分 （如源极接触、 漏极 接触和栅极接触） 的详细描述。 为了简明起见， 可以在一幅图中描述经过数个步骤 后获得的半导体结构。
参见图 2， 本发明的制造半导体器件的方法开始于 SOI晶片， SOI晶片是包括 底部衬底 21、 掩埋绝缘层 （BOX) 22和顶部半导体层 23的叠层。
通过已知的沉积工艺， 如 PVD、 CVD、 原子层沉积、 溅射等,在 SOI晶片上依 次外延生长 Ge含量约为 5-15%、厚度约为 3- 20nm的 SiGe层 24和厚度约为 30-100nm 的 Si层 25。 Si层 25可以在单独的沉积步骤中形成， 也可以在外延生长 SiGe层 24 之后通过使用 Si靶或前体原位形成。
然后，通过原子层沉积或磁控溅射，在 Si层 25上形成厚度约为 3-10nm的 Hf02 层 26。
参见图 3,通过包括曝光和显影步骤的常规光刻工艺，在 ΗίΌ2层 26上形成了条 形的光抗蚀剂图案 27。
参见图 4,利用光抗蚀图案 27作为掩模， 通过千法蚀刻， 如离子铣蚀刻、 等离 子蚀刻、 反应离子蚀刻、 激光烧蚀， 去除 1¾02层 26、 Si层 25、 SiGe层 24的一部 分， 形成 Hf02层 26、 Si层 25、 SiGe层 24的构图的叠层结构。
如果采用反应离子蚀刻， 可以分为两个步骤进行。 在第一歩骤， 选择蚀刻气氛 的 体组分， 使得去除 HfO2层 26和 Si )i 25的一部分， 并在 SiGe层 24顶部停止。 在第二步骤，通过改变蚀刻气氛的气体组分，使得去除 SiGe层 24的一部分，并在 SOI 衬底的顶部半导体层 23上停止。 本领域的技术人员已知在反应离子蚀刻中， 可以通 过改变蚀刻气氛的气体组分控制材料的选择性去除 SiGe层和 Si层中的一种。
然后， 通过在溶剂屮溶解或灰化去除光抗蚀剂图案 27。
在构图的叠层结构和 SOI衬底的顶部半导体层 23的暴露部分上形成厚度约为 2-5nm的共形氧化物层 28。
氧化物薄层可通过已知的沉积工艺形成， 如 PVD、 CVD、 原子层沉积、 溅射 等。
然后， 首先形成共形氮化物^， 然后去除该层的一部分， 从而在包括 Η1Ό2
26、 Si层 25、 SiGe层 24的叠层结构两侧形成厚度约为 5-50nm的氮化物间隔侧壁 29。
参见图 5,通过包括曝光和显影步骤的常规光刻工艺，在图 4所示的结构上形成 光抗蚀剂层图案 30， 以遮挡左侧的间隔侧壁以及构图的叠层结构的左侧部分。
参见图 6,利用抗蚀剂图案 30作为掩模， 通过各向同性蚀刻， 例如使用蚀刻剂 溶液的常规湿法蚀刻， 去除右侧的间隔侧壁。
替代地， 可以分为三个歩骤去除右侧的间隔侧壁。 在第一步骤， 利用抗蚀剂图 案 30作为掩模， 利用倾角离子注入在右侧的间隔侧壁中注入 Ge以造成损伤。 在第 二歩骤， 通过在溶剂中溶解或灰化去除光抗蚀剂图案 30。 在第三歩骤， 通过湿法蚀 刻或干法蚀刻， 相对于左侧的间隔侧壁选择性地去除右侧的间隔侧壁。
在去除右侧的间隔侧壁之后， 选择蚀刻气氛的气体组分， 例如通过反应离子蚀 刻选择性地去除氧化物层 28在半导体结构的表面上暴露的部分。接着， 利用氧化物 层 28的剩余部分、 侧壁间隔侧壁 29和包括 Η1Ό2层 26、 Si层 25、 SiGe层 24的叠 结构作为硬掩模， 改变蚀刻气氛的气体组分， 例如通过反应离子蚀刻选择性去除 SOI衬底的顶部半导体层的暴露部分， 以自对准的方式形成半导体材料的鳍片 23'。
参见图 7, 例如通过 CVD或 ALD, 在图 6所示的半导体结构表面上依次形成 厚度约为 2-4nm的共形氧化物（如 Hf02)薄层 26'作为栅极电介质、厚度约为 3-10nm 的共形金属 （如 TiN， 金属陶瓷） 层 31作为叠层栅导体的金属层、 以及覆盖的多晶 硅层 32作为叠层栅^体中的多晶硅层。
优选地， 可以对多晶硅层 32进行原位掺杂以提高导电性。 多晶硅层 32覆盖半导体结构的整个顶部。然后， 对多晶硅层 32进行平面化处 理（CMP)。 该平面化处理停止在叠层栅导体的金属层的顶部， 从而获得了半导体结 构的平整表面。
参见图 8， 通过湿法蚀刻或千法蚀刻，相对于金属层 31选择性地去除多晶硅层 32的一部分， 对多品硅^ 32进行回蚀刻。 然后， 例如通过 CVD , 在半导体结构的 整个表面上形成稷盖的氧化物层 33。
对氧化物层 33进行平面化处理， 该平面化处理停止在叠层栅导体的金属层的 顶部， 从而获得了半导体结构的平整表面。 结粜， 氧化物层 33填充了多晶硅层 32 的通过回蚀刻去除的部分。
然后， 例如通过 CVD， 在半导体结构的表面上形成氮化物层 34。
参见图 9， 通过包括曝光和显影歩骤的常规光刻工艺， 形成条形的光抗蚀剂图 案 35， 用于限定器件的栅极区域， 叠层的栅导体包括金属层 31和多晶硅层 32。
然后， 利用光抗蚀剂图案 35作为掩模， 通过千法蚀刻， 如离子铣蚀刻、 等离 子蚀刻、 反应离子蚀刻、 激光烧蚀， 依次去除氮化物眉 34、 氧化物层 33、 多晶硅层 32、 金属层 31、 氧化物薄层 26'的位于鳍片 23'两侧的一部分， 该蚀刻在 SOI晶片的 掩埋绝缘层 （BOX) 22的顶部停止。
与图 9所示的半导体结构沿 线的截面图相对应， 在图 10中示出了半导体 结构沿 1-1'线的截面图。 利用光抗蚀图案 35作为掩模的蚀刻歩骤获得了位于 Si层 25上方的氮化物层 34、 氧化物层 33、 多晶硅层 32、 金属层 31、 氧化物薄层 26'的 ¾层。
在上述蚀刻歩骤之前或之后， 通过附加的掩模形成歩骤和蚀刻歩骤， 可以去除 鳍片 23'、 SiGe层 24和 Si层 25的一部分， 以限定鳍片的长度。在图 10中示出了由 此限定的鳍片 23'沿水平方向的尺寸。
参见图 11， 仍然利用光抗蚀剂图案 35作为掩模， 通过干法蚀刻， 如离子铣蚀 刻、 等离子蚀刻、 反应离子蚀刻、 激光烧蚀， 依次去除 Si层 25和 SiGe层 24的 - 部分，该蚀刻在鳍片 23'的顶部停止。结果，在鰭片 23'上方形成了包括氮化物层 34、 氧化物层 33、 多晶硅层 32、 金属层 31、 氧化物薄层 26'、 Si 25、 SiGe层 24的多 层叠层 101。
参见图 12， 通过在溶剂中溶解或灰化去除光抗蚀剂图案 35。
然后， 例如通过 CVD， 在半导体结构的整个表而上依次形成厚度约为 2-5mn 的共形氧化物层 35和厚度约为 10-20nm的共形氮化物层 37。
通过千法蚀刻， 如离子铣蚀刻、 等离子蚀刻、 反应离子蚀刻、 激光烧蚀， 去除 氮化物层 37的一部分， 该烛刻在氧化物层 36的表面停止， 从而在鳍片 23'和多层叠 层 101的两侧分别形成氮化物间隔侧壁 37。
参见图 13， 利用多层叠层 101及两侧的氮化物间隔侧壁 37作为硬掩模， 通过 干法蚀刻， 如离子铣蚀刻、 等离子蚀刻、 反应离子蚀刻、 激光烧蚀， 去除氧化物层 36的暴露表面及鳍片 23'的一部分半导体材料， 从而在鰭片 23沿长度方向 （即图中 的水平方向）的两端形成开口 38。在幵口 38的底部保留了厚度约为 l Onm的半导体 材料薄层。
该蚀刻歩骤是 对准的，其中丌 I」 38的尺寸基本上山氧化物层 36和氮化物间 隔侧壁 37确定。
图 14示出了某些实施例中的可选步骤， 利用倾角离子注入从开口 38 向鰭片 23'的中间部分进行晕圈注入（halo implantation 对于 n型 MOSFET,采用 B或 BF2 作为糁杂剂。 对于 p型 MOSFET, 采用 As或 P作为惨杂剂。
图 15示出了某些实施例中的可选步骤，利用倾角离子注入向鳍片 23'的中间部 分进行延伸注入（extension implantation ) 0 对于 n型 MOSFET, 采用 As或 P作为掺 杂剂。 对于 P型 MOSFET， 采用 B或 BF2作为掺杂剂。
与晕圈注入相比， 延伸注入采用的倾角较小而能量较大， 从而在延伸注入中， 大多数注入的离子穿过开口 38底部的半导体材料薄层，使得该半导体材料薄层没有 非晶化。
由于开口 38提供了离子注入的窗口， 并且位于半导体结构的表面上的氮化物 层 34、 氧化物层 36、 氮化物间隔侧壁 37提供了硬掩模， 因此上述延仲注入、 晕圈 注入和源 /漏区注入可以在原位进行， 从而减少了掩模数量并简化了工艺。
参见图 16，对所形成的半导体结构进行退火处理，例如尖峰退火（spike anneal 退火歩骤用来激活通过先前的注入歩骤而注入的掺杂剂并消除注入导致的损伤。
经过退火处理之后， 在半导体鳍片 23'屮的掺杂剂分布如图中所示， 在开口 38 的底部分别形成了源区 12和漏区 13， 在与源区 12和漏区 13相邻的位置分别形成 了源延仲区 12'和漏延伸区 13'，在与源延伸区 12'和漏延伸区 13'相邻并朝着鳍片 23' 的中间部分延伸的位置分别形成了源晕圈区 12"和漏晕圈区 13"。
然后， 通过己知的沉积工艺， 如 PVD、 CVD、 原子层沉积、 溅射等，在开口 38 中依次外延生长应力层 39及其上的外延硅层 40。 山于外延生长， 应力 39仅形成 在丌口 38底部的半导体材料薄 ^上。 对于 p型 MOSFET, 应力 j¾ 39的材料是 Ge 含量约为 20-50%的 SiGe并原位掺 B， 外延生长后，在沟道区延源漏方向产生压应力， 这可以增强 p型 MOSFET的性能。 对于 n型 MOSFET, 应力层 39的材料是 C含量 约为 0.5-2%的 Si:C并原位掺 As或 P， 外延生长后， 在沟道区延源漏方向产生拉应 力， 这可以增强 n型 MOSFET的性能。
然后， 对所形成的半导体结构进行氧化处理， 外延硅层 40的顶部发生氧化从 而形成厚度约为 3-10nm的氧化薄层 36'。 在应力层 39的顶部形成的外延硅层 40用 于获得良好质量的 Si02。
参见图 17，利用在图 8所示的步骤中形成的氧化物层 33作为硬掩模，通过干法 蚀刻， 如离子铣蚀刻、 等离子蚀刻、 反应离子蚀刻、 激光烧蚀， 依次去除金属层 31、 氮化物薄层 26' 、 Si层 25、 SiGe层 24、 鳍片 23'的一部分， 该蚀刻在 SOI衬底的掩 埋绝缘层 22顶部停止， 从而以自对准的方'式形成幵口 41。 结果， 鳍片 23'的厚度减 小到大致等丁 ·氧化物 28和氮化物间隔侧壁 29的厚度之和的数值。 如下文所述， 该鳍片用于形成沟道区， 由于蚀刻所去除的材料， 在沟道区中的应力进 歩增加， 此应力可对进一歩增强器件性能。
在开口 41的右侧保留着包括氮化物薄层 26'、 金属层 31、 多晶硅层 32、 氧化 物层 33的一部分的叠层材料。在制造含有相同结构的多个 MOSFET的集成电路时， 位于开口 41 右侧的叠层材料可以作为相邻的 MOSFET (未示出） 的栅极区域， 而 开口 41中的填充材料可以起到浅沟隔离区的作用。
此外， 如图 17所示， 在图 12所示歩骤中形成的氮化物间隔侧壁 37还存在于 栅极叠层的侧面上。
参见图 18， 通过千法蚀刻， 如离子铣蚀刻、 等离子蚀刻、 反应离子蚀刻、 激 光烧蚀， 相对于氧化物 j 33， 选择性地去除开口内部残留的氧化物薄层 26'和金属 层 31 (图 18中的右侧侧壁部分）。
然后， 优选地， 利用倾角离子注入向半导体材料的鳍片 23'注入离子， 然后进 行退火（例如激光退火）， 以激活注入的掺杂剂， 从而在鳍片 23'靠近开口 41的一侧 形成 SSRW 42。 开口 41提供了离子注入的窗口。 有关 SSRW的形成工艺可参见以 下文件：
1) G.G. Shahidi, D.A. Antoniadis and H.I. Smith, IEEE TED Vol 36, p.2605, 1989
2) C. Fiegna, H. Iwai, T. Wada, M. Saito, E. Sangiorgi and B. Ricco, IEEE TED Vol.41, p.941 , 1994.
3) J.B. Jacobs and D.A. Antoniadis, IEEE TED Vol.42, p.870, 1995.
4) S.E. Thompson, Ρ.Λ. Packan and M.T. Bohr, VLSI Tech Symp,, p.154, 1996. 参见图 19和 20， 分¾_≡个歩骤去除左侧的间隔侧壁 37。 在第一歩骤， 禾 氧 化物层 33作为掩模， 利川倾角离子注入在左侧的间隔侧壁中注入 Ge以造成损伤， 如图 19所示。 在第二步骤， 通过在溶剂中溶解或灰化去除光抗蚀剂图案 30。 在第 三歩骤， 通过湿法蚀刻或干法蚀刻， 相对于右侧的间隔侧壁选择性地去除左侧的间 隔侧壁， 如图 20所示。
参见图 21， 例如通过 CVD , 在半导体结构的整个表面上形成厚度约为 2-5nm 的共形氧化物薄层 33'。 然后， 例如通过 CVD沉积氮化物， 其厚度至少能够填充开 口 41。 相对于氧化物层 33 '， 选择性地回蚀刻氮化物， 使得完全去除开口周围的氮 化物层， 仅在丌口中留卜氮化物填充材料 43。
参见图 22A和 22B , 通过干法蚀刻， 如离子铣蚀刻、 等离于蚀刻、 反应离子蚀 亥 |J、 激光烧蚀， 相对于氮化物填充材料 43选择性地去除 ¾化物，
该蚀刻完全去除了氧化物层 33'在半导体结构表面上暴露的部分， 只留下氧化 物层 33'在巳填充的开口侧壁和底部的部分， 从而暴露出栅极叠层中的多晶硅层 32 的上表而和左侧表而， 以及源极区域和漏极区域的外延硅层 40的上表面。
该蚀刻也去除了 SOI衬底的掩埋氧化物层 22的一部分。
参见图 23Λ和 23B , 利用常规的硅化工艺， 将栅极叠层中的多晶硅层 32的上 表面和左侧表面的一部分， 以及源极区域和漏极区域的外延硅层 40的至少一部分， 转化为硅化物层， 以减小栅极、 源 /漏极与相应的金属接触之间的接触电阻。
例如， 首先沉积厚度约为 5- 12nm的 Ni层， 然后在 300-500°C的温度下热处理 1 -10秒钟， 使得多晶硅层 32和外延硅层 40的至少一部分形成 NiSi， 最后利用湿法 蚀刻去除未反应的 Ni。
在完成图 2-23 所 的歩骤之后， 按照本领域公知的方法， 在所得到的半导体 结构上形成层间绝缘层、 位于层间绝缘层中的通孔、 位 T层间绝缘层上表面的布线 或屯极， 从而完成半导体器件的其它部分。
以上描述只是为了示例说明和描述本发明，而非意图穷举和限制本发明。因此， 本发明不局限于所描述的实施例。 对于本领域的技术人员明显可知的变型或更改， 均在本发明的保护范围之内。

Claims

权 利 要 求
1、 一种半导体器件， 形成在 S0I衬底上， 所述 S0I衬底包括掩埋绝缘层和在 掩埋绝缘层上形成的半导体层， 在所述半导体层中形成半导体材料的鳍片， 所述鰭 片包括垂直于 SOI衬底表面的两个相对侧面， 所述半导体器件包括：
设置在鳍片两端的源区 （12) 和漏区 （13);
设置在鳍片的中问部分的沟道区 （11); 以及
设置在鳍片的一个侧面上的栅极电介质（14)和栅极导体的叠层， 所述栅极导 体与所述沟道区 （11) 之间山所述栅极电介质 （14) 隔离，
其中所述栅极导体沿着平行于所述 S01 衬底表面的方向背离所述鳍片的所述 一个侧面延伸。
2、 根据权利耍求 1所述的半导体器件， 其中所述源区 （12) 和漏区 （13) 包 括沿着平行于所述 SOI衬底表面的方向背离所述鰭片的另一个侧面延伸的部分。
3、 根据权利要求 1所述的半导体器件， 还包括超陡后退阱 （42)， 所述超陡后 退阱 (42) 设置在所述鳍片中邻接沟道区并靠近所述鳍片的另一个侧而的位置。
4、 根据权利要求 1至 3中任一项所述的半导体器件， 其中所述沟道区 （11) 的厚度在 5-40nm的范围内。
5、 根据权利要求 1至 3所述的半导体器件， 其中所述栅极导体为金属层、 掺 杂多晶硅层、 或包括金属层和掺杂多晶硅层的叠层栅导体。
6、 根据权利要求 5所述的半导体器件， 其中所述金属层由选自由 TaC、 TiN、
TaTbN、 TaErN、 TaYbN、 TaSiN、 HlSiN、 MoSiN、 RuTax、 NiTax, MoNx、 TiSiN、 TiCN、 TaAlC、 TiAlN、 TaN、 PtSix、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 應 u、 RuOx及其组 合构成的组中的一种材料形成。
7、根据权利要求 1至 3中任一项所述的半导体器件，其中所述栅极电介质（14) 山选自由 Si02、 Si3N4、 I- ΙβίΟχ、 Hf02, Zr02、 A1203、 Ti02、 La2()3、 SrTi03、 LaA103 及其组合构成的组中的 种材料形成。
8、根据权利要求 1至 3中任一项所述的半导体器件， 还包括应力层（16, 17)， 所述应力层 （16， 17) 设置在所述源区 （12) 和漏区 （13) 上， 并用于向所述源区
(12) 和漏区 （13) 施加应力。
9、 根据权利要求 8所述的半导体器件， 其中所述源区 （12) 和漏区 （13) 包 括凹进的台阶部分， 所述应力层 （16， 17) 设置在所述台阶部分中。
10、 根据权利要求 8所述的半导体器件， 其中所述应力层 （16， 17) 由 SiGe 或 Si:C形成。
11、根据权利要求 1至 3中任- -项所述的半导体器件， 其中还包拈在所述鰭片 中与所述源区（12)和漏区（13)邻接并朝着所述沟道区（11 )延伸的源延伸区（ 12') 和漏延伸区 (13')。
12、 根据权利耍求 11所述的半导体器件， 其中还包括在所述鳍片中与所述源 延仲区（12')和漏延伸区（ 13')邻接并朝着所述沟道区（11)延仲的源晕圈区（12") 和漏晕圈区 （13")。
13、 一种制造半导体器件的方法， 包括以下歩骤：
a) 通过 对准方法在 SOI衬底的半导体材料 (23) 中形成 导体材料的鳍 片 （23')， 所述鳍片 （23') 包括垂直于 S01衬底表而的两个相对侧 1ΪΓΙ;
b) 在鰭片 （23' ) 的一个侧面上形成栅极电介质 （14) 和栅极导体的叠层， 所 述栅极导体沿着平行于所述 SOI衬底表面的方向背离所述鳍片（23') 的所述一个侧 而延伸；
c) 向鳍片 '（23')两端的半导休材料中注入掺杂剂以形成源区（12)和漏区（13); 以及
d) 在鳍片 (23，) 的中间部分形成沟道区 （11)。
14、 根据权利要求 13所述的方法， 其屮形成半导体材料的鰭片 （23') 的歩骤 a)包括以下歩骤：
在所述卡导体材料层 （23) 上形成构图的叠层结构 （24， 25, 26);
在所述叠层结构 （24， 25， 26) 上和所述半导体材料 (23) 的整个暴露表面 上形成共形氧化物层 （28) 和共形氮化物层；
选择性去除所述共形氧化物 ^ (28)和所述共形氮化层的一部分， 以便在叠层 结构 (24， 25， 26) 的一个侧壁上留下所述共形氧化物层 (28) 的一部分和氮化物 间隔侧壁 （29); 以及
利 ffl所述共形氧化物层 （28) 的所述一部分、 所述氮化物间隔侧壁 （29)、 以 及所述叠层结构 （24， 25， 26) 作为硬掩模， 选择性去除所述半导体材料层 （23)， 在鳍片 （23') 的屮间部分留下第一厚度的半导体材料。
15、 根据权利要求 14所述的方法， 其屮形成沟道区的歩骤 d)包括以下歩骤： 利用所述共形氧化物层 （28) 的所述一部分、 以及所述氮化物问隔侧壁 （29) 作为硬掩模， 选择性去除所述叠层结构 （24， 25, 26) 及半导体材料的鳍片 （23') 的- 部分， 在鳍片 （23') 的中间部分留下第二厚度的半导体材料作为沟道区 （11)。
16、 根据权利耍求 13所述的方法， 在形成沟道区的步骤 d)之后， 还包括以下 歩骤：
在所述鳍片的中间部分， 在靠近鳍片的另一个侧面的位置形成与沟道区 （11) 邻接的超陡后退阱 （42)。
17、 根据权利要求 13所述的方法， 其中所述栅极导体为金属层、 掺杂多晶硅 层、 或包括金属层和掺杂多晶硅层的叠层栅导体
18、 根据权利要求 13所述的方法， 在形成源区和漏区的步骤 c)和形成沟道区 的歩骤 d)之间， 还包括在所述源区 （12) 和漏区 （13) 上形成应力层 （16， 17)， 用 于向所述源区 （12) 和漏区 （13) 施加应力。
19、 根据权利耍求 18所述的方法， 其中形成应力层的步骤包括以下歩骤： 在所述源区 （12) 和漏区 （13) 中分别形成凹进的开口 （38); 以及 在开口 （38) 中填充应力层 （16、 17) 的材料。
20、 根据权利耍求 19所述的方法， 在形成幵口的歩骤和填充应力层的材料的 歩骤之间， 还包括以下歩骤：
采用倾角离子注入， 从丌口 （38) 向鳍片 （23') 的中间部分进行延伸注入以 形成延伸区 （12'， 13')。
21、 根据权利要求 20所述的方法， 在延伸注入歩骤之前， 还包括以下歩骤： 采用倾角离子注入， 从幵口 （38) 向鰭片 （23') 的中间部分进行晕圈注入以 形成晕圈区 （12"， 13")。
22、 根据权利要求 21所述的方法， 其中延伸注入步骤屮使用的注入倾角小于 晕圈注入步骤， 而延伸注入步骤中使用的注入能量大于暈圈注入歩骤。
PCT/CN2010/074392 2009-09-30 2010-06-24 半导体器件及其制造方法 WO2011038598A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/865,220 US8552477B2 (en) 2009-09-30 2010-06-24 FinFET with improved short channel effect and reduced parasitic capacitance
US14/029,157 US8741703B2 (en) 2009-09-30 2013-09-17 Method for manufacturing FinFET with improved short channel effect and reduced parasitic capacitance

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN2009102353399A CN102034865B (zh) 2009-09-30 2009-09-30 半导体器件及其制造方法
CN200910235339.9 2009-09-30

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US12/865,220 A-371-Of-International US8552477B2 (en) 2009-09-30 2010-06-24 FinFET with improved short channel effect and reduced parasitic capacitance
US14/029,157 Division US8741703B2 (en) 2009-09-30 2013-09-17 Method for manufacturing FinFET with improved short channel effect and reduced parasitic capacitance

Publications (1)

Publication Number Publication Date
WO2011038598A1 true WO2011038598A1 (zh) 2011-04-07

Family

ID=43825524

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2010/074392 WO2011038598A1 (zh) 2009-09-30 2010-06-24 半导体器件及其制造方法

Country Status (3)

Country Link
US (2) US8552477B2 (zh)
CN (1) CN102034865B (zh)
WO (1) WO2011038598A1 (zh)

Families Citing this family (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102034865B (zh) 2009-09-30 2012-07-04 中国科学院微电子研究所 半导体器件及其制造方法
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
CN102315265B (zh) * 2010-06-30 2013-12-04 中国科学院微电子研究所 半导体器件及其制造方法
US8377783B2 (en) 2010-09-30 2013-02-19 Suvolta, Inc. Method for reducing punch-through in a transistor device
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8400219B2 (en) 2011-03-24 2013-03-19 Suvolta, Inc. Analog circuits having improved transistors, and methods therefor
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
KR101891373B1 (ko) 2011-08-05 2018-08-24 엠아이이 후지쯔 세미컨덕터 리미티드 핀 구조물을 갖는 반도체 디바이스 및 그 제조 방법
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
CN103165425B (zh) * 2011-12-08 2015-07-15 中芯国际集成电路制造(上海)有限公司 一种形成鳍式场效应管栅极侧壁层的方法
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US9368628B2 (en) * 2012-07-05 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with high mobility and strain channel
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
CN103779222A (zh) * 2012-10-23 2014-05-07 中国科学院微电子研究所 Mosfet的制造方法
WO2014071049A2 (en) 2012-10-31 2014-05-08 Suvolta, Inc. Dram-type device with low variation transistor peripheral circuits, and related methods
US8802513B2 (en) * 2012-11-01 2014-08-12 International Business Machines Corporation Fin field effect transistors having a nitride containing spacer to reduce lateral growth of epitaxially deposited semiconductor materials
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US8994415B1 (en) 2013-03-01 2015-03-31 Suvolta, Inc. Multiple VDD clock buffer
US8988153B1 (en) 2013-03-09 2015-03-24 Suvolta, Inc. Ring oscillator with NMOS or PMOS variation insensitivity
US9034715B2 (en) * 2013-03-12 2015-05-19 International Business Machines Corporation Method and structure for dielectric isolation in a fin field effect transistor
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9449967B1 (en) 2013-03-15 2016-09-20 Fujitsu Semiconductor Limited Transistor array structure
US9112495B1 (en) 2013-03-15 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit device body bias circuits and methods
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US8976575B1 (en) 2013-08-29 2015-03-10 Suvolta, Inc. SRAM performance monitor
KR102178831B1 (ko) * 2014-03-13 2020-11-13 삼성전자 주식회사 스트레서를 갖는 반도체 소자 형성 방법 및 관련된 소자
US9312364B2 (en) 2014-05-27 2016-04-12 International Business Machines Corporation finFET with dielectric isolation after gate module for improved source and drain region epitaxial growth
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment
KR102255174B1 (ko) 2014-10-10 2021-05-24 삼성전자주식회사 활성 영역을 갖는 반도체 소자 및 그 형성 방법
US9397161B1 (en) 2015-02-26 2016-07-19 International Business Machines Corporation Reduced current leakage semiconductor device
US9425259B1 (en) 2015-07-17 2016-08-23 Samsung Electronics Co., Ltd. Semiconductor device having a fin
US9583624B1 (en) * 2015-09-25 2017-02-28 International Business Machines Corporation Asymmetric finFET memory access transistor
KR102323943B1 (ko) 2015-10-21 2021-11-08 삼성전자주식회사 반도체 장치 제조 방법
US9997606B2 (en) 2016-09-30 2018-06-12 International Business Machines Corporation Fully depleted SOI device for reducing parasitic back gate capacitance
WO2018125035A1 (en) * 2016-12-27 2018-07-05 Intel Corporation Transistors including final source/drain material processed after replacement gate processing
US10199503B2 (en) 2017-04-24 2019-02-05 International Business Machines Corporation Under-channel gate transistors
CN111737937B (zh) * 2020-07-16 2023-06-23 杰华特微电子股份有限公司 半导体器件建模方法
WO2023133725A1 (zh) * 2022-01-12 2023-07-20 华为技术有限公司 一种晶体管、半导体集成电路
TWI799233B (zh) * 2022-01-24 2023-04-11 南亞科技股份有限公司 具有減少突起的記憶胞的記憶體元件

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050145941A1 (en) * 2004-01-07 2005-07-07 International Business Machines Corporation High performance strained silicon FinFETs device and method for forming same
US20060027870A1 (en) * 2004-08-05 2006-02-09 Satoshi Inaba Semiconductor device and method of manufacturing the same
CN101267001A (zh) * 2007-03-14 2008-09-17 国际商业机器公司 鳍片fet器件及其制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6413802B1 (en) 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6458662B1 (en) * 2001-04-04 2002-10-01 Advanced Micro Devices, Inc. Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed
US6787402B1 (en) * 2001-04-27 2004-09-07 Advanced Micro Devices, Inc. Double-gate vertical MOSFET transistor and fabrication method
US7091566B2 (en) * 2003-11-20 2006-08-15 International Business Machines Corp. Dual gate FinFet
KR100585111B1 (ko) * 2003-11-24 2006-06-01 삼성전자주식회사 게르마늄 채널 영역을 가지는 비평면 트랜지스터 및 그제조 방법
US8227316B2 (en) * 2006-06-29 2012-07-24 International Business Machines Corporation Method for manufacturing double gate finFET with asymmetric halo
JP2008066562A (ja) * 2006-09-08 2008-03-21 Toshiba Corp 半導体装置およびその製造方法
US7855411B2 (en) * 2007-05-25 2010-12-21 Macronix International Co., Ltd. Memory cell
US7795088B2 (en) * 2007-05-25 2010-09-14 Macronix International Co., Ltd. Method for manufacturing memory cell
CN102034865B (zh) 2009-09-30 2012-07-04 中国科学院微电子研究所 半导体器件及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050145941A1 (en) * 2004-01-07 2005-07-07 International Business Machines Corporation High performance strained silicon FinFETs device and method for forming same
US20060027870A1 (en) * 2004-08-05 2006-02-09 Satoshi Inaba Semiconductor device and method of manufacturing the same
CN101267001A (zh) * 2007-03-14 2008-09-17 国际商业机器公司 鳍片fet器件及其制造方法

Also Published As

Publication number Publication date
CN102034865A (zh) 2011-04-27
US8741703B2 (en) 2014-06-03
CN102034865B (zh) 2012-07-04
US20110193164A1 (en) 2011-08-11
US20140011330A1 (en) 2014-01-09
US8552477B2 (en) 2013-10-08

Similar Documents

Publication Publication Date Title
US8741703B2 (en) Method for manufacturing FinFET with improved short channel effect and reduced parasitic capacitance
US20230187447A1 (en) Enhanced channel strain to reduce contact resistance in nmos fet devices
US8710556B2 (en) Semiconductor device comprising a Fin and method for manufacturing the same
US8445340B2 (en) Sacrificial offset protection film for a FinFET device
US7388259B2 (en) Strained finFET CMOS device structures
WO2012100463A1 (zh) 一种形成半导体结构的方法
US20120146142A1 (en) Mos transistor and method for manufacturing the same
WO2011127634A1 (zh) 半导体器件及其制造方法
US20220208986A1 (en) Finfet fabrication methods
US8598595B2 (en) Semiconductor device and method for manufacturing the same
US20150200275A1 (en) Finfet and method for manufacturing the same
CN103824775A (zh) FinFET及其制造方法
WO2013166733A1 (zh) FinFET及其制造方法
US20150380297A1 (en) Method for manufacturing mosfet
WO2013053167A1 (zh) Mosfet及其制造方法
US10998443B2 (en) Epi block structure in semiconductor product providing high breakdown voltage
WO2014131239A1 (zh) 半导体器件及其制造方法
US10892339B2 (en) Gate first technique in vertical transport FET using doped silicon gates with silicide
WO2015054915A1 (zh) 一种非对称超薄soimos晶体管结构及其制造方法
WO2014131240A1 (zh) 半导体器件的制造方法
US9583593B2 (en) FinFET and method of manufacturing the same
CN103985712A (zh) 半导体器件及其制造方法
WO2014071660A1 (zh) 半导体器件及其制造方法
WO2014121540A1 (zh) 半导体器件及其制造方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 12865220

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10819827

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10819827

Country of ref document: EP

Kind code of ref document: A1