CN103904020B - 优化自对准接触孔底部金属硅化物形貌的方法 - Google Patents
优化自对准接触孔底部金属硅化物形貌的方法 Download PDFInfo
- Publication number
- CN103904020B CN103904020B CN201210567505.7A CN201210567505A CN103904020B CN 103904020 B CN103904020 B CN 103904020B CN 201210567505 A CN201210567505 A CN 201210567505A CN 103904020 B CN103904020 B CN 103904020B
- Authority
- CN
- China
- Prior art keywords
- contact hole
- aligned contact
- metal silicide
- self
- district
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 30
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 21
- 239000002184 metal Substances 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 17
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000000137 annealing Methods 0.000 claims abstract description 6
- 239000001257 hydrogen Substances 0.000 claims abstract description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 6
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 6
- 239000011241 protective layer Substances 0.000 claims abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000010410 layer Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910008479 TiSi2 Inorganic materials 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明公开了一种优化自对准接触孔底部金属硅化物形貌的方法，该方法在刻蚀形成接触孔后，成长金属阻挡层前，进行以下工艺步骤：1）在衬底损失区的表面生长一层氧化硅保护层；2）用氮气和氢气进行快速热退火处理；3）去除接触孔底部的氧化硅。本发明通过在衬底损失区域的侧壁上形成氧化硅保护层，避免了自对准接触孔形成时，阻挡层金属Ti与衬底损失区侧壁的Si反应，形成无规则的硅化物延伸，从而保证了半导体器件的性能。
Description
技术领域
本发明涉及集成电路制造领域，特别是涉及一种优化自对准接触孔底部金属硅化物形貌的方法。
背景技术
金属硅化物（silicide）是半导体工艺中不可缺少的重要工艺手段，在降低孔电阻、接触电阻以及提高MOS器件速度上有着重要的用途。在自对准接触孔(SAC-LIC)形成时，通过金属Ti与硅衬底之间的化学反应，我们可以得到TiSi2这种最常用的金属硅化物。为了保证接触孔与衬底（sub）的良好接触，在孔的底部一般都留有一定量的衬底损失区（silicon loss），正是这个衬底损失区让接触孔底部的硅形成了侧壁。但是，在现有的制造工艺中，这个侧壁上是没有针对硅的保护结构的，因此，侧壁会与金属Ti反应。在一些极端的异常情况下，Ti与Si侧壁的反应失控，硅化物区域会在水平方向上无规则地延伸，如图1所示，这会造成MOS器件的性能异常，如图2所示，ID、IB两条曲线重合，即ID、IB电流大小相等，漏电的路径是从器件的漏极到衬底，表示整个电路的失效。
发明内容
本发明要解决的技术问题是提供一种优化自对准接触孔底部金属硅化物形貌的方法，它可以阻止硅化物无规则的横向生长。
为解决上述技术问题，本发明的优化自对准接触孔底部金属硅化物形貌的方法，在刻蚀形成接触孔后，成长金属阻挡层前，包括有以下步骤：
1）在衬底损失区的表面生长一层氧化硅保护层；
2）使用氮气和氢气进行快速热退火处理；
3）去除接触孔底部的氧化硅。
本发明通过在衬底损失区域的侧壁上形成氧化硅保护层，避免了自对准接触孔形成时，阻挡层金属与衬底损失区的侧壁反应，形成无规则的硅化物延伸，从而保证了半导体器件的性能。
附图说明
图1是采用现有工艺形成金属硅化物时，硅化物在接触孔底部横向无规则生长的示意图。
图2是硅化物发生横向延伸的异常MOS器件的NPASS管漏电曲线。其中，ID代表测试时漏极的电流，IB代表测试时衬底的电流。
图3是本发明实施例的金属硅化物的形成方法流程示意图。
图4是硅化物未发生横向延伸的正常MOS器件的NPASS管漏电曲线。其中，ID是漏极的电流，IS是源极的电流。
图中附图标记说明如下：
1：前金属介质层（PMD）
2：硅衬底
3：自对准接触孔
4：衬底损失区
5：氧化层
6：阻挡层
7：金属硅化物
具体实施方式
为对本发明的技术内容、特点与功效有更具体的了解，现结合图示的实施方式，详述如下：
本发明的接触孔制作方法，其具体工艺流程如下：
步骤1，采用现有工艺，通过光刻和刻蚀形成自对准接触孔3，如图3（a）所示，此时，硅衬底2上会有一定的硅缺失，形成衬底损失区4。
步骤2，在900～1050℃下，通入氧气和氮气（氧气:氮气=1:99），快速热退火处理20s，在衬底损失区4的表面生长一层氧化硅，形成氧化层5，如图3（b）所示。
步骤3，在970℃下，同时通入氮气和氢气（氮气:氢气=10:1），快速热退火处理400s，以改变接触孔内各种物质的表面态，消除表面缺陷，增加接触的良好性。
步骤4，常温下使用RF（射频）工艺去除自对准接触孔3正下方底部的氧化硅，仅保留侧壁的氧化硅，如图3（c）所示。
步骤5，采用现有工艺生长金属Ti-TiN阻挡层6（先生长Ti，再生长TiN，两层结构叠加），如图3（d）所示。此时，由于衬底损失区4的侧壁有氧化层5的保护，不会与金属Ti接触，因此，TiSi2金属硅化物只能形成在自对准接触孔3的底部，不会横向无规则地生长。
步骤6，填充金属钨。
上述方法在既不影响原器件结构与性能，又不必对原工艺进行复杂改动的情况下，很好地解决了硅化物横向延伸的问题，使困扰产品的漏电现象得到了解决，如图4所示，ID（漏极电流）、IS（源极电流）两者基本相等，表示漏电路径是从漏极到源极，器件性能正常。
Claims (4)
1.优化自对准接触孔底部金属硅化物形貌的方法，其特征在于，在刻蚀形成接触孔后，成长金属阻挡层前，包括有以下步骤：
1)使用氧气快速热退火工艺在衬底损失区的表面生长一层氧化硅保护层；
2)使用氮气和氢气进行快速热退火处理；
3)采用射频工艺去除接触孔底部的氧化硅。
2.根据权利要求1所述的方法，其特征在于，步骤1)，热退火的温度为900～1050℃，时间为20s。
3.根据权利要求1所述的方法，其特征在于，步骤2)，氮气与氢气的比例为10:1。
4.根据权利要求1或4所述的方法，其特征在于，步骤2)，热退火处理的温度为970℃，处理时间为400s。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210567505.7A CN103904020B (zh) | 2012-12-24 | 2012-12-24 | 优化自对准接触孔底部金属硅化物形貌的方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210567505.7A CN103904020B (zh) | 2012-12-24 | 2012-12-24 | 优化自对准接触孔底部金属硅化物形貌的方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103904020A CN103904020A (zh) | 2014-07-02 |
| CN103904020B true CN103904020B (zh) | 2016-08-17 |
Family
ID=50995283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210567505.7A Active CN103904020B (zh) | 2012-12-24 | 2012-12-24 | 优化自对准接触孔底部金属硅化物形貌的方法 |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103904020B (zh) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110579494B (zh) * | 2019-09-19 | 2021-12-17 | 长江存储科技有限责任公司 | 一种金属硅化物的表征方法 |
| CN110739269B (zh) * | 2019-10-25 | 2020-11-20 | 武汉新芯集成电路制造有限公司 | 半导体器件及其形成方法 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101924068A (zh) * | 2009-06-11 | 2010-12-22 | 中芯国际集成电路制造(上海)有限公司 | 电阻存储器、含有电阻存储器的集成电路的制作方法 |
| CN102157493A (zh) * | 2010-02-11 | 2011-08-17 | 上海华虹Nec电子有限公司 | 金属塞及其制造方法 |
| CN102437088A (zh) * | 2010-09-29 | 2012-05-02 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4534164B2 (ja) * | 2006-07-25 | 2010-09-01 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
-
2012
- 2012-12-24 CN CN201210567505.7A patent/CN103904020B/zh active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101924068A (zh) * | 2009-06-11 | 2010-12-22 | 中芯国际集成电路制造(上海)有限公司 | 电阻存储器、含有电阻存储器的集成电路的制作方法 |
| CN102157493A (zh) * | 2010-02-11 | 2011-08-17 | 上海华虹Nec电子有限公司 | 金属塞及其制造方法 |
| CN102437088A (zh) * | 2010-09-29 | 2012-05-02 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103904020A (zh) | 2014-07-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7649263B2 (en) | Semiconductor device | |
| CN101211781A (zh) | 自对准金属硅化物的制造方法 | |
| CN103904020B (zh) | 优化自对准接触孔底部金属硅化物形貌的方法 | |
| CN105448730A (zh) | 半导体结构及其形成方法 | |
| CN104733374A (zh) | 金属互连结构及其形成方法 | |
| CN103000579A (zh) | 一种半导体器件及其制备方法 | |
| CN104217990A (zh) | 一种形成接触孔的方法 | |
| CN104752205A (zh) | 半导体器件及其形成方法 | |
| Lu et al. | Study of high-tech process furnace using inherently safer design strategies (III) advanced thin film process and reduction of power consumption | |
| KR100780598B1 (ko) | 벌브형 리세스 게이트를 갖는 반도체 소자의 제조 방법 | |
| CN105097477A (zh) | 一种镍硅化物的制作方法 | |
| CN103187254B (zh) | 一种双多晶硅栅的制造方法 | |
| CN101692425B (zh) | 一种esd保护的设计方法 | |
| CN102569089B (zh) | 半导体器件的形成方法 | |
| CN102332400B (zh) | 半导体器件的形成方法 | |
| US20120156873A1 (en) | Method for restricting lateral encroachment of metal silicide into channel region | |
| CN102867743B (zh) | 改善掺杂与非掺杂多晶硅栅极刻蚀形貌差异的方法 | |
| CN103165453B (zh) | 高介电金属栅mos及其制造方法 | |
| US9620619B2 (en) | Borderless contact structure | |
| CN100547738C (zh) | 栅介电层的制造方法 | |
| CN103700644A (zh) | 基于tsv工艺的转接板深槽电容及其制造方法 | |
| CN105226002A (zh) | 自对准沟槽型功率器件及其制造方法 | |
| CN107706188A (zh) | 外围电路接触孔形成方法、三维存储器及电子设备 | |
| CN102891112B (zh) | 改善双栅cmos多晶硅耗尽的方法以及双栅cmos | |
| CN104425364B (zh) | 连接线的形成方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |