TWI715218B - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TWI715218B
TWI715218B TW108135103A TW108135103A TWI715218B TW I715218 B TWI715218 B TW I715218B TW 108135103 A TW108135103 A TW 108135103A TW 108135103 A TW108135103 A TW 108135103A TW I715218 B TWI715218 B TW I715218B
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Taiwan
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gate
region
work function
metal material
gate stack
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TW108135103A
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TW202027278A (zh
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吳仲強
蔡昕翰
李威縉
李家慶
鍾鴻欽
洪正隆
李達元
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台灣積體電路製造股份有限公司
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Abstract

提供具有不同臨界電壓的半導體元件和其製造方法。在實施例中，透過在取代閘極製程中的個別閘極堆疊內不同材料的移除和放置，來調節個別半導體元件的臨界電壓，其中移除和放置有助於保持整體製程寬裕度，大到足以允許填充材料完全填充。

Description

半導體元件及其製造方法
本發明實施例是關於半導體元件的形成方法，特別是關於臨界電壓的調節。
半導體元件被使用在各種電子應用中，例如，個人電腦、行動電話、數位相機、和其他電子器材。通常藉由於半導體基底上方依序沉積絕緣或介電層、導電層、和半導體層材料，以及使用微影來圖案化各種材料層，以形成電路元件和其上方部件來製造半導體元件。
藉由不斷的減少最小特徵尺寸，使得更多部件可被整合進入給定的面積空間中，半導體產業因而能持續改善各種電子部件(例如，電晶體、二極體、電阻、電容等)的整合密度。然而，在減少最小特徵尺寸的同時，需要解決額外發生的問題。
一種半導體元件的製造方法，方法包括：沉積閘極介電質於第一區、第二區、第三區、和第四區上方；沉積第一金屬材料於第一區、第二區、 第三區、和第四區上方；沉積第一功函數層於第一區、第二區、第三區、和第四區上方；從第三區移除第一功函數層；在移除第一功函數層之後，沉積第二功函數層於第一區、第二區、第三區、和第四區上方，第二功函數層與第一功函數層不同；從第一區和第二區移除第二功函數層；從第一區移除第一功函數層；以及在移除第一功函數層之後，沉積填充材料於第一區、第二區、第三區、和第四區上方。
一種半導體元件的製造方法，方法包括：沉積第一複數個閘極材料於第一區和第二區上方；藉由移除第一區的第一複數個閘極材料的第一閘極材料，來調節由第一複數個閘極材料所形成的多個電晶體之中的第一電晶體的第一臨界電壓；以及藉由形成第二閘極材料於第一區和第二區上方，和由第二區移除第二閘極材料，來調節由第一複數個閘極材料所形成的多個電晶體之中的第二電晶體的第二臨界電壓，第一閘極材料與第二閘極材料不同，多個電晶體之中的第一電晶體為第一PMOS電晶體，而多個電晶體之中的第二電晶體為第二PMOS電晶體。
一種半導體元件，包括：第一閘極堆疊，於第一半導體鰭片上方，第一閘極堆疊包括第一金屬材料；第二閘極堆疊，於第二半導體鰭片上方，第二閘極堆疊包括第一金屬材料和與第一金屬材料不同的第一P金屬材料；第三閘極堆疊，於第三半導體鰭片上方，第三閘極堆疊包括第一金屬材料和與第一金屬材料不同的第二P金屬材料；第四閘極堆疊，於第四半導體鰭片上方，第四閘極堆疊包括第一金屬材料、第一P金屬材料、和第二P金屬材料；以及其中第一閘極堆疊、第二閘極堆疊、第三閘極堆疊、和第四閘極堆疊各包括N金屬材料，在第一閘極堆疊中的N金屬材料與第一金屬材料物理接觸，在第二閘極堆疊中的 N金屬材料與第一P金屬材料物理接觸，在第三閘極堆疊中的N金屬材料與第二P金屬材料物理接觸，而在第四閘極堆疊中的N金屬材料與第二P金屬材料物理接觸。
100:半導體元件
101:基底
103:第一溝槽
105:第一隔離區
107:鰭片
109:虛置閘極介電質
111:虛置閘極電極
113:第一間隔物
115:堆疊
201:源極/汲極區
203:層間介電層
301:界面層
302:第一區
303:第一介電材料
304:第二區
305:第一金屬材料
306:第三區
307:第一P金屬功函數層
308:第四區
401:第一光阻
501:第二P金屬功函數層
601:第二光阻
701:第三光阻
802:第一N金屬功函數層
804:黏著層
806:填充材料
901:蓋層
902:第一閘極堆疊
903:第一電晶體
904:第二閘極堆疊
905:第二電晶體
906:第三閘極堆疊
907:第三電晶體
908:第四閘極堆疊
909:第四電晶體
H1:第一高度
H2:第二高度
H3:第三高度
H4:第四高度
T1:第一厚度
T2:第二厚度
T3:第三厚度
T4:第四厚度
T5:第五厚度
T6:第六厚度
T7:第七厚度
Vt1:第一臨界電壓
Vt2:第二臨界電壓
Vt3:第三臨界電壓
Vt4:第四臨界電壓
W1:第一寬度
W2:第二寬度
W3:第三寬度
W4:第四寬度
以下將配合所附圖式詳述本揭露之各面向。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製。事實上，可任意地放大或縮小元件的尺寸，以清楚地表現出本揭露的特徵。
第1圖是根據一些實施例繪示了半導體鰭片形成的透視圖。
第2圖是根據一些實施例繪示了源極/汲極區的形成。
第3圖是根據一些實施例繪示了閘極堆疊材料的形成。
第4圖是根據一些實施例繪示了第一阻障層的移除製程。
第5圖是根據一些實施例繪示了第二阻障層的沉積。
第6圖是根據一些實施例繪示了第二阻障層的移除製程。
第7圖是根據一些實施例繪示了第一阻障層的另一個移除製程。
第8圖是根據一些實施例繪示了填充材料的沉積。
第9圖是根據一些實施例繪示了蓋層的形成。
以下揭露提供了許多的實施例或範例，用於實施本發明的不同部件。組件和配置的具體範例描述如下，以簡化本發明實施例。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例來說，敘述中提及第一部件形成於 第二部件之上，可包括形成第一和第二部件直接接觸的實施例，也可包括額外的部件形成於第一和第二部件之間，使得第一和第二部件不直接接觸的實施例。另外，本發明可在各種範例中重複元件符號及/或字母。這樣重複是為了簡化和清楚的目的，其本身並非主導所討論各種實施例及/或配置之間的關係。
再者，此處可使用空間上相關的用語，如「在...之下」、「下方的」、「低於」、「在...上方」、「上方的」和類似用語可用於此，以便描述如圖所示一元件或部件和其他元件或部件之間的關係。這些空間用語企圖包括使用或操作中的裝置的不同方位。當裝置被轉至其他方位(旋轉90°或其他方位)，則在此所使用的空間相對描述可同樣依旋轉後的方位來解讀。
此刻將依據特定範例描述實施例，包括在5nm或3nm技術節點中具有多重臨界電壓的鰭式場效電晶體元件。然而，實施例並非限定於此處所提供的範例，而是可實施其概念在各種各樣的實施例中。
參考第1圖，繪示了半導體元件100，如一鰭式場效電晶體元件的透視圖。在一實施例中，半導體元件100包括基底101和第一溝槽103。基底101可以是矽基底，儘管也能使用其他的基底，如絕緣層上半導體(semiconductor-on-insulator,SOI)、絕緣層上應變半導體(strained SOI)、和絕緣層上矽鍺(silicon germanium on insulator)。基底101可以是P型半導體，儘管在其他實施例，基底101也能是N型半導體。
可形成第一溝槽103，作為最終形成第一隔離區105的初始步驟。可使用遮罩層(未單獨繪示於第1圖)以及合適的蝕刻製程來形成第一溝槽103。舉例來說，遮罩層可以是包括氮化矽的硬遮罩，其形成可透過如化學氣相沉積(chemical vapor deposition,CVD)的製程，儘管亦可利用其他材料(如氧化物、 氮氧化物、碳化矽、其組合、或其他類似材料)和其他製程(如電漿輔助化學氣相沉積(plasma enhanced chemical vapor deposition,PECVD)、低壓化學氣相沉積(low pressure chemical vapor deposition,LPCVD)、或甚至形成氧化矽後進行氮化反應)。一旦形成後，可透過合適的光微影製程來圖案化遮罩層，以露出基底101會被移除的部分來形成第一溝槽103。
然而，如在本發明所屬技術領域中具有通常知識者會認知，上述用來形成遮罩層的製程和材料並非可用來保護部分基底101同時露出基底101其他部分以形成第一溝槽103的唯一方法。任何合適製程(如圖案化後並顯影完的光阻)皆可被用來露出基底101會被移除的部分，以形成第一溝槽103。所有的方法均完全意欲涵蓋在本實施例的範圍中。
一旦形成了並圖案化遮罩層，則在基底101中形成第一溝槽103。可透過一個合適的製程，如反應離子蝕刻(reactive ion etching,RIE)來移除基底101的暴露部分，以在基底101中形成第一溝槽103，儘管任何合適的製程皆可被使用。在一實施例中，可形成第一溝槽103，其具有從基底101表面下低於約5000Å的第一深度，如約2500Å。
不過，如在本發明所屬技術領域中具有通常知識者會認知，上述用來形成第一溝槽103的製程僅僅是一個可能使用的製程，而並非意指為唯一的實施例。反而，任何可形成第一溝槽103的合適製程皆可被利用，且可使用任何合適製程，包括任意數量的遮罩和移除步驟。
除了形成第一溝槽103之外，遮罩和蝕刻製程從基底101未被移除的部分另外形成鰭片107。為了方便起見，鰭片107在圖中，從基底101以虛線被分開繪示，儘管可呈現或可不呈現分開繪示的物理跡象。如下所述，可使用這 些鰭片107來形成複數閘極的鰭式場效電晶體的通道區。即便第1圖僅僅繪示了從基底101形成的3個鰭片107，任意數量的鰭片107皆可被利用。
可形成鰭片107，其寬度於基底101表面上介於約5nm和80nm之間，如約30nm。此外，可將鰭片107與彼此隔開至介於約10nm和100nm之間的距離，如約50nm。藉由此方式隔開鰭片107，各個鰭片107可形成分開的通道區，卻仍與彼此距離夠近來分享一共用閘極(進一步於下描述)。
一旦形成了第一溝槽103和鰭片107，可以介電材料填充第一溝槽103，並可在第一溝槽103內凹蝕介電材料來形成第一隔離區105。介電材料可以是氧化物材料、高密度電漿(high-density plasma,HDP)氧化物、或其他類似材料。在第一溝槽103可選的清洗和內襯之後，可使用化學氣相沉積方法(例如，HARP製程)、高密度電漿化學氣相沉積方法、或其他在本發明所屬技術領域習知的合適形成方法來形成介電材料。
第一溝槽103的填充，可藉由將介電材料過渡填充第一溝槽103和基底101，然後透過如化學機械拋光(chemical mechanical polishing,CMP)、蝕刻法、其組合、或其他類似方法來移除第一溝槽103和鰭片107外的過多材料。在一實施例中，移除製程將任何位於鰭片107上方的介電材料移除，使得介電材料的移除會暴露鰭片107表面以進行進一步製程步驟。
一旦以介電材料填充了第一溝槽103，則可將介電材料從鰭片107表面凹蝕掉。可進行凹蝕來暴露至少一部分與鰭片107頂面相鄰的側壁。可使用濕蝕刻，藉由將鰭片107頂面浸入如HF的蝕刻劑來凹蝕介電材料，儘管其他蝕刻劑(如H2)和其他方法(如反應離子蝕刻、具有如NH3/NF3的蝕刻劑的乾蝕刻、化學氧化物移除、或乾化學清洗)皆可被使用。可自鰭片107表面凹蝕介電材料 至具有介於約50Å和500Å之間的距離，如約400Å。此外，凹蝕也可移除任何位於鰭片107上方殘留的介電材料來確保鰭片107暴露於後續製程。
然而，如在本發明所屬技術領域中具有通常知識者會認知，上述步驟僅是用來填充和凹蝕介電材料的整體製程流程的一部分。舉例來說，也可利用內襯步驟(lining step)、清洗步驟、退火步驟、間隙填充步驟、其組合、或其他類似步驟，以介電材料來形成和填充第一溝槽103。這些可能使用的製程步驟都完全意欲涵蓋在本實施例的範圍內。
在形成了第一隔離區105之後，可於各鰭片107上方形成虛置閘極介電質109、於虛置閘極介電質109上方的虛置閘極電極111、和第一間隔物113。在一實施例中，可藉由熱氧化、化學氣相沉積、濺鍍法、或其他在本發明所屬技術領域習知並用於形成閘極介電質的方法來形成虛置閘極介電質109。取決於閘極介電質形成的技術，在鰭片107頂部上的虛置閘極介電質109的厚度可與在鰭片107側壁上的虛置閘極介電質109的厚度不同。
虛置閘極介電質109可包括如二氧化矽或氮氧化矽的材料，其具有從約3Å至100Å的厚度，如約10Å。可由高介電常數(high k)材料(例如，具有相對介電常數約大於5，如氧化鑭(La2O3)、氧化鋁(Al2O3)、二氧化鉿(HfO2)、氮氧化鉿(HfON)、或二氧化鋯(ZrO2)、或其組合)，具有約0.5Å至100Å的等值氧化物厚度(如約10Å或更小)來形成虛置閘極介電質109。此外，可將二氧化矽、氮氧化矽、及/或高介電常數材料的任意組合，用於虛置閘極介電質109。
虛置閘極電極111可包括導電或非導電材料，且可選自包括多晶矽、Al、Cu、AlCu、W、Ti、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、Ta、TaN、Co、Ni、其組合、或其他類似材料的族群。可藉由化學氣相沉積、濺鍍 沉積、或其他在本發明所屬技術領域習知並用於沉積導電材料的技術來沉積虛置閘極電極111。虛置閘極電極111的厚度可在約5Å至200Å的範圍中。虛置閘極電極111的頂面可具有非平坦的頂面，並可在圖案化虛置閘極電極111或閘極蝕刻前進行平坦化。在此刻，可導入或可不導入離子於虛置閘極電極111中。可藉由例如離子植入方式來導入離子。
一旦形成後，可圖案化虛置閘極介電質109和虛置閘極電極111，於鰭片107上方形成一系列的堆疊115。堆疊115定義多個位在鰭片107兩側上，並於虛置閘極介電質109下方的通道區。可藉由使用例如在本發明所屬技術領域習知的沉積和光微影方式沉積和圖案化閘極遮罩(未單獨繪示於第1圖)來在虛置閘極電極111上形成堆疊115。閘極遮罩可納入常用的掩蔽法和犧牲材料，例如(但並未限定於)矽氧化物(silicon oxide)、矽氧氮化物(silicon oxynitride)、矽氧碳氮化物(SiCON)、矽碳化物(SiC)、矽氧碳化物(SiOC)、及/或矽氮化物(silicon nitride)，且可沉積至介於約5Å和200Å之間的厚度。可使用乾蝕刻製程來蝕刻虛置閘極電極111和虛置閘極介電質109，以形成圖案化的堆疊115。
一旦圖案化堆疊115，可形成第一間隔物113。可在堆疊115的兩側上形成第一間隔物113。通常藉由在先前形成的結構上毯覆式沉積(blanket deposit)間隔層(未單獨繪示於第1圖)來形成第一間隔物113。間隔層可包括氮化矽(SiN)、氧氮化物(oxynitride)、碳化矽(SiC)、氧氮化矽(SiON)、氧碳氮化矽(SiOCN)、氧碳化矽(SiOC)、氧化物(oxide)、或其他類似材料，並可藉由用以形成當層的方法(如化學氣相沉積、電漿輔助化學氣相沉積、濺鍍法、或其他在本發明所屬技術領域習知的方法)來形成間隔層。間隔層可 包括具有不同蝕刻特性的不同材料，或與在第一隔離區105內的介電材料相同的材料。然後，可圖案化第一間隔物113，藉由例如一或多次蝕刻，從結構的水平面上，移除間隔層來形成第一間隔物113。
在一實施例中，可形成具有介於約5Å和500Å之間厚度的第一間隔物113。此外，一旦形成了第一間隔物113，鄰近於其中一個堆疊115的第一間隔物113可與鄰近於另一個堆疊115的第一間隔物113隔開至約介於5nm和200nm之間的距離，如約20nm。然而，任何合適的厚度和距離皆可被利用。
第2圖繪示了從沒有被堆疊115和第一間隔物113保護的區域上移除鰭片107，以及源極/汲極區201的再成長。可藉由反應離子蝕刻(或任何其他合適的移除製程)，使用堆疊115和第一間隔物113作為硬遮罩，自沒有被堆疊115和第一間隔物113保護的區域進行鰭片107的移除。可持續移除直到鰭片107與第一隔離區105的表面共面(如圖所示)，或低於第一隔離區105的表面。
一旦移除了鰭片107的這些部分，放置並圖案化硬遮罩(未單獨繪示)來覆蓋虛置閘極電極111以防止其增長，而可再成長源極/汲極區201來與各個鰭片107接觸。在一實施例中，可再成長源極/汲極區201，而在一些實施例中，可再成長源極/汲極區201來形成應力源(stressor)，其應力源將會傳遞應力至位於堆疊115下方的鰭片107的通道區。在一實施例中，其中鰭片107包括矽，而鰭式場效電晶體為P型元件，可透過選擇性磊晶製程，以例如矽或具有與通道區不同晶格常數的鍺化矽的材料來再成長源極/汲極區201。磊晶成長製程可使用如矽烷(silane)、二氯矽烷(dichlorosilane)、鍺烷(germane)、或其他類似材料的前驅物(precursor)，並可持續介於約5分鐘和120分鐘之間，如30分鐘。
在一實施例中，可形成源極/汲極區201至具有介於約5Å和1000Å 之間的厚度，和於第一隔離區105上方具有介於約10Å和500Å之間的高度，如約200Å。在此實施例中，可在第一隔離區105的上表面之上形成源極/汲極區201至具有介於約5nm和250nm之間的高度，如約100nm。然而，任何合適的高度皆可被利用。
一旦形成源極/汲極區201，可藉由植入合適摻質以補足鰭片107的摻質來植入摻質於源極/汲極區201中。舉例來說，可植入P型摻質(如硼、鎵、銦、或類似材料)來形成PMOS元件。或者，可植入N型摻質(如磷、砷、銻、或其他類似材料)來形成NMOS元件。可使用堆疊115和第一間隔物113作為遮罩來植入這些摻質。應注意的是，在本發明所屬技術領域中具有通常知識者會發現，可使用許多其他製程、步驟、或類似方式來植入摻質。舉例來說，在本發明所屬技術領域中具有通常知識者會發現，可適用各種組合的間隔物和襯層來進行複數個植入過程，以形成具有特定形狀或適用於特定目的之特性的源極/汲極區。可使用這些製程的任一種來植入摻質，而上述並非用以限定本實施例於上所呈現的步驟中。
此外，於此刻，移除在源極/汲極區201的形成中覆蓋虛置閘極電極111的硬遮罩。在一實施例中，可使用例如針對硬遮罩材料具有選擇性的濕蝕刻製程或乾蝕刻製程來移除硬遮罩。然而，任何合適的移除製程皆可被利用。
第2圖也繪示了，於堆疊115和源極/汲極區201上方所形成的層間介電層(inter-layer dielectric layer,ILD)203(在第2圖中用虛線繪示，以便更清楚繪示於下方的結構)。層間介電層203可包括如硼磷矽酸玻璃(boron phosphorous silicate glass,BPSG)的材料，儘管任何合適的介電質皆可被使用。可使用如電漿輔助化學氣相沉積的製程來形成層間介電層203，儘管其他製程 (如低壓化學氣相沉積)可被替代地使用。可形成層間介電層203至介於約100Å和3000Å之間的厚度。一旦形成後，可使用如化學機械拋光的平坦化製程，將層間介電層203與第一間隔物113平坦化，儘管任何合適的製程皆可被利用。
第3圖是沿著第2圖的3-3’線段所繪示的剖面示意圖，以便更佳繪示虛置閘極電極111和虛置閘極介電質109材料的移除和替換，以作為具有複數層的第一閘極堆疊902(未繪示於第3圖中，但依據第9圖於下繪示和相關描述)。此外在第3圖中，除了第一閘極堆疊902繪示於基底101的第一區302內，也繪示了基底101的第二區304(作為第二閘極堆疊904)、基底101的第三區306(作為第三閘極堆疊906)、和基底101的第四區308(作為第四閘極堆疊908)。在一實施例中，第一閘極堆疊902可作為具有第一臨界電壓Vt1的第一電晶體903的閘極堆疊(例如第一NMOS鰭式場效電晶體)，而第二閘極堆疊904可作為第二電晶體905的閘極堆疊(例如第二NMOS鰭式場效電晶體)，其具有與第一臨界電壓Vt1不同的第二臨界電壓Vt2。此外，第三閘極堆疊906可作為具有第三臨界電壓Vt3的第三電晶體907的閘極堆疊(例如第一PMOS鰭式場效電晶體)，而第四閘極堆疊908可作為第四電晶體909的閘極堆疊(例如第二PMOS鰭式場效電晶體)，其具有與第三臨界電壓Vt3不同的第四臨界電壓Vt4。然而，任何合適的元件皆可被利用。
在一實施例中，可使用例如一或多個濕蝕刻或乾蝕刻製程，其利用針對虛置閘極電極111和虛置閘極介電質109的材料具有選擇性的蝕刻劑，來移除虛置閘極電極111和虛置閘極介電質109。然而，任何一或多個合適的移除製程皆可被利用。
一旦移除了虛置閘極電極111和虛置閘極介電質109，可藉由沉積 一系列膜層來開始第一閘極堆疊902、第二閘極堆疊904、第三閘極堆疊906、和第四閘極堆疊908的形成製程。在一實施例中，一系列的膜層可包括界面層301、第一介電材料303、第一金屬材料305、和第一P金屬功函數層307。
可選地，可在形成第一介電材料303前形成界面層301。在一實施例中，界面層301的材料可以是如透過原位蒸氣產生(in situ steam generation,ISSG)製程所形成的二氧化矽。在另一個實施例中，界面層301可以是高介電常數材料(如二氧化鉿(HfO2)、矽氧化鉿(HfSiO)、矽氧氮化鉿(HfSiON)、氧化鉿鉭(HfTaO)、氧化鉿鈦(HfTiO)、氧化鉿鋯(HfZrO)、氧化鑭(LaO)、氧化鋯(ZrO)、氧化鉭(Ta2O5)、其組合、或其他類似材料)，具有介於約5Å和20Å之間的第一厚度T1，如約10Å。然而，任何合適的形成材料或製程皆可被利用。
一旦形成界面層301，可形成第一介電材料303作為於界面層301上方的蓋層。在一實施例中，第一介電材料303為高介電常數材料(如二氧化鉿(HfO2)、矽氧化鉿(HfSiO)、矽氧氮化鉿(HfSiON)、氧化鉿鉭(HfTaO)、氧化鉿鈦(HfTiO)、氧化鉿鋯(HfZrO)、氧化鑭(LaO)、氧化鋯(ZrO)、氧化鉭(Ta2O5)、其組合、或其他類似材料)，透過如原子層沉積(atomic layer deposition)、化學氣相沉積、或其他類似方法的製程來沉積第一介電材料303。可沉積第一介電材料303至具有介於約5Å和200Å之間的第二厚度T2，儘管任何合適的材料和厚度皆可被利用。
可形成第一金屬材料305，與第一介電材料303相鄰，作為阻障層，並可自，如TaN、Ti、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、Ru、Mo、WN、其他金屬氧化物、金屬氮化物、金屬矽化物、過渡金屬氧化物、過 渡金屬氮化物、過渡金屬矽化物、金屬的氧氮化物、金屬鋁酸鹽、鋯矽化物、鋯鋁酸鹽、其組合、或其他類似材料來形成。可使用如原子層沉積、化學氣相沉積、濺鍍法、或其他類似的沉積製程來沉積第一金屬材料305，至介於約5Å和200Å之間的第三厚度T3，儘管任何合適的沉積製程和厚度皆可被利用。
可形成第一P金屬功函數層307，與第一金屬材料305相鄰，而在一個特別的實施例中，可與第一金屬材料305相似。舉例來說，可自，如TiN、Ti、TiAlN、TaC、TaCN、TaSiN、TaSi2、NiSi2、Mn、Zr、ZrSi2、TaN、Ru、Al、Mo、MoSi2、WN、其他金屬氧化物、金屬氮化物、金屬矽化物、過渡金屬氧化物、過渡金屬氮化物、過渡金屬矽化物、金屬的氧氮化物、金屬鋁酸鹽、鋯矽化物、鋯鋁酸鹽、其組合、或其他類似的金屬材料來形成第一P金屬功函數層307。此外，可使用如原子層沉積、化學氣相沉積、濺鍍法、或其他類似的沉積方法來沉積第一P金屬功函數層307至介於約5Å和200Å之間的第四厚度T4，儘管任何合適的沉積製程和厚度皆可被利用。
第4圖繪示了從第三區306移除第一P金屬功函數層307，但未從第一區302、第二區304、和第四區308移除第一P金屬功函數層307。在一實施例中，可藉由放置第一光阻401於第一區302、第二區304、和第四區308上方來啟動移除。一旦就位，可接著圖案化第一光阻401來暴露第三區306，而不暴露第一區302、第二區304、和第四區308。圖案化的進行可將第一光阻401暴露於圖案化的能量源來調整第一光阻401的物理性質，接著塗覆顯影劑來移除第一光阻401於第三區306上方的部分，而保留第一光阻401於第一區302、第二區304、和第四區308上方作保護。
一旦在第三區306中暴露了第一P金屬功函數層307，可移除在第 三區306中的第一P金屬功函數層307。在一實施例中，可利用一或多個蝕刻製程(如針對第一P金屬功函數層307的材料(例如氮化鈦)有選擇性的濕蝕刻製程或乾蝕刻製程)，在第三區306中移除第一P金屬功函數層307，且其製程停止於下方的第一金屬材料305，而未顯著的移除第一金屬材料305的材料(例如氮化鉭)。然而，任何合適的移除製程皆可被利用。
第5圖繪示了，一旦移除了第一P金屬功函數層307，可於第一區302、第二區304、和第四區308上方移除第一光阻401。在一實施例中，可使用如灰化製程，使第一光阻401的溫度增加到經歷熱分解(thermal decomposition)且可被移除的溫度來移除第一光阻401。然而，任何其他合適的製程皆可被利用來移除第一光阻401。
第5圖另外繪示了，一旦移除了第一光阻401，可於第一區302、第二區304、第三區306、和第四區308上方沉積第二P金屬功函數層501。在一實施例中，第二P金屬功函數層501可以是具有與第一P金屬功函數層307的材料(例如氮化鈦)相似或較高功函數的金屬，也和第一P金屬功函數層307的材料針對蝕刻製程一樣的高選擇比。在一實施例中，其中使用具有如NH4OH或DIO3的濕蝕刻劑來圖案化第二P金屬功函數層501，且第一P金屬功函數層307為氮化鈦，第二P金屬功函數層501的材料可具有大於500的選擇比。然而，任何合適的選擇比皆可被利用。
在特別的實施例中，第二P金屬功函數層501的材料可以為鎢基材料，如鎢、鎢氮化物(tungsten nitride,WNx)、鎢碳氮化物(tungsten carbide nitride,WCxNy)、鎢氧化物(tungsten oxide,WOx)、其組合、或其他類似材料。在另一個實施例中，第二P金屬功函數層501可以是鉬基材料，如鉬、鉬氮化物 (molybdenum nitride,MoNx)、其組合、或其他類似材料。而在另一個實施例中，第二P金屬功函數層501可以是金、鉑、鈀、其組合、或其他類似材料。然而，任何合適的材料皆可被利用。
在一實施例中，可使用如原子層沉積、化學氣相沉積、濺鍍法、或其他類似的沉積方法來沉積第二P金屬功函數層501。此外，可沉積第二P金屬功函數層501至介於約5Å和200Å之間的第五厚度T5，儘管任何合適的沉積製程或厚度皆可被利用。
第6圖繪示了，一旦於第一區302、第二區304、第三區306、和第四區308上方沉積了第二P金屬功函數層501，從第一區302和第二區304移除第二P金屬功函數層501。在一實施例中，可藉由放置第二光阻601於第一區302、第二區304、第三區306、和第四區308上方來啟動移除。一旦就位，可接著圖案化第二光阻601來暴露第一區302和第二區304，而不暴露第三區306和第四區308。圖案化的進行可將第二光阻601暴露於圖案化的能量源來調整第二光阻601的物理性質，接著塗覆顯影劑來移除第二光阻601於第一區302和第二區304上方的部分，而保留第二光阻601於第三區306和第四區308上方作保護。
一旦在第一區302和第二區304中暴露了第二P金屬功函數層501，可移除在第一區302和第二區304中的第二P金屬功函數層501。在一實施例中，可利用一或多個蝕刻製程(如針對第二P金屬功函數層501的材料具有選擇性的濕蝕刻製程或乾蝕刻製程)，在第一區302和第二區304中移除第二P金屬功函數層501，且其製程停止於下方的第一P金屬功函數層307而未顯著的移除第一P金屬功函數層307的材料。然而，任何合適的移除製程皆可被利用。
第7圖繪示了，一旦移除了第二P金屬功函數層501，可於第三區 306和第四區308上方移除第二光阻601。在一實施例中，可使用如灰化製程，使第二光阻601的溫度增加到經歷熱分解且可被移除的溫度來移除第二光阻601。然而，任何其他合適的製程皆可被利用來移除第二光阻601。
第7圖另外繪示了，一旦移除了第二光阻601，可從第一區302移除第一P金屬功函數層307。在一實施例中，可藉由放置第三光阻701於第一區302、第二區304、第三區306、和第四區308上方來啟動移除。一旦就位，可接著圖案化第三光阻701來暴露第一區302，而不暴露第二區304、第三區306、和第四區308。圖案化的進行可將第三光阻701暴露於圖案化的能量源來調整第三光阻701的物理性質，接著塗覆顯影劑來移除第三光阻701於第一區302上方的部分，而保留第三光阻701於第二區304、第三區306、和第四區308上方作保護。
一旦在第一區302中暴露了第一P金屬功函數層307，可在第一區302中移除第一P金屬功函數層307。在一實施例中，可利用一或多個蝕刻製程(如針對第一P金屬功函數層307的材料具有選擇性的濕蝕刻製程或乾蝕刻製程)，在第一區302中移除第一P金屬功函數層307，且其製程停止於下方的第一金屬材料305而未顯著的移除第一金屬材料305的材料。然而，任何合適的移除製程皆可被利用。
第8圖繪示了第三光阻701的移除和第一N金屬功函數層802、黏著層804、填充材料806的沉積。在一實施例中，可使用如灰化製程，使第三光阻701的溫度增加到經歷熱分解且可被移除的溫度，於第二區304、第三區306、和第四區308上方移除第三光阻701。然而，任何其他合適的製程皆可被利用來移除第三光阻701。
一旦移除了第三光阻701，可沉積第一N金屬功函數層802。在一 實施例中，第一N金屬功函數層802可以是Ti、Ag、Al、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、其他合適的N型功函數材料、或其組合的材料。舉例來說，可使用如原子層沉積、化學氣相沉積、或其他類似方法來沉積第一N金屬功函數層802，至介於約20Å和50Å之間的第六厚度T6，如約30Å。然而，任何合適的材料和製程皆可被利用來形成第一N金屬功函數層802。
一旦形成了第一N金屬功函數層802，可形成黏著層804來幫助貼和上方的填充材料806與下方的第一N金屬功函數層802，並對填充材料806的形成提供了成核層。在一實施例中，黏著層804可以是如氮化鈦(titanium nitride)的材料，或可與第一N金屬功函數層802相似的材料，並可使用如原子層沉積的類似製程來形成至介於約10Å和100Å之間的第七厚度T7，如約50Å。然而，任何合適的材料和製程皆可被利用。
一旦形成了黏著層804，即可沉積填充材料806來填充使用黏著層804作為開口的剩下部分。然而，利用第二P金屬功函數層501，代替單純地額外沉積第一P金屬功函數層307，可使用了較少數量的膜層來獲得所欲之臨界電壓的調節(於下進一步描述)，而後續將被填充材料806的沉積所填充的部分則維持較大的寬度。舉例來說，在第一區302中，在黏著層804沉積之後的剩餘開口可具有介於約10Å和50Å之間第一寬度W1，如約30Å。相似地，在第二區304中，在黏著層804沉積之後的剩餘開口可具有介於約10Å和40Å之間的第二寬度W2，如約20Å。在第三區306中，在黏著層804沉積之後的剩餘開口可具有介於約10Å和40Å之間的第三寬度W3，如約15Å。最後，在第四區308中，在黏著層804沉積之後的剩餘開口可具有介於約10Å和40Å之間的第四寬度W4，如約15Å。
此外，由於在第一區302、第二區304、第三區306、和第四區308 中所具有不同數量的膜層，在填充材料806的沉積中，各開口可具有不同高度。舉例來說，在第一區302中，在黏著層804沉積之後的剩餘開口可具有介於約60nm和100nm之間的第一高度H1，如約80nm。相似地，在第二區304中，在黏著層804沉積之後的剩餘開口可具有介於約60nm和100nm之間的第二高度H2，如約80nm。在第三區306中，在黏著層804沉積之後的剩餘開口可具有介於約60nm和100nm之間的第三高度H3，如約80nm。最後，在第四區308中，在黏著層804沉積之後的剩餘開口可具有介於約60nm和100nm之間的第四高度H4，如約80nm。
在一實施例中，填充材料806可以是如Al、Cu、AlCu、W、Ti、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、Ta、TaN、Co、Ni、其組合、或其他類似的材料，並可使用如電鍍法、化學氣相沉積、原子層沉積、物理氣相沉積、其組合、或類他似的沉積方法來形成填充材料806。此外，可沉積填充材料806至介於約1000Å和2000Å之間的厚度，如約1500Å。然而，任何合適的材料皆可被利用。
然而，利用於此描述的實施例，各個開口的高寬比(例如，高度和寬度的比例)可維持夠小，則不抑制填充材料806的沉積。特別的是，若高寬比過大，填充材料806的沉積製程可導致位在填充材料806內所形成的空洞，其空洞會在後續製程或操作中造成不良的狀況。然而，在各種閘極堆疊的調節中使用較少的膜層，高寬比能夠維持較低，從而得到空洞形成的機率和附帶的負面效應的減少。
第9圖繪示了，在沉積了填充材料806來填充和過渡填充開口，可平坦化在第一區302、第二區304、第三區306、和第四區308的各個開口內的材料來形成第一閘極堆疊902、第二閘極堆疊904、第三閘極堆疊906、和第四閘極 堆疊908。在一實施例中，可使用如化學機械拋光製程來將其材料與第一間隔物113平坦化，儘管任何合適的製程如研磨或蝕刻皆可被利用。
在形成和平坦化了第一閘極堆疊902、第二閘極堆疊904、第三閘極堆疊906、和第四閘極堆疊908的材料後，可凹蝕第一閘極堆疊902、第二閘極堆疊904、第三閘極堆疊906、和第四閘極堆疊908的材料，並蓋上蓋層901。在一實施例中，可使用如針對第一閘極堆疊902、第二閘極堆疊904、第三閘極堆疊906、和第四閘極堆疊908的材料具有選擇性的濕蝕刻製程或乾蝕刻製程來凹蝕第一閘極堆疊902、第二閘極堆疊904、第三閘極堆疊906、和第四閘極堆疊908的材料。在一實施例中，可凹蝕第一閘極堆疊902、第二閘極堆疊904、第三閘極堆疊906、和第四閘極堆疊908的材料至介於約5nm和150nm之間的距離，如約120nm。然而，任何合適的製程和距離皆可被利用。
一旦凹蝕了第一閘極堆疊902、第二閘極堆疊904、第三閘極堆疊906、和第四閘極堆疊908的材料，可沉積蓋層901並將其與第一間隔物113平坦化。在一實施例中，蓋層901為如氮化矽(SiN)、氧氮化矽(SiON)、氧碳氮化矽(SiCON)、碳化矽(SiC)、氧碳化矽(SiOC)、其組合、或其他類似的材料，並使用如原子層沉積、化學氣相沉積、濺鍍法、或其他類似的沉積方法來沉積蓋層901。可沉積蓋層901至介於約5Å和200Å之間的厚度，接著使用如化學機械拋光的平坦化製程來平坦化蓋層901，使蓋層901與第一間隔物113共面。
利用於此描述的實施例，能達到具有分別調節的臨界電壓的多重電晶體，而不減少各種製造過程的寬裕度。舉例來說，在第一區302內，可形成第一電晶體903，其具有包括界面層301、第一介電材料303、第一金屬材料305、第一N金屬功函數層802、黏著層804、和填充材料806的閘極堆疊。如此，對於 第一NMOS元件，第一電晶體903可具有介於約0.01V和0.15V之間的第一臨界電壓Vt1，如約0.10V。
相似地，在第二區304內，可形成第二電晶體905，其具有包括界面層301、第一介電材料303、第一金屬材料305、第一P金屬功函數層307、第一N金屬功函數層802、黏著層804、和填充材料806的閘極堆疊。如此，對於第二NMOS元件，第二電晶體905可具有介於約0.15V和0.40V之間的第二臨界電壓Vt2，如約0.25V。
此外，在第三區306內，可形成第三電晶體907，其具有包括界面層301、第一介電材料303、第一金屬材料305、第二P金屬功函數層501、第一N金屬功函數層802、黏著層804、和填充材料806的閘極堆疊。如此，對於第一PMOS元件，第三電晶體907可具有介於約0.15V和0.40V之間的第三臨界電壓Vt3，如約0.25V。
最後，在第四區308內，可形成第四電晶體909，其具有包括界面層301、第一介電材料303、第一金屬材料305、第一P金屬功函數層307、第二P金屬功函數層501、第一N金屬功函數層802、黏著層804、和填充材料806的閘極堆疊。如此，對於第二PMOS元件，第四電晶體909可具有介於約0.01V和0.15V之間的第四臨界電壓Vt4，如約0.10V。
利用於此描述的實施例，是利用多種不同的材料來調節元件的臨界電壓。藉由利用多種不同的材料，可避免相同材料(如氮化鈦)的複數層堆疊，並且相較於相同材料，可達到整體厚度的減少。如此，可減少膜層的總厚度，對後續膜層增加了間隙填充寬裕度來降低成本。這樣的減少將會形成較少的空洞，而金屬閘極能完全填充開口，進一步允許了更佳的臨界穩定度。如此， 能夠在更加狹小的臨界尺寸中(如5nm和3nm的技術節點)達成多重臨界電壓調節，又不犧牲N/P圖案化和金屬閘極間隙填充寬裕度。
在一實施例中，一種製造半導體元件的方法包括：沉積閘極介電質於第一區、第二區、第三區、和第四區上方；沉積第一金屬材料於第一區、第二區、第三區、和第四區上方；沉積第一功函數層於第一區、第二區、第三區、和第四區上方；自第三區移除第一功函數層；在移除第一功函數層之後，沉積第二功函數層於第一區、第二區、第三區、和第四區上方，第二功函數層不同於第一功函數層；自第一區和第二區移除第二功函數層；自第一區移除第一功函數層；以及在移除第一功函數層之後，沉積填充材料於第一區、第二區、第三區、和第四區上方。在一實施例中，第一功函數層包括氮化鈦。在一實施例中，第二功函數層包括鎢。在一實施例中，第二功函數層包括氧化鎢。在一實施例中，第二功函數層包括氮化鎢。在一實施例中，第二功函數層包括鉬。在一實施例中，第二功函數層包括氮化鉬。
在另一個實施例中，一種製造半導體元件的方法包括：沉積第一複數個閘極材料於第一區和第二區上方；藉由移除第一區的第一複數個閘極材料的第一閘極材料，來調節由第一複數個閘極材料所形成的多個電晶體之中的第一電晶體的第一臨界電壓；以及藉由形成第二閘極材料於第一區和第二區上方，和由第二區移除第二閘極材料，來調節由第一複數個閘極材料所形成的多個電晶體之中的第二電晶體的第二臨界電壓，第一閘極材料與第二閘極材料不同，多個電晶體之中的第一電晶體為第一PMOS電晶體，而多個電晶體之中的第二電晶體為第二PMOS電晶體。在一實施例中，沉積第二閘極材料於第一區上方包括沉積第二閘極材料與阻障層物理接觸。在一實施例中，沉積第二閘極材料 於第二區上方包括沉積第二閘極材料與在第二區中的第一閘極材料物理接觸。在一實施例中，阻障層包括氮化鉭。在一實施例中，沉積第一複數個閘極材料更包括：沉積界面層於半導體鰭片上方；以及沉積介電蓋層於界面層上方。在一實施例中，製造半導體元件的方法更包括沉積黏著層於第二閘極材料上方。在一實施例中，製造半導體元件的方法更包括沉積填充材料於黏著層上方。
而在另一個實施例中，一種半導體元件包括：第一閘極堆疊於第一半導體鰭片上方，第一閘極堆疊包括第一金屬材料；第二閘極堆疊於第二半導體鰭片上方，第二閘極堆疊包括第一金屬材料和與第一金屬材料不同的第一P金屬材料；第三閘極堆疊於第三半導體鰭片上方，第三閘極堆疊包括第一金屬材料和與第一金屬材料不同的第二P金屬材料；第四閘極堆疊於第四半導體鰭片上方，第四閘極堆疊包括第一金屬材料、第一P金屬材料、和第二P金屬材料；以及其中第一閘極堆疊、第二閘極堆疊、第三閘極堆疊、和第四閘極堆疊各包括N金屬材料，在第一閘極堆疊中的N金屬材料與第一金屬材料物理接觸，在第二閘極堆疊中的N金屬材料與第一P金屬材料物理接觸，在第三閘極堆疊中的N金屬材料與第二P金屬材料物理接觸，而在第四閘極堆疊中的N金屬材料與第二P金屬材料物理接觸。在一實施例中，第二P金屬材料包括鎢基材料。在一實施例中，第二P金屬材料包括碳氮化鎢。在一實施例中，第二P金屬材料包括鉬基材料。在一實施例中，第二P金屬材料包括氮化鉬。在一實施例中，第一P金屬材料包括氮化鈦。
以上概述數個實施例之部件，以便在本發明所屬技術領域中具有通常知識者可以更加理解本發明的觀點。在本發明所屬技術領域中具有通常知識者應理解，他們能輕易地以本發明實施例為基礎，設計或修改其他製程和結 構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解，此類等效的結構並無悖離本發明的精神與範圍，且他們能在不違背本發明之精神和範圍下，做各式各樣的改變、取代和替換。
100:半導體元件
107:鰭片
113:第一間隔物
301:界面層
302:第一區
303:第一介電材料
304:第二區
305:第一金屬材料
306:第三區
307:第一P金屬功函數層
308:第四區
501:第二P金屬功函數層
802:第一N金屬功函數層
804:黏著層
806:填充材料
901:蓋層
902:第一閘極堆疊
903:第一電晶體
904:第二閘極堆疊
905:第二電晶體
906:第三閘極堆疊
907:第三電晶體
908:第四閘極堆疊
909:第四電晶體

Claims (14)

  1. 一種半導體元件的製造方法，該方法包括：沉積一閘極介電質於一第一區、一第二區、一第三區、和一第四區上方；沉積一第一金屬材料於該第一區、該第二區、該第三區、和該第四區上方；沉積一第一功函數層於該第一區、該第二區、該第三區、和該第四區上方；從該第三區移除該第一功函數層；在移除該第一功函數層之後，沉積一第二功函數層於該第一區、該第二區、該第三區、和該第四區上方，該第二功函數層與該第一功函數層不同；從該第一區和該第二區移除該第二功函數層；沉積一黏著層於該第二功函數層上方；從該第一區移除該第一功函數層；以及在移除該第一功函數層之後，沉積一填充材料於該第一區、該第二區、該第三區、和該第四區上方。
  2. 如請求項1之半導體元件的製造方法，其中該第一功函數層包括氮化鈦。
  3. 如請求項1-2中任一項之半導體元件的製造方法，其中該第二功函數層包括鎢、氧化鎢、或氮化鎢。
  4. 如請求項1-2中任一項之半導體元件的製造方法，其中該第二功函數層包括鉬或氮化鉬。
  5. 一種半導體元件的製造方法，該方法包括：沉積一第一複數個閘極材料於一第一區和一第二區上方；藉由移除該第一區的該第一複數個閘極材料的一第一閘極材料，來調節由該 第一複數個閘極材料所形成的多個電晶體之中的一第一電晶體的一第一臨界電壓，其中沉積該第一複數個閘極材料更包括：沉積一界面層於一半導體鰭片上方；以及沉積一介電蓋層於該界面層上方；以及藉由形成一第二閘極材料於該第一區和該第二區上方，和由該第二區移除該第二閘極材料，來調節由該第一複數個閘極材料所形成的多個電晶體之中的一第二電晶體的一第二臨界電壓，該第一閘極材料與該第二閘極材料不同，所述多個電晶體之中的該第一電晶體為一第一PMOS電晶體，而所述多個電晶體之中的該第二電晶體為一第二PMOS電晶體。
  6. 如請求項5之半導體元件的製造方法，其中沉積該第二閘極材料於該第一區上方包括沉積該第二閘極材料與一阻障層物理接觸。
  7. 如請求項6之半導體元件的製造方法，其中沉積該第二閘極材料於該第二區上方包括沉積該第二閘極材料與在該第二區中的該第一閘極材料物理接觸。
  8. 如請求項7之半導體元件的製造方法，其中該阻障層包括氮化鉭。
  9. 如請求項5-8中任一項之半導體元件的製造方法，更包括沉積一黏著層於該第二閘極材料上方。
  10. 如請求項9之半導體元件的製造方法，更包括沉積一填充材料於該黏著層上方。
  11. 一種半導體元件，包括：一第一閘極堆疊，於一第一半導體鰭片上方，該第一閘極堆疊包括一第一金屬材料； 一第二閘極堆疊，於一第二半導體鰭片上方，該第二閘極堆疊包括該第一金屬材料和與該第一金屬材料不同的一第一P金屬材料；一第三閘極堆疊，於一第三半導體鰭片上方，該第三閘極堆疊包括該第一金屬材料和與該第一金屬材料不同的一第二P金屬材料；一第四閘極堆疊，於一第四半導體鰭片上方，該第四閘極堆疊包括該第一金屬材料、該第一P金屬材料、和該第二P金屬材料；一黏著層，於該第二P金屬材料上方；以及其中該第一閘極堆疊、該第二閘極堆疊、該第三閘極堆疊、和該第四閘極堆疊各包括一N金屬材料，在該第一閘極堆疊中的該N金屬材料與該第一金屬材料物理接觸，在該第二閘極堆疊中的該N金屬材料與該第一P金屬材料物理接觸，在該第三閘極堆疊中的該N金屬材料與該第二P金屬材料物理接觸，而在該第四閘極堆疊中的該N金屬材料與該第二P金屬材料物理接觸。
  12. 如請求項11之半導體元件，其中該第二P金屬材料包括一鎢基材料。
  13. 如請求項11之半導體元件，其中該第二P金屬材料包括一鉬基材料。
  14. 如請求項11之半導體元件，其中該第一P金屬材料包括氮化鈦。
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